KR940012554A - 와이어 본딩시 본딩 다이어그램 자동 메모리 방법 - Google Patents

와이어 본딩시 본딩 다이어그램 자동 메모리 방법 Download PDF

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Publication number
KR940012554A
KR940012554A KR1019920022846A KR920022846A KR940012554A KR 940012554 A KR940012554 A KR 940012554A KR 1019920022846 A KR1019920022846 A KR 1019920022846A KR 920022846 A KR920022846 A KR 920022846A KR 940012554 A KR940012554 A KR 940012554A
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South Korea
Prior art keywords
pad
bonding
post
memory
selecting
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KR1019920022846A
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English (en)
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KR960006431B1 (ko
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명수동
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김주용
현대전자산업 주식회사
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Priority to KR1019920022846A priority Critical patent/KR960006431B1/ko
Publication of KR940012554A publication Critical patent/KR940012554A/ko
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Publication of KR960006431B1 publication Critical patent/KR960006431B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 와이어 본딩시 본딩 다이어그램 자동 메모리방법에 관한 것으로, 종래에는 실제 본딩할 위치를 메모리하는 과정에서 매 와이어마다 본드 포인트1과 본드 포인트2를 지정해주고 있어 하이리드인 경우 시간이 많이 소요되고, 메모리 종료후 패드의 중앙에 본딩이 되도록 수정을 해야 하며, 사람의 실수로 인하여 잘못 패드와 포스트간을 연결할 경우 부정확한 본드를 발생시켜 정확도가 떨어지는 문제점이 있었다. 본 발명은 이와같은 문제점을 감안하여, 카메라에서 본딩 다이어그램을 읽는 순간에 모니터에 읽는 부분이 나타나며, 그것이 마이크로프로세서에 의하여 위치가 결정되고, 그 결정된 위치를 롬에 저장된 프로그램에 의해 자동으로 램에 메모리시킴으로써, 메모리시 소요되는 패드와 포스트간의 위치 지정시간을 단축하고, 사람의 실수로 인한 부정확한 본드를 예방할수 있어 정확히 메모리할수 있으며, 누구나 손쉽게 메모리할수 있게 된다.

Description

와이어 본딩시 본딩 다이어그램 자동 메모리 방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명을 위한 본딩 다이어그램 일예시도.
제6도는 본 발명 와이어 본딩시 본딩 다이어그램 자동 메모리 방법 동작 순서도이다.

Claims (3)

  1. 와이어 본딩시 본딩 다이어그램 메모리 방법에 있어서, 시스템 수의 선정으로 실제 본딩할 위치가 몇 개인가 선정하고, 기준점인 XYO를 선정하는 제1단계(100)와; 기준점 선정후 각 시스템마다 레퍼런스 포인트 및 아이 포인트의 위치를 선정하는 제2단계(200)와; 각 위치 선정후 롬(27)에 저장된 프로그램에 의해 실제로 본딩할 위치로 자동으로 램(26)에 메모리하는 제3단계(310)로 동작함을 특징으로 하는 와이어 본딩시 본딩 다이어그램 자동 메모리방법.
  2. 제1항에 있어서, 제3단계(310)는 패드(11)를 보여준다고 지시한후 첫 번째 패드(11-1)부터 순서대로 패드(11) 전체를 보여주는 단계(311)와; 패드(11)를 보여주는 것이 종료되면, 마지막 패드(11-N)에서 패드(11)가 종료되었음을 지시한후, 포스트(8)를 보여준다고 지시하는 단계(312)와; 첫 패드(11-1)와 연결되는 첫 번째 포스트(8-1)를 기점으로하여 순서대로 포스트(8) 전체를 보여주는 단계(313)와; 포스트(8)를 보여주는 것이 종료되면 마지막 포스트(8-N)에서 포스트(8)가 종료되었음을 지시하는 단계(314)로 동작하여 메모리를 종료함을 특징으로 하는 와이어 본딩시 본딩 다이어그램 자동 메모리방법.
  3. 제2항에 있어서, 제3단계(310)의 메모리 순서는 내부 리드(5)의 포스트(8)에서 칩(9)의 패드(11)로 본딩할 경우, 내부 리드(5)의 포스트(8)를 먼저 보여주는 단계(313)를 1차적으로 수행하고; 칩(9)의 패드(11)에서 내부 리드(5)의 포스트(8)로 본딩할 경우, 칩(9)의 패드(11)를 먼저 보여주는 단계(311)를 1차적으로 수행하도록 선택하여 유동적으로 순서를 변경함을 특징으로 하는 와이어 본딩시 다이어그램 자동 메모리 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920022846A 1992-11-30 1992-11-30 와이어 본딩시 본딩 다이어그램 자동 메모리 방법 KR960006431B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920022846A KR960006431B1 (ko) 1992-11-30 1992-11-30 와이어 본딩시 본딩 다이어그램 자동 메모리 방법

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KR1019920022846A KR960006431B1 (ko) 1992-11-30 1992-11-30 와이어 본딩시 본딩 다이어그램 자동 메모리 방법

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KR940012554A true KR940012554A (ko) 1994-06-23
KR960006431B1 KR960006431B1 (ko) 1996-05-15

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