KR940010869A - 질화알루미늄회로기판 및 그 제조방법 - Google Patents

질화알루미늄회로기판 및 그 제조방법 Download PDF

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KR940010869A
KR940010869A KR1019930014823A KR930014823A KR940010869A KR 940010869 A KR940010869 A KR 940010869A KR 1019930014823 A KR1019930014823 A KR 1019930014823A KR 930014823 A KR930014823 A KR 930014823A KR 940010869 A KR940010869 A KR 940010869A
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South Korea
Prior art keywords
aluminum nitride
green sheet
circuit board
titanium
copper
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KR1019930014823A
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English (en)
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KR0125101B1 (ko
Inventor
미찌오 호리우찌
요이찌 하라야마
고이찌로오 하야시
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이노우에 사다오
신꼬오 덴기 고오교오 가부시끼가이샤
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Publication of KR940010869A publication Critical patent/KR940010869A/ko
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Publication of KR0125101B1 publication Critical patent/KR0125101B1/ko

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867Applying pastes or inks, e.g. screen printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0302Properties and characteristics in general
    • H05K2201/0317Thin film conductor layer; Thin film passive component

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Ceramic Products (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

본 발명은 질화알루미늄 세라믹과 도체부의 계면에서의 접합성을 양호하게 하고 내부도체 배선의 단선을 없게 하는 동시에 회로기판의 기계적 강도를 향상시킴을 목적으로 한다.
본 발명은 질화알루미늄의 그린쉬트에 동을 주성분으로하고 주기율표 제 IVa족의 금속 또는 금속화합물을 첨가한 동페이스트를 사용하여 평면배선, 비어등의 도체배선부를 설비하고 이 도체배선부를 설비한 그린쉬트의 외표면에 별개의 그린쉬트를 적층하여 상기 그린쉬트의 외표면에 노출되는 상기 도체배선부를 보호 그린쉬트로 덮어서 일체화하고 소정처리 및 소성조건에 의해서 소결시킨후에 소결체의 상기 외표면을 덮는 외층부를 연삭·연마하여 제거하는 것을 특징으로 한다.

Description

질화알루미늄회로기판 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 질화알루미늄 회로기판의 일실시예의 내부도체부의 단면에 있어서의 입자구조를 나타낸 사진,
제2도는 질화알루미늄 회로기판의 다른 실시예의 내부도체부의 단면에 있어서의 입자구조를 나타낸 사진,
제3도는 질화알루미늄 회로기판의 비어의 횡단면에서의 동, 알루미늄, 티탄의 선분석결과를 나타낸 그래프.

Claims (5)

  1. 질화알루미늄의 소성온도보다드 융점이 낮은 금속을 배선재료로써 내부도체부를 형성한 질화알루미늄 회로기판에 있어서, 상기 내부도체부가 동을 주성분으로하고 질화알루미늄과 동과의 계면에 주기율표 제 IVa족을 주성분으로 하는 층이 형성된 것을 특징으로 하는 질화알루미늄 회로기판.
  2. 제1항에 있어서, 상기 질화알루미늄과 동과의 계면에 티탄을 주성분으로하는 층이 형성된 것을 특징으로 하는 질화 알루미늄 회로기판.
  3. 질화알루미늄의 그린쉬트에 동을 주성분으로 하고 주기율표 제IVa족의 금속 또는 금속화합물을 첨가한 동페이스트를 사용하여 평면배선, 비어등의 도체배선부를 설비하고, 상기 도체배선부를 설비한 그린쉬트의 외표면에 별개의 그린쉬트를 적층하여 상기 그린쉬트의 외표면에 노출되는 상기 도체배선부를 보호그린쉬트로 덮어서 일체화하고 소정처리 및 소정조건에 의해서 소결시킨후에 소결체의 상기 외표면을 덮는 외충부를 연삭·연마하여 제거하는 것을 특징으로 하는 질화알루미늄 회로기판의 제조방법.
  4. 제3항에 있어서, 상기 동페이스로써 동을 주성분으로 하고 금속티탄 또는 티탄화합물을 금속티탄환산으로 0.2중량% 이상 20중량% 이하의 이율로 함유하는 페이스트를 사용하는 것을 특징으로 하는 질화알루미늄 회로기판의 제조방법.
  5. 제4항에 있어서, 상기 티탄성분이 금속티탄, 2붕화티탄, 2산화티탄중의 1종인 것을 특징으로 하는 질화알루미늄 회로기판의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930014823A 1992-10-12 1993-07-31 질화알루미늄 회로기판 및 그 제조방법 KR0125101B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP4299192A JPH06125153A (ja) 1992-10-12 1992-10-12 窒化アルミニウム回路基板及びその製造方法
JP93-299192 1992-10-12
JP92-299192 1992-10-12

Publications (2)

Publication Number Publication Date
KR940010869A true KR940010869A (ko) 1994-05-26
KR0125101B1 KR0125101B1 (ko) 1997-12-04

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KR1019930014823A KR0125101B1 (ko) 1992-10-12 1993-07-31 질화알루미늄 회로기판 및 그 제조방법

Country Status (2)

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JP (1) JPH06125153A (ko)
KR (1) KR0125101B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100261793B1 (ko) * 1995-09-29 2000-07-15 니시무로 타이죠 고강도 고신뢰성 회로기판 및 그 제조방법

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3537648B2 (ja) * 1997-10-28 2004-06-14 京セラ株式会社 窒化アルミニウム質配線基板及びその製造方法
JP3538549B2 (ja) * 1998-08-31 2004-06-14 京セラ株式会社 配線基板およびその製造方法
US7868358B2 (en) * 2003-06-06 2011-01-11 Northrop Grumman Systems Corporation Coiled circuit device with active circuitry and methods for making the same
EP1636837B1 (en) * 2003-06-06 2011-10-05 Northrop Grumman Systems Corporation Coiled circuit device and method of making the same
JP6526888B1 (ja) * 2018-08-01 2019-06-05 Jx金属株式会社 セラミックス層と銅粉ペースト焼結体の積層体
CN111556655A (zh) * 2020-04-28 2020-08-18 重庆市澳欧硕铭科技有限公司 基于氮化铝板的pcb板制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100261793B1 (ko) * 1995-09-29 2000-07-15 니시무로 타이죠 고강도 고신뢰성 회로기판 및 그 제조방법

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KR0125101B1 (ko) 1997-12-04
JPH06125153A (ja) 1994-05-06

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