KR940005196A - 혼성 집적 회로 장치 - Google Patents

혼성 집적 회로 장치 Download PDF

Info

Publication number
KR940005196A
KR940005196A KR1019930016750A KR930016750A KR940005196A KR 940005196 A KR940005196 A KR 940005196A KR 1019930016750 A KR1019930016750 A KR 1019930016750A KR 930016750 A KR930016750 A KR 930016750A KR 940005196 A KR940005196 A KR 940005196A
Authority
KR
South Korea
Prior art keywords
current
insulating resin
pattern
conductive path
bonding pad
Prior art date
Application number
KR1019930016750A
Other languages
English (en)
Other versions
KR100223504B1 (ko
Inventor
료이치 다까하시
가쯔미 오까와
유스께 이가라시
Original Assignee
다까노 야스아끼
상요덴기 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP4229960A external-priority patent/JP2869261B2/ja
Priority claimed from JP4247913A external-priority patent/JP2975778B2/ja
Priority claimed from JP4252899A external-priority patent/JP2902871B2/ja
Priority claimed from JP4258379A external-priority patent/JP2989390B2/ja
Priority claimed from JP4258374A external-priority patent/JP2846776B2/ja
Priority claimed from JP4258376A external-priority patent/JP2962945B2/ja
Application filed by 다까노 야스아끼, 상요덴기 가부시끼가이샤 filed Critical 다까노 야스아끼
Publication of KR940005196A publication Critical patent/KR940005196A/ko
Application granted granted Critical
Publication of KR100223504B1 publication Critical patent/KR100223504B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/01Mounting; Supporting
    • H01C1/012Mounting; Supporting the base extending along and imparting rigidity or reinforcement to the resistive element
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0234Resistors or by disposing resistive or lossy substances in or near power planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/647Resistive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12035Zener diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10439Position of a single component
    • H05K2201/10477Inverted
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/049Wire bonding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Abstract

과전류를 검출하는데 온도 변화에 대해 매우 안정한 상태에서 전류 검출이 가능한 혼성 집적 회로 장치를 제공하는 것을 목적으로 한다.
금속 기판(1)상에, 절연 수지층(2)를 통해 형성된 도전로(3)에 전류 검출용 저항 소자(5)를 포함하는 복수의 회로 소자(4 및 7)에 접속된 혼성 집적 회로 장치의 전류 검출용 저항 소자(5)에 금속편(5B)의 한 주면상에 수지막(5C)를 개재하여 온도 계수가 약 1ppm∼500ppm인 합금재로 저항 패턴(5A)가 형성된 저항체 부품을 이용해서, 주변의 도전로(3)과 와이어 접속한다.

Description

혼성 집적 회로 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 제1발명의 혼성 집적 회로 장치를 도시하는 사시 확대도,
제2도는 본 발명에서 사용되는 인버터 회로를 도시하는 도면,
제3도는 제2발명의 혼성 집적 회로 장치를 도시하는 사시 확대도,
제4도는 제2발명을 설명하기 위한 도면.

Claims (6)

  1. 금속 기판상에 절연 수지층을 개재하여 동박으로 형성된 원하는 형상의 도전로에 저항 소자를 포함하는 복수의 회로 소자가 접속된 혼성 집적 회로 장치에 있어서. 상기 저항 소자는 금속편의 한 주면상에 절연 수지막을 개재하여 소정 형성의 저항 패턴이 형성되고, 그 저항 패턴의 연장선 상에 2개 이상의 본딩용 패드를 가진 저항체 부품으로, 상기 저항체 부품을 상기 기판상에 탑재하고, 상기 저항체 부품 근방에 뻗는 도전로와 상기 저항체 부품의 본딩 패드를 와이어 본딩 접속한 것을 특징으로 하는 혼성 집적 회로 장치.
  2. 금속 기관상에 절연 수지층을 개재하여 동박으로 형성된 원하는 형상의 도전로에 금속편의 한 주면상에 절연수지막을 개재하여 전류를 흘리는 전류용 패턴의 양단부에 설치된 전류용 본딩 패드화 상기 전류용 패턴에 흐르는 전류를 검출하기 위한 전압 검출용 본딩 패드를 가진 저항 패턴이 형성된 저항체 부품 및 복수의 회로 소자가 접속된 흔성 집적 회로장치에 있어서, 상기 전류용 패턴은 그 패턴에 흐르는 전류의 전류경로가 균일해지도록 형성되고, 상기 저항체 부품의 본딩 패드와 그 근방에 뻗는 상기 도전로를 와이어 본딩 접속한 것을 특징으로 하는 혼성 집적 회로 장치.
  3. 금속 기판상에 절연 수지층을 개재하여 동박으로 형성된 원하는 형상의 도전로에 금속편의 한 주면상에 절연 수지막을 개재하여 전류를 흘리는 전류용 패턴의 양단부에 설치된 전류용 본딩 패드와 상기 전류용 패턴에 흐르는 전류를 검출하기 위한 전압 검출용 본딩 패드를 가진 저항 패턴이 형성된 저항체 부품 및 복수의 회로 소자가 접속된 혼성 집적 회로장치에 있어서, 상기 전류용 본딩 패드와 상기 전압 검출용 본딩 패드의 주변 근방에 상기 도전로가 각각 뻗어있고, 상기 양 본딩 패드와 상기 도전로를 접속하는 본딩 와이어선이 다른 방향에서 본딩 접속되는 것을 특징으로 하는 혼성 집적 회로 장치.
  4. 금속 기판상에 절연 수지층를 개재하여 동박으로 형성된 원하는 형상의 도전로에 금속편의 한 주면상에 절연수지막을 개재하여 전류를 흘리는 전류용 패턴의 양단부가 설치된 전류용 본딩 패드와 상기 전류용 패턴에 흐르는 전류를 검출하기 위한 전압 검출용 본딩 패드를 가진 저항 패턴이 형성된 저항체 부품 및 복수의 회로 소자가 접속된 혼성 집적 회로장치에 있어서, 상기 저항체 부품은 상기 하나 이상의 전류용 본딩 패드와 접속되는 도전로가 뻗어서 형성된 고착 패드상에 탑재되고, 상기 저항체 부품의 각 본딩 패드와, 상기 고착 패드의 근방에 뻗어있는 상기 도전로를 와이어 본딩 접속한 것을 특징으로 하는 혼성 집적 회로 장치.
  5. 금속 기판상에 절연 수지층을 개재하여 동박으로 형성된 원하는 형상의 도전로에 전류 검출용 저항 소자를 포함하는 복수의 회로 소자가 접속된 혼성 집적 회로 장치에 있어서, 상기전류 검출용 저항 소자의 금속편의 한 주면상에 절연 수지막을 개재하여 원하는 형상의 저항 패턴이 형성되고, 그 저항 패턴의 연장선상에 복수의 전류용 본딩 패드 및 상기 저항 패턴의 저항값을 달리하는 1쌍의 복수의 전압 검출용 본딩 패드를 가진 저항체 부품으로, 상기 저항체 부분이 탑재되는 그 근방에 뻗어 배치된 전력용 및 소신호용 도전로와 상기 전류용 본딩 패드 및 전압 검출용 본딩 패드를 와이어 본딩 접속한 것을 특징으로 하는 혼성 집적 회로 장치.
  6. 금속 기판상에 절연 수지층을 개재하여 동박으로 형성된 원하는 형상의 도전로에 전류 검출용 저항 소자를 포함하는 복수의 횔 소자가 접속된 혼성 집적 회로 장치에 있어서, 상기 전류 검출용 저항 소자는 금속편의 한 주면상에 절연 수지막을 개재하여 저항 온도 계수가 약 1ppm∼500ppm인 합금재로 이루어지는 원하는 형상의 저항 패턴이 형성되고, 이 저항 패턴의 연장선상에 2개 이상의 전류용 및 전압 검출용 패드를 가진 저항체 부품으로 이 저항체 부품을 상기 기판상에 표면 실장하며, 상기 저항체 부품을 열전도성에 양호한 절연성 수지로 피복한 것을 특징으로 하는 혼성 집적 회로 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930016750A 1992-08-28 1993-08-27 혼성 집적 회로 장치 KR100223504B1 (ko)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
JP92-229960 1992-08-28
JP4229960A JP2869261B2 (ja) 1992-08-28 1992-08-28 混成集積回路装置
JP92-247913 1992-09-17
JP4247913A JP2975778B2 (ja) 1992-09-17 1992-09-17 混成集積回路装置
JP92-252899 1992-09-22
JP4252899A JP2902871B2 (ja) 1992-09-22 1992-09-22 混成集積回路装置
JP4258379A JP2989390B2 (ja) 1992-09-28 1992-09-28 混成集積回路装置
JP92-258374 1992-09-28
JP92-258376 1992-09-28
JP4258374A JP2846776B2 (ja) 1992-09-28 1992-09-28 混成集積回路装置
JP4258376A JP2962945B2 (ja) 1992-09-28 1992-09-28 混成集積回路装置
JP92-258379 1992-09-28

Publications (2)

Publication Number Publication Date
KR940005196A true KR940005196A (ko) 1994-03-16
KR100223504B1 KR100223504B1 (ko) 1999-10-15

Family

ID=27554037

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930016750A KR100223504B1 (ko) 1992-08-28 1993-08-27 혼성 집적 회로 장치

Country Status (2)

Country Link
US (1) US5469131A (ko)
KR (1) KR100223504B1 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675310A (en) * 1994-12-05 1997-10-07 General Electric Company Thin film resistors on organic surfaces
US5683928A (en) * 1994-12-05 1997-11-04 General Electric Company Method for fabricating a thin film resistor
US6040226A (en) * 1997-05-27 2000-03-21 General Electric Company Method for fabricating a thin film inductor
JP3803025B2 (ja) * 2000-12-05 2006-08-02 富士電機ホールディングス株式会社 抵抗器
JP2004241416A (ja) * 2003-02-03 2004-08-26 Alps Electric Co Ltd 電子回路ユニットおよびその製造方法
JP4342232B2 (ja) * 2003-07-11 2009-10-14 三菱電機株式会社 半導体パワーモジュールおよび該モジュールの主回路電流値を計測する主回路電流計測システム
JP4452196B2 (ja) * 2004-05-20 2010-04-21 コーア株式会社 金属板抵抗器
JP4595665B2 (ja) * 2005-05-13 2010-12-08 富士電機システムズ株式会社 配線基板の製造方法
JP2008118067A (ja) * 2006-11-08 2008-05-22 Hitachi Ltd パワーモジュール及びモータ一体型コントロール装置
WO2016027692A1 (ja) 2014-08-18 2016-02-25 株式会社村田製作所 電子部品および電子部品の製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5469768A (en) * 1977-11-14 1979-06-05 Nitto Electric Ind Co Printing circuit substrate with resistance
US4196411A (en) * 1978-06-26 1980-04-01 Gentron Corporation Dual resistor element
DE2919433A1 (de) * 1979-05-15 1980-12-04 Bosch Gmbh Robert Messonde zur messung der masse und/oder temperatur eines stroemenden mediums und verfahren zu ihrer herstellung
FR2516739A1 (fr) * 1981-11-17 1983-05-20 Rhone Poulenc Spec Chim Procede de fabrication de circuits electroniques de type hybride a couches epaisses, des moyens destines a la mise en oeuvre de ce procede et les circuits obtenus selon ce procede
US5262615A (en) * 1991-11-05 1993-11-16 Honeywell Inc. Film resistor made by laser trimming

Also Published As

Publication number Publication date
US5469131A (en) 1995-11-21
KR100223504B1 (ko) 1999-10-15

Similar Documents

Publication Publication Date Title
JPH0627959Y2 (ja) ダイオード
USRE39660E1 (en) Surface mounted four terminal resistor
KR970701352A (ko) 전기적 파라미터를 감지하는 합체형 저항기(an integrated resistor for sensing electrical parameters)
EP0780899B1 (en) Semiconductor assembly
KR960019670A (ko) 반도체칩 패키지 및 그의 제조 방법
KR940005196A (ko) 혼성 집적 회로 장치
US6181234B1 (en) Monolithic heat sinking resistor
US6082609A (en) Process for producing a sensor arrangement for measuring temperature
KR950028575A (ko) 파워혼성집적회로장치
JP2002184601A (ja) 抵抗器
KR960043165A (ko) 다수의 보호 소자를 포함하는 정전기 보호 회로
WO1998020718A1 (en) Heat sink-lead frame structure
JP3670593B2 (ja) 抵抗器を用いる電子部品及びその使用方法
US5495223A (en) Hybrid integrated circuit device
JP2989390B2 (ja) 混成集積回路装置
JPH033262A (ja) 半導体装置
WO2021111952A1 (ja) 流量センサ
JPH06260730A (ja) プリント配線基板
JP2001358283A (ja) 電流シャント及びそれを使用した複合半導体装置
KR960019683A (ko) 반도체 장치
JP2975778B2 (ja) 混成集積回路装置
WO2023199611A1 (ja) シャント抵抗器およびシャント抵抗装置
JP3477002B2 (ja) 半導体装置
JP2500773Y2 (ja) 半導体装置
US20020093417A1 (en) Electrical resistor with thermal voltage prevention

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070625

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee