KR940004855A - LDD MOSFET Manufacturing Method - Google Patents

LDD MOSFET Manufacturing Method Download PDF

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Publication number
KR940004855A
KR940004855A KR1019920015700A KR920015700A KR940004855A KR 940004855 A KR940004855 A KR 940004855A KR 1019920015700 A KR1019920015700 A KR 1019920015700A KR 920015700 A KR920015700 A KR 920015700A KR 940004855 A KR940004855 A KR 940004855A
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KR
South Korea
Prior art keywords
oxide film
forming
ldd
film
exposed
Prior art date
Application number
KR1019920015700A
Other languages
Korean (ko)
Other versions
KR950005475B1 (en
Inventor
정재관
엄재철
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920015700A priority Critical patent/KR950005475B1/en
Priority to US08/113,988 priority patent/US5523250A/en
Publication of KR940004855A publication Critical patent/KR940004855A/en
Application granted granted Critical
Publication of KR950005475B1 publication Critical patent/KR950005475B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G03F7/2014—Contact or film exposure of light sensitive plates such as lithographic plates or circuit boards, e.g. in a vacuum frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 고집적 반도체 소자의 LDD MOSFET 제조방법에 관한 것으로, 소바분리 산화막의 버즈비크와 LDD 영역이 인접한 부분이 소정의 식각공정에서 손상되는 것을 방지하여 소오스/드레인 접합 파괴전압이 약화되는 것을 해결하는 기술에 관한 것이다.The present invention relates to a method for fabricating an LDD MOSFET of a highly integrated semiconductor device, which solves that source / drain junction breakdown voltage is weakened by preventing the adjacent portions of the soda-separated oxide film from damaging the portion of the buzz beak and the LDD region in a predetermined etching process. It's about technology.

Description

저도핑 드레인구조를 가진 금속산화물 반도체 전계효과 트랜지스터(LDD MOSFET) 제조방법Manufacturing method of metal oxide semiconductor field effect transistor (LDD MOSFET) with low doping drain structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4a도 내지 제4d도는 본발명에 의해 LDD MOSFET를 제조하는 단계를 도시한 단면도.4A to 4D are cross-sectional views showing steps of manufacturing an LDD MOSFET according to the present invention.

Claims (1)

반도체 소자의 저도핑 드레인구조를 가진 금속산화물 반도체 전계효과 트랜지스터(LDD MOSFET)제조방법에 있어서, 실리콘 기판의 예정된 부분에 소자분리 산화막을 형성하고, 노출된 실리콘 기판 상에 게이트 산화막을 형성하고, 예정된 부분에 게이트 전극을 형성하는 단계와, 상기 게이트 전극 상부에 폴리 산화막을 형성한후 저농도 불순물을 이온주입하여 LDD영역을 형성하고, 전체구조 상부에 예정된 두께의 산화막을 형성하는 단계와, 상기 산화막 상부에 감광막을 도포한 다음, 산화막 패턴 마스크를 이용한 노광 및 현상 공정으로 소자분리 산화막의 버즈비크가 충분하게 덮이는 감광막 패턴을 형성하는 단계와, 노출된 산화막을 비등방성식각공정으로 식각하여 소자분리 산화막의 버즈비크는 덮히고, 액티브 영역은 노출되는 산화막 패턴 및 게이트 스페이서를 형성한후, 감광막 패턴을 제거하는 단계와, 고농도 불순물을 이온주입 및 열처리 공정으로 소오스/드레인 영역을 LDD영역 내에서 형성되도록 하는 것을 특징으로 하는 저도핑 드레인구조를 가진 금속산화물 반도체 전계효과 트랜지스터(LDD MOSFET) 제조방법.In a method of manufacturing a metal oxide semiconductor field effect transistor (LDD MOSFET) having a low doping drain structure of a semiconductor device, a device isolation oxide film is formed on a predetermined portion of a silicon substrate, a gate oxide film is formed on an exposed silicon substrate, and Forming a LDD region by forming a gate electrode in a portion, forming a poly oxide film on the gate electrode, and implanting low concentration impurities into the LDD region, and forming an oxide film having a predetermined thickness on the entire structure; Applying a photoresist film to the photoresist layer, and then forming a photoresist pattern in which the Buzzbee of the oxide film is sufficiently covered by an exposure and development process using an oxide film mask, and etching the exposed oxide film by an anisotropic etching process. The oxide pattern and gay film of the oxide film is covered with the Buzzbeek and the active area is exposed. After forming the spacer, the photoresist pattern is removed, and the source / drain regions are formed in the LDD region by ion implantation and heat treatment of high concentration impurities. Method for manufacturing transistor (LDD MOSFET). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920015700A 1992-08-31 1992-08-31 Making method of ldd mosfet KR950005475B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920015700A KR950005475B1 (en) 1992-08-31 1992-08-31 Making method of ldd mosfet
US08/113,988 US5523250A (en) 1992-08-31 1993-08-30 Method of manufacturing a MOSFET with LDD regions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920015700A KR950005475B1 (en) 1992-08-31 1992-08-31 Making method of ldd mosfet

Publications (2)

Publication Number Publication Date
KR940004855A true KR940004855A (en) 1994-03-16
KR950005475B1 KR950005475B1 (en) 1995-05-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920015700A KR950005475B1 (en) 1992-08-31 1992-08-31 Making method of ldd mosfet

Country Status (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100377861B1 (en) * 2000-07-07 2003-03-29 한학수 A composition for forming dielectric thin film or thin film-type package on electronic device or chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100377861B1 (en) * 2000-07-07 2003-03-29 한학수 A composition for forming dielectric thin film or thin film-type package on electronic device or chip

Also Published As

Publication number Publication date
KR950005475B1 (en) 1995-05-24

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