KR960026554A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR960026554A
KR960026554A KR1019940035151A KR19940035151A KR960026554A KR 960026554 A KR960026554 A KR 960026554A KR 1019940035151 A KR1019940035151 A KR 1019940035151A KR 19940035151 A KR19940035151 A KR 19940035151A KR 960026554 A KR960026554 A KR 960026554A
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KR
South Korea
Prior art keywords
semiconductor substrate
semiconductor device
channel stop
forming
manufacturing
Prior art date
Application number
KR1019940035151A
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Korean (ko)
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940035151A priority Critical patent/KR960026554A/en
Publication of KR960026554A publication Critical patent/KR960026554A/en

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Abstract

본 발명은 고집적 반도체소자 제조방법에 관한 것으로, 특히 채널스톱 임플란트를 반도체기판으로 O2 +이온영역과 채널스톱 임플란트를 이온주입하여 반도체기판에 O2 +이온영역과 채널스톱 임플란트 영역을 형성하여 소자격리 기능을 하도록 하는 기술로 넓은 면적의 액티브영역을 얻을 수 있으며 소자분리산화막을 형성하지 않음으로 인하여 토폴로지에 의한 영향을 배재할 수 있다.The present invention relates to a method for fabricating a highly integrated semiconductor device, and in particular, an O 2 + ion region and a channel stop implant are implanted into a semiconductor substrate using a channel stop implant to form an O 2 + ion region and a channel stop implant region on a semiconductor substrate. It is possible to obtain the active area of a large area through isolation technology and to exclude the influence of topology by not forming the device isolation oxide film.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도 내지 제6도는 본 발명의 실시예에 의해 반도체소자의 소자분리 기능을 갖는 채널스톱 임플란트 영역을 형성하는 단계를 도시한 단면도.4 to 6 are cross-sectional views showing the step of forming a channel stop implant region having a device isolation function of a semiconductor device according to an embodiment of the present invention.

Claims (4)

반도체소자 제조방법에 있어서, 반도체기판상부에 산화막을 형성하고, 그 상부에 소자분리막 마스크용 감광막패턴을 형성하는 단계와, O2 +이온을 반도체기판에 이온주입하는 단계와, 채널스톱 임플란트를 반도체기판으로 이온주입하는 단계와, 상기 감광막패턴을 제거한 다음, 열처리공정으로 상기 이온주입된 이온들을 기판하부로 확산시켜 O2 +이온영역과 그 하부에 채널스톱 임플란트 영역을 형성하는 단계를 포함하여 소자격리 기능을 하도록 하는 것을 특징으로 하는 반도체소자 제조방법.A method of manufacturing a semiconductor device, comprising: forming an oxide film on a semiconductor substrate, forming a photoresist pattern for a device isolation mask thereon, implanting O 2 + ions into the semiconductor substrate, and forming a channel stop implant in the semiconductor substrate device, including the steps of forming a removal of the photoresist pattern and then, by diffusion of the implanted ions in the heat treatment process to the substrate a lower O 2 + ion region and the channel stop implant region in a lower portion of the ion implantation to the substrate A method of manufacturing a semiconductor device, characterized in that the isolation function. 제1항에 있어서, 상기 O2 +이온영역은 반도체기판의 표면에서 0.3 내지 1.5㎛의 깊이로 형성되도록 하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1 wherein the O 2 + ion region is method of manufacturing a semiconductor device characterized in that to form a 0.3 to 1.5㎛ depth from the surface of the semiconductor substrate. 제1항에 있어서, 상기 반도체기판에 N-MOS트랜지스터가 형성되는 경우에 채널스톱 임플란트를 1×1013/㎠ 내지 1×1014/㎠의 농도를 갖는 BF2로 이온주입하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein when the N-MOS transistor is formed on the semiconductor substrate, the channel stop implant is ion implanted with BF 2 having a concentration of 1 × 10 13 / cm 2 to 1 × 10 14 / cm 2 . Semiconductor device manufacturing method. 제1항에 있어서, 상기 반도체기판에 P-MOS트랜지스터가 형성되는 경우에 임플란트를 N형 불순물로 이온주입하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the implant is ion implanted with an N-type impurity when a P-MOS transistor is formed on the semiconductor substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035151A 1994-12-19 1994-12-19 Semiconductor device manufacturing method KR960026554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940035151A KR960026554A (en) 1994-12-19 1994-12-19 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940035151A KR960026554A (en) 1994-12-19 1994-12-19 Semiconductor device manufacturing method

Publications (1)

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KR960026554A true KR960026554A (en) 1996-07-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940035151A KR960026554A (en) 1994-12-19 1994-12-19 Semiconductor device manufacturing method

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KR (1) KR960026554A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382556B1 (en) * 2001-06-27 2003-05-09 주식회사 하이닉스반도체 Method for manufacturing isolation of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382556B1 (en) * 2001-06-27 2003-05-09 주식회사 하이닉스반도체 Method for manufacturing isolation of semiconductor device

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