KR970054108A - Manufacturing Method of Semiconductor Memory Device - Google Patents

Manufacturing Method of Semiconductor Memory Device Download PDF

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Publication number
KR970054108A
KR970054108A KR1019950065898A KR19950065898A KR970054108A KR 970054108 A KR970054108 A KR 970054108A KR 1019950065898 A KR1019950065898 A KR 1019950065898A KR 19950065898 A KR19950065898 A KR 19950065898A KR 970054108 A KR970054108 A KR 970054108A
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KR
South Korea
Prior art keywords
photoresist pattern
forming
region
pattern
oxide film
Prior art date
Application number
KR1019950065898A
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Korean (ko)
Inventor
조강식
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950065898A priority Critical patent/KR970054108A/en
Publication of KR970054108A publication Critical patent/KR970054108A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 메모리 장치의 제조방법에 관한 것으로서, 특히 셀영역과 주변영역을 가지는 반도체 메모리 장치의 베조 방법에 있어서, 피형 반도체 기판 상에 산화막을 형성한 후에 셀영역과 주변영역의 엔형 웰 형성을 위한 포토 레지스터 패턴을 형성하고 형성된 제1포토 레지스터 패턴을 이온주입 마스크로 사용하여 엔형 불순물을 이온주입하는 단계 포토 레지스터 패턴을 제거한 후에 산화막 상에 질화막을 덮고 그 위에 액티브 영역을 한정하기 위한 제2포토 레지스터 패턴을 형성하고 이 패턴을 식각 마스크로 사용하여 질화막을 선택적으로 식각하는 단계 제2포토 레지스터 패턴을 제거한 후에 기판을 열처리하여 필드산화막을 형성함과 동시에 주입된 엔형 불순물을 활성화시켜서 엔형 웰영역을 형성하는 단계 및 남겨진 질화막을 완전히 제거한 다음에 셀영역 및 주변영역의 피형 웰을 형성하기 위한 제3포토 레지스터 패턴을 형성하고 이 패턴을 이온주입 마스크로 사용하여 피형 불순물을 이온주입하고 주입된 불순물을 활성화시키는 단계를 구비하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a memory device, and more particularly, to a method of forming a semiconductor well in a semiconductor memory device having a cell region and a peripheral region, after forming an oxide film on a semiconductor substrate. Forming a photoresist pattern and ion implanting N-type impurities using the formed first photoresist pattern as an ion implantation mask After removing the photoresist pattern, a second photoresist for covering the nitride film on the oxide film and defining an active region thereon Forming a pattern and selectively etching the nitride film using the pattern as an etch mask. After removing the second photoresist pattern, the substrate is heat-treated to form a field oxide film, and the implanted Y-type impurities are activated to form an N-type well region. Steps and complete removal of the remaining nitride film And forming a third photoresist pattern for forming the wells of the cell region and the peripheral region at the negative side, using the pattern as an ion implantation mask to ion implant the implanted impurities and to activate the implanted impurities. do.

따라서, 본 발명에서는 피형 기판에 트리플 웰 형성을 간략화 할 수 있다.Therefore, in the present invention, triple well formation can be simplified in the substrate.

Description

반도체 메모리 장치의 제조방법Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제9도는 본 발명에 의한 반도체 메모리 장치의 제조방법을 나타낸 공정순서도.9 is a process flowchart showing a method of manufacturing a semiconductor memory device according to the present invention.

Claims (2)

셀영역과 주변영역을 가지는 반도체 메모리 장치의 제조방법에 있어서, 피형 반도체 기판 상에 산화막을 형성한 후에 셀영역과 주변영역의 엔형 웰 형성을 위한 포토 레지스터 패턴을 형성하고 형성된 제1포토 레지스터 패턴을 이온주입 마스크로 사용하여 엔형 불순물을 이온주입하는 단계 상기 포토 레지스터 패턴을 제거한 후에 산화막 상에 질화막을 덮고 그위에 액티브 영역을 한정하기 위한 제2포토 레지스터 패턴을 형성하고 이 패턴을 식각 마스크로 사용하여 질화막을 선택적으로 식각하는 단계 상기 제2포토 레지스터 패턴을 제거한 후에 기판을 열처리하여 필드산화막을 형성함과 동시에 주입된 엔형 불순물을 활성화시켜서 엔형 웰영역을 형성하는 단계 및 상기 남겨진 질화막을 완전히 제거한 다음에 셀영역 및 주변영역의 피형 웰을 형성하기 위한 제3포토레지스터 패턴을 형성하고 이패턴을 이온주입 마스크로 사용하여 피형 불순물을 이온주입하고 주입된 불순물을 활성화시키는 단계를 구비하는 것을 특징으로 하는 반도체 메모리 장치의 제조방법.A method of manufacturing a semiconductor memory device having a cell region and a peripheral region, wherein after forming an oxide film on a semiconductor substrate, a photoresist pattern for forming an N-type well of the cell region and the peripheral region is formed, and the first photoresist pattern is formed. Ion implantation of Y-type impurities using an ion implantation mask After removing the photoresist pattern, a second photoresist pattern is formed on the oxide film to cover the nitride film and define an active region thereon, and the pattern is used as an etching mask. Selectively etching the nitride film, after removing the second photoresist pattern, heat treating the substrate to form a field oxide film, activating the implanted N-type impurities to form an N-type well region, and completely removing the remaining nitride film. Formed wells in the cell region and the surrounding region The method of manufacturing a semiconductor memory device comprising the steps of forming a third photoresist pattern, and implanting impurity pihyeong using this pattern as a mask, ion implantation and activate the implanted impurities group. 제1항에 있어서, 상기 방법은 제3포토 레지스터 패턴을 사용하여 피형 웰 이온주입후에는 필드이온주입을 수행하는 것을 특징으로 하는 반도체 메모리 장치의 제조방법.The method of claim 1, wherein the method performs field ion implantation after implantation of a well type ion using a third photoresist pattern. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065898A 1995-12-29 1995-12-29 Manufacturing Method of Semiconductor Memory Device KR970054108A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065898A KR970054108A (en) 1995-12-29 1995-12-29 Manufacturing Method of Semiconductor Memory Device

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KR1019950065898A KR970054108A (en) 1995-12-29 1995-12-29 Manufacturing Method of Semiconductor Memory Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465606B1 (en) * 1998-06-30 2005-04-06 주식회사 하이닉스반도체 Triple well manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465606B1 (en) * 1998-06-30 2005-04-06 주식회사 하이닉스반도체 Triple well manufacturing method of semiconductor device

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