KR960002747A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR960002747A
KR960002747A KR1019940014875A KR19940014875A KR960002747A KR 960002747 A KR960002747 A KR 960002747A KR 1019940014875 A KR1019940014875 A KR 1019940014875A KR 19940014875 A KR19940014875 A KR 19940014875A KR 960002747 A KR960002747 A KR 960002747A
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KR
South Korea
Prior art keywords
oxide film
film
oxide
implanted
nitride film
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Application number
KR1019940014875A
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Korean (ko)
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KR0131717B1 (en
Inventor
김승준
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940014875A priority Critical patent/KR0131717B1/en
Publication of KR960002747A publication Critical patent/KR960002747A/en
Application granted granted Critical
Publication of KR0131717B1 publication Critical patent/KR0131717B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자의 소자분리방법에 관한 것으로, 특히, 트랜치 스페이서(Trench spacer)를 이용하여 트랜치 스패이서가 형성된 부분에서는 고 농도의 이온 주입이 되지 않아 필드 산화막이 성장하지 않고, 이소 스패이서가 넓은 비 활성 영역에서는 즉, 고 농도의 이온 주입이 된 비 활성 영역에서는 필드 산화막이 급격하게 성장하므로 필드 산화막으로서의 역할을 하게 되고, 이로써 활성영역과 비활성영역의 접합부 부근에서는 트랜치 스패이서의 형성으로 고 이온 주입이 되지 않게함으로써 비 활성영역의 일정부분, 즉 접합부 부근에는 고 농도의 이온주입을 차단하여 접합 파괴전압을 증가 시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device. In particular, in a portion where a trench spacer is formed using a trench spacer, ion implantation of a high concentration is not performed, so that a field oxide film does not grow and an iso spacer is formed. The field oxide film grows rapidly in a large inactive area, that is, in an inactive area to which high concentrations of ions are implanted, and thus acts as a field oxide film, thereby forming a trench spacer near the junction between the active area and the inactive area. By preventing the ion implantation, the junction breakdown voltage can be increased by blocking the high concentration of ion implantation in a portion of the inactive region, that is, the junction portion.

Description

반도체 소자의 소자 분리막 제조방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명의 반도체 소자의 소자 분리막 제조방법에 따른 제조 공정을 도시한 단면도.5 is a cross-sectional view showing a manufacturing process according to the device isolation film manufacturing method of a semiconductor device of the present invention.

Claims (4)

반도체 소자의 소자 분리막 제조방법에 있어서, 실리콘 기판 상부에 산화막 및 질화막을 차례로 증착하는 단계와, 상기 질화막 상부에 감광막을 증착한 후, 소자 분리용 마스크를 사용하여 상기 일정부분의 질화막과 산화막 그리고 기판을 일정두께까지 식각하여 트랜치를 형성하는 단계와, 상기 감광막을 제거한 다음, 전체 상부에 산화막을 증착하고 스페이서 식각을 한 후, 고농도의 이온 주입을 하는 단계와, 상기 고 농도의 이온이 주입된 기판을 산화시켜 필드 산화막을 형성하는 단계와, 다시, 기판 상부에 산화막을 증착하고 평탄화 식각을 하는 단계와, 상기 남아 있는 질화막과 그 하부의 산화막을 제거하는 단계로 구성되는 것을 특징으로 하는 반도체 소자의 소자 분리막 제거방법.In the method of manufacturing a device isolation film of a semiconductor device, the step of depositing an oxide film and a nitride film on the silicon substrate in turn, and after depositing a photosensitive film on the nitride film, using a mask for device isolation, the nitride film and the oxide film and the substrate of the predetermined portion Etching trenches to a predetermined thickness, removing the photoresist layer, depositing an oxide layer over the entire surface, etching the spacers, implanting a high concentration of ions, and implanting the high concentration ions into the substrate. Forming a field oxide film by oxidizing the oxide, depositing an oxide film on the substrate and performing planarization etching, and removing the remaining nitride film and the oxide film under the oxide film. Device Separator Removal Method. 제1항에 있어서 상기 이온 주입된 활성영역에서 필드 산화막 형성시 건식식각으로 이온 주입된 산화막 혹은 질화막을 제거하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제거방법.The method of claim 1, wherein the oxide or nitride film implanted by dry etching is removed when the field oxide film is formed in the ion implanted active region. 제1항에 있어서 상기 이온 주입된 활성영역에서 필드 산화막 형성시 습식식각으로 이온 주입된 산화막 혹은 질화막을 제거하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제거방법.The method of claim 1, wherein the oxide or nitride film implanted by wet etching is removed when the field oxide film is formed in the ion implanted active region. 제1항에 있어서 상기 이온 주입시 N 형 또는 P 형이온을 주입하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제거방법.The method of claim 1, wherein the N-type or P-type ion is implanted during the ion implantation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940014875A 1994-06-27 1994-06-27 Method for forming the elements isolation on the semiconductor device KR0131717B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940014875A KR0131717B1 (en) 1994-06-27 1994-06-27 Method for forming the elements isolation on the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940014875A KR0131717B1 (en) 1994-06-27 1994-06-27 Method for forming the elements isolation on the semiconductor device

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KR960002747A true KR960002747A (en) 1996-01-26
KR0131717B1 KR0131717B1 (en) 1998-04-14

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KR980006090A (en) * 1996-06-29 1998-03-30

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