KR970053843A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR970053843A
KR970053843A KR1019950065745A KR19950065745A KR970053843A KR 970053843 A KR970053843 A KR 970053843A KR 1019950065745 A KR1019950065745 A KR 1019950065745A KR 19950065745 A KR19950065745 A KR 19950065745A KR 970053843 A KR970053843 A KR 970053843A
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KR
South Korea
Prior art keywords
film
plate electrode
lower plate
semiconductor device
diffusion layer
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KR1019950065745A
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Korean (ko)
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KR0157119B1 (en
Inventor
김남주
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김광호
삼성전자 주식회사
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Priority to KR1019950065745A priority Critical patent/KR0157119B1/en
Publication of KR970053843A publication Critical patent/KR970053843A/en
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Publication of KR0157119B1 publication Critical patent/KR0157119B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

확산층 상에 커패시터의 하부 플레이트 전극이 형성된 반도체 장치에 관하여 개시한다. 본 발명은 반도체 기판에 하부 플레이트 전극, 유전체막 및 상부 플레이트 전극으로 구성된 커패시터를 갖는 반도체 장치에 있어서, 상기 하부 플레이트 전극은 상기 반도체 기판에 형성된 불순물 확산층 상에 형성되어 있는 것을 특징으로 하는 반도체 장치를 제공한다. 본 발명의 반도체 장치는 커패시터의 하부 플레이트 전극을 불순물이 도핑된 액티브 지역에 형성함으로써 플레이트 전극의 저항을 낮출 수 있어 커패시터의 AC특성을 향상시킬 수 있다.Disclosed is a semiconductor device in which a lower plate electrode of a capacitor is formed on a diffusion layer. A semiconductor device having a capacitor comprising a lower plate electrode, a dielectric film, and an upper plate electrode on a semiconductor substrate, wherein the lower plate electrode is formed on an impurity diffusion layer formed on the semiconductor substrate. to provide. The semiconductor device of the present invention can lower the resistance of the plate electrode by forming the lower plate electrode of the capacitor in an active region doped with impurities, thereby improving the AC characteristics of the capacitor.

Description

반도체장치 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 폴리실리콘 플레이트 커패시터를 도시한 평면도이다.2 is a plan view showing a polysilicon plate capacitor according to the present invention.

Claims (5)

반도체 기판에 하부 플레이트 전극, 유전체막 및 상부 플레이트 전극으로 구성된 커패시터를 갖는 반도체 장치에 있어서, 상기 하부 플레이트 전극은 상기 반도체 기판에 형성된 불순물 확산층 상에 형성되어 있는 것을 특징으로 하는 반도체 장치.A semiconductor device having a capacitor comprising a lower plate electrode, a dielectric film, and an upper plate electrode on a semiconductor substrate, wherein the lower plate electrode is formed on an impurity diffusion layer formed on the semiconductor substrate. 제1항에 있어서, 상기 하부 플레이트 전극은 불순물이 도핑된 폴리실리콘막으로 구성하는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein the lower plate electrode is made of a polysilicon film doped with impurities. 제1항에 있어서, 상기 유전체막은 산화막, 질화막 및 산화막의 복합막으로 구성하는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein said dielectric film is composed of a composite film of an oxide film, a nitride film and an oxide film. 반도체 기판 상에 패드 산화막을 형성하는 단계; 상기 패드 산화막 상에 제1포토레지스트 패턴을 형성하는 단계; 상기 제1포토레지스트 패턴을 이온주입마스크로 상기 반도체 기판의 전면에 이온주입을 실시하는 단계; 상기 제1포토레지스트 패턴을 제거하는 단계; 상기 패드 산화막 상에 질화막 패턴을 형성하는 단계; 상기 질화막 패턴이 형성된 기판을 산화시켜 필드산화막 및 제1확산층을 형성하는 단계; 상기 필드 산화막이 형성된 기판의 전면에 불순물이 도핑된 하부 플레이트용 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막을 열처리하여 상기 제1확산층 상에 제2확산층을 형성하는 단계; 상기 폴리실리콘막을 패터닝하여 상기 제2확산층 상에 하부 플레이트 전극을 형성하는 단계; 및 상기 하부 플레이트 전극 상에 유전체막 및 상부 플레이트 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.Forming a pad oxide film on the semiconductor substrate; Forming a first photoresist pattern on the pad oxide layer; Ion implanting the entire surface of the semiconductor substrate using the first photoresist pattern as an ion implantation mask; Removing the first photoresist pattern; Forming a nitride film pattern on the pad oxide film; Oxidizing the substrate on which the nitride film pattern is formed to form a field oxide film and a first diffusion layer; Forming a polysilicon film for a lower plate doped with impurities on an entire surface of the substrate on which the field oxide film is formed; Heat treating the polysilicon film to form a second diffusion layer on the first diffusion layer; Patterning the polysilicon film to form a lower plate electrode on the second diffusion layer; And forming a dielectric film and an upper plate electrode on the lower plate electrode. 제4항에 있어서, 상기 유전체막은 산화막, 질화막 및 산화막의 복합막으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein the dielectric film is formed of a composite film of an oxide film, a nitride film and an oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065745A 1995-12-29 1995-12-29 Semiconductor device and its manufacture KR0157119B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065745A KR0157119B1 (en) 1995-12-29 1995-12-29 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065745A KR0157119B1 (en) 1995-12-29 1995-12-29 Semiconductor device and its manufacture

Publications (2)

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KR970053843A true KR970053843A (en) 1997-07-31
KR0157119B1 KR0157119B1 (en) 1998-10-15

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Application Number Title Priority Date Filing Date
KR1019950065745A KR0157119B1 (en) 1995-12-29 1995-12-29 Semiconductor device and its manufacture

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100482240B1 (en) * 2001-10-30 2005-04-13 미쓰비시덴키 가부시키가이샤 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100482240B1 (en) * 2001-10-30 2005-04-13 미쓰비시덴키 가부시키가이샤 Semiconductor device

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KR0157119B1 (en) 1998-10-15

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