KR950021276A - Semiconductor MOSFET Manufacturing Method - Google Patents

Semiconductor MOSFET Manufacturing Method Download PDF

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Publication number
KR950021276A
KR950021276A KR1019930031879A KR930031879A KR950021276A KR 950021276 A KR950021276 A KR 950021276A KR 1019930031879 A KR1019930031879 A KR 1019930031879A KR 930031879 A KR930031879 A KR 930031879A KR 950021276 A KR950021276 A KR 950021276A
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KR
South Korea
Prior art keywords
film
oxide film
forming
field oxide
gate electrode
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Application number
KR1019930031879A
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Korean (ko)
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KR0170891B1 (en
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930031879A priority Critical patent/KR0170891B1/en
Priority to US08/365,293 priority patent/US5620911A/en
Priority to DE4447254A priority patent/DE4447254C2/en
Priority to JP7000039A priority patent/JP2624948B2/en
Publication of KR950021276A publication Critical patent/KR950021276A/en
Application granted granted Critical
Publication of KR0170891B1 publication Critical patent/KR0170891B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 모스펫 제조방법에 관한 것으로 소오스/드레인 전극의 상부에 실리사이드를 형성하여 금속배선과 접속되게 하므로써 스파이킹 현상을 방지하며 필드 산화막 상부에도 연장되어 존재하게 하여 소오스/드레인 전극과 금속배선과의 접속여유도를 증가시키며 가상의 필드 산화막을 이용하여 실리콘 기판과 게이트 전극의 단차를 감소시키는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor MOSFET, by forming a silicide on the top of the source / drain electrode to be connected to the metal wiring to prevent spikes and to extend to the top of the field oxide film and to exist in the source / drain electrode and the metal wiring The present invention relates to a method for increasing the connection margin of and reducing the step difference between the silicon substrate and the gate electrode using a virtual field oxide film.

Description

반도체 모스펫(MOSFET)제조방법Semiconductor MOSFET Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명의 공정방법에 의해 제조한 모스펫의 단면도이다.2A to 2E are cross-sectional views of the MOSFET produced by the process method of the present invention.

제3도는 본 발명의 다른 실시예를 도시한 단면도이다.3 is a cross-sectional view showing another embodiment of the present invention.

Claims (2)

반도체 모스펫 제조방법에 있어서 실리콘 기판에 P-웰을 형성하고 산화막과 질화막을 적층한 다음 사진식각방법으로 활성영역의 실리콘 기판 상부에만 산화막과 질화막을 남도록 하는 동시에 활성영역중 게이트 전극이 형성될 부분은 노출되도록 하고 전체적으로 P+형 불순물을 주입하여 채널 스토퍼 영역을 형성하는 공정과, 비활성영역에 필드산화막을 활성영역에 가상의 필드산화막을 동시에 형성하고 질화막과 산화막을 제거한 후 필드산화막과 가상 필드산화막 상부에 감광막 패턴을 형성하여 N+이온주입영역을 실시하는 공정과 감광막 패턴을 제거하고 그 상부에 전체적으로 제2폴리실리콘을 적층하고 가상 필드산화막 부분을 제외한 나머지 부분에 감광막 패턴을 형성한 다음 폴리실리콘막과 가상 필드산화막을 제거하여 트렌치를 형성하는 공정과, 감광막 패턴을 제거한 후 트렌체 내부에 공지의 기술로 게이트 전극을 형성하고 N-이온주입영역을 형성하는 공정과, 게이트전극 측벽에 스페이서를 형성하고 전이금속막을 선택증착하여 열처리하여 폴리실리콘막 상부와 게이트 전극 상부에만 실리사이드를 형성하고 층간절연막을 적층한 후 콘택홀과 금속배선을 형성하여 금속배선과 실리사이드가 접속되어 소오스/드레인 전극의 스파이킹을 방지하는 것을 특징으로 하는 반도체 모스펫 제조방법.In the method of manufacturing a semiconductor MOSFET, a P-well is formed on a silicon substrate, an oxide film and a nitride film are laminated, and a portion of the active area where the gate electrode is formed while leaving the oxide film and the nitride film only on the silicon substrate in the active region. Forming a channel stopper region by exposing and injecting P + type impurities as a whole, and simultaneously forming a field oxide film in an inactive region, a virtual field oxide film in an active region, removing a nitride film and an oxide film, and then removing the top of the field oxide film and the virtual field oxide film. Forming a photoresist pattern on the photoresist layer to remove N + ion implantation region, removing the photoresist pattern, and laminating the second polysilicon on top of it, forming a photoresist pattern on the remaining portions except the virtual field oxide layer, and then polysilicon film. To form trenches by removing the A process of forming a gate electrode and a N - ion implantation region in a trench by removing the photoresist pattern, and then forming a spacer on the sidewall of the gate electrode and heat-processing by selectively depositing a transition metal film. Method of manufacturing a semiconductor MOSFET, characterized in that the silicide is formed only on the top of the film and the top of the gate electrode, and the interlayer insulating film is laminated, and then the contact hole and the metal wiring are formed so that the metal wiring and the silicide are connected to prevent spikes of the source / drain electrodes. . 제1항에 있어서, 산화막과 질화막 사이에 패드용으로 불순물이 도핑되지 않은 폴리실리콘막을 적층하는 것을 특징으로 하는 반도체 모스펫 제조방법.A method according to claim 1, wherein a polysilicon film which is not doped with impurities for a pad is laminated between the oxide film and the nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930031879A 1993-12-31 1993-12-31 Method of manufacturing semiconductor mosfet KR0170891B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019930031879A KR0170891B1 (en) 1993-12-31 1993-12-31 Method of manufacturing semiconductor mosfet
US08/365,293 US5620911A (en) 1993-12-31 1994-12-28 Method for fabricating a metal field effect transistor having a recessed gate
DE4447254A DE4447254C2 (en) 1993-12-31 1994-12-30 Method of manufacturing a metal oxide semiconductor field effect transistor
JP7000039A JP2624948B2 (en) 1993-12-31 1995-01-04 MOS-FET manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930031879A KR0170891B1 (en) 1993-12-31 1993-12-31 Method of manufacturing semiconductor mosfet

Publications (2)

Publication Number Publication Date
KR950021276A true KR950021276A (en) 1995-07-26
KR0170891B1 KR0170891B1 (en) 1999-03-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970060491A (en) * 1996-01-26 1997-08-12 김주용 Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970060491A (en) * 1996-01-26 1997-08-12 김주용 Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
KR0170891B1 (en) 1999-03-30

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