KR100187673B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100187673B1 KR100187673B1 KR1019950006094A KR19950006094A KR100187673B1 KR 100187673 B1 KR100187673 B1 KR 100187673B1 KR 1019950006094 A KR1019950006094 A KR 1019950006094A KR 19950006094 A KR19950006094 A KR 19950006094A KR 100187673 B1 KR100187673 B1 KR 100187673B1
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- drain
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- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 230000008569 process Effects 0.000 claims description 39
- 238000005468 ion implantation Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 21
- 150000002500 ions Chemical class 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- -1 LDD ions Chemical class 0.000 claims 2
- 239000007943 implant Substances 0.000 claims 1
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000008570 general process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 비대칭 LDD 구조를 갖는 반도체 소자의 제조방법에 관하여 개시된다.The present invention relates to a method for manufacturing a semiconductor device having an asymmetric LDD structure.
본 발명은 드레인을 N-이온 영역 또는 N-/N+이온 영역으로 형성하여 N+이온영역으로 된 소오스에 대하여 비대칭 LDD 구조를 갖는 반도체 소자를 제조한다.The present invention is a drain N - to produce a semiconductor device having an LDD structure with respect to the asymmetric / N + to form the ion region in the N + source region ion-ion region or the N.
따라서, 본 발명은 반도체 소자에서 구동능력을 높이고, 핫 캐리어 효과를 감소시킬 수 있다.Therefore, the present invention can increase the driving capability in the semiconductor device and reduce the hot carrier effect.
Description
제1a내지 제c도는 본 발명의 제1실시예에 의한 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.1A to C are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
제1a내지 제c도는 본 발명의 제2실시예에 의한 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.1A to C are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 필드 산화막1: semiconductor substrate 2: field oxide film
3 : 게이트 산화막 4 : 게이트 전극3: gate oxide film 4: gate electrode
5 : 포토레지스트 패턴 6A 및 6B : 드레인 및 소오스5: photoresist pattern 6A and 6B: drain and source
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 비대칭(asymmetric) LDD(lightly doped drain) 구조를 갖는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an asymmetric lightly doped drain (LDD) structure.
일반적으로, NMOS 트랜지스터에서 기생 효과(parasitic effects)는 소오스(source)와 드레인(drain)쪽에서 크게 다르다. 소오스쪽의 기생 저항은 유효 게이트 전압(effective gate voltage)의 현저한 감소를 가져오나, 드레인쪽의 드레인 전류는 크게 영향을 받지 않는다. 이와같이 소오스와 드레인의 기생효과가 다름으로 인하여 고집적 반도체 소자에서 구동능력(drivability)이 저하되고, 핫 캐리어 효과(hot carrier effect)가 증대되는 문제가 있다.In general, parasitic effects in NMOS transistors differ greatly in terms of source and drain. The parasitic resistance on the source side results in a significant reduction in the effective gate voltage, but the drain current on the drain side is not significantly affected. As such, the parasitic effects of the source and the drain are different, so that the drivability is reduced and the hot carrier effect is increased in the highly integrated semiconductor device.
따라서, 본 발명은 반도체 소자에서 구동능력을 높이고, 핫 캐리어 효과를 감소시킬 수 있는 비대칭 LDD 구조를 갖는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having an asymmetric LDD structure capable of increasing driving capability and reducing hot carrier effects in a semiconductor device.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은 게이트 전극이 형성된 반도체 기판에 LDD 이온주입공정을 실시하는 단계와; N+소오스/드레인 불순물 주입 마스크를 사용한 리소그라피 공정으로 소오스가 형성될 영역이 개방되도록 포토레지스트 패턴을 형성한 후, N+소오스/드레인 이온주입공정을 실시하는 단계와; 상기 포토레지스트 패턴을 제거하고, 열처리공정을 실시하여 상기 반도체 기판내에 주입된 LDD 이온 및 N+소오스/드레인 불순물 이온을 확산시켜 N-이온 영역으로 된 드레인과 N+이온영역으로 된 소오스를 형성하는 단계로 이루어지는 것을 특징으로 한다.A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of performing an LDD ion implantation process on a semiconductor substrate on which a gate electrode is formed; Performing a N + source / drain ion implantation process by forming a photoresist pattern to open a region where a source is to be formed by a lithography process using an N + source / drain impurity implantation mask; Removing the photoresist pattern and performing a heat treatment process to diffuse LDD ions and N + source / drain impurity ions implanted into the semiconductor substrate to form a drain having an N − ion region and a source having an N + ion region ; It is characterized by consisting of steps.
이러한 목적을 달성하기 위한 본 발명의 다른 제조방법은 게이트 전극이 형성된 반도체 기판에 LDD 이온주입공정을 실시하는 단계와; N+소오스/드레인 불순물 주입 마스크를 사용한 리소그라피 공정으로 드레인이 형성될 영역이 소정부분 덮히도록 포토레지스트 패턴을 형성한 후, N+소오스/드레인 이온주입공정을 실시하는 단계와; 상기 포토레지스트 패턴을 제거하고, 열처리공정을 실시하여 상기 반도체 기판내에 주입된 LDD 이온 및 N+소오스/드레인 불순물 이온을 확산시켜 N-이온 영역과 N+이온 영역으로 된 드레인과 N+이온 영역으로 된 소오스를 형성하는 단계로 이루어지는 것을 특징으로 한다.Another manufacturing method of the present invention for achieving this object comprises the steps of performing an LDD ion implantation process on a semiconductor substrate on which a gate electrode is formed; Performing a N + source / drain ion implantation process by forming a photoresist pattern so as to cover a predetermined region of the drain region by a lithography process using an N + source / drain impurity implantation mask; The ion region and the N + of the ionic regions drain and the N + ions region by removing the photoresist pattern, and subjected to a heat treatment step the LDD ion and N + source / drain impurity ion implantation in the semiconductor substrate diffuse to N Characterized in that it comprises a step of forming a source.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a 내지 1c도는 본 발명의 제1실시예에 의한 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
제1a도는 필드 산화막(2)을 소자분리 마스크 공정에 의해 반도체기판(1)상에 형성한 다음, 게이트 산화막(3)과 게이트 전극(4)을 일반적인 공정으로 형성하고, 이후 LDD 이온주입공정을 실시하는 것이 도시된다.FIG. 1A shows that the field oxide film 2 is formed on the semiconductor substrate 1 by the device isolation mask process, the gate oxide film 3 and the gate electrode 4 are formed in a general process, and then the LDD ion implantation process is performed. The implementation is shown.
LDD 이온주입공정은 마스크 공정없이 P311.5E13의 도우즈(dose)로 60KeV의 에너지에 의해 반도체 기판(1)의 소오스/드레인이 형성될 영역에 주입한다.The LDD ion implantation process is implanted into a region where the source / drain of the semiconductor substrate 1 is to be formed by energy of 60 KeV with a dose of P 31 1.5E13 without a mask process.
제1b도는 N+소오스/드레인 불순물 주입 마스크를 사용한 리소그라피 공정으로 소오스가 형성될 영역이 개방도록 포토레지스트 패턴(5)을 형성한 후, N+소오스/드레인 이온주입공정을 실시하는 것이 도시된다.FIG. 1B shows a lithography process using an N + source / drain impurity implantation mask to form the photoresist pattern 5 so as to open a region where a source is to be formed, and then perform an N + source / drain ion implantation process.
N+소오스/드레인 이온주입공정은 As75를 6.0E15의 도우즈로 60KeV의 에너지에 의해 반도체 기판(1)의 소오스가 형성될 영역에 주입한다.In the N + source / drain ion implantation process, As 75 is injected into a region where the source of the semiconductor substrate 1 is to be formed by energy of 60 KeV with a dose of 6.0E15.
제1c도는 포토레지스트 패턴(5)을 제거하고, 열처리공정을 실시하여 상기 공정에서 주입된 LDD 이온 및 N+소오스/드레인 불순물 이온을 반도체 기판(1)내부로 확산시켜 N-이온 영역으로 된 드레인(6A)과 N+이온 영역으로 된 소오스(6B)를 형성한 것이 도시된다.FIG. 1C illustrates the removal of the photoresist pattern 5 and heat treatment to diffuse the LDD ions and N + source / drain impurity ions implanted in the process into the semiconductor substrate 1 to form an N − ion region. The formation of the source 6B of 6A and the N + ion region is shown.
제2a 내지 2c도는 본 발명의 제2실시예에 의한 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도이다.2A through 2C are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
제2a도는 필드 산화막(2)을 소자분리 마스크 공정에 의해 반도체기판(1)상에 형성한 다음, 게이트 산화막(3)과 게이트 전극(4)을 일반적인 공정으로 형성하고, 이후 LDD 이온주입공정을 실시하는 것이 도시된다.2A shows that the field oxide film 2 is formed on the semiconductor substrate 1 by a device isolation mask process, the gate oxide film 3 and the gate electrode 4 are formed in a general process, and then the LDD ion implantation process is performed. The implementation is shown.
LDD 이온주입공정은 마스크 공정없이 P31을 1.5E13의 도우즈(does)로 60KeV의 에너지의 의해 반드체 기판(1)의 소오스/드레인이 형성될 영역에 주입한다. 이때, 드레인이 형성될 영역쪽에 LDD 구조물 만들기 위하여 게이트 전극(4)쪽으로 5 내지 10°정도의 기울기로 사입사 하는 것이 바람직하다.In the LDD ion implantation process, P 31 is implanted into a region where the source / drain of the semiconductor substrate 1 is to be formed by 60KeV of energy with a dose of 1.5E13 without a mask process. In this case, in order to make the LDD structure on the region where the drain is to be formed, it is preferable to inject inclined at about 5 to 10 degrees toward the gate electrode 4.
제2b도는 N+소오스/드레인 불순물 주입 마스크를 사용한 리소그라피 공정으로 드레인이 형성될 영역이 게이트 전극(4)의 일측으로부터 0.1내지 0.3μm 정도가 덮히도록 포토레지스트 패턴(5)을 형성한 후, N+소오스/드레인 이온주입공정을 실시하는 것이 도시된다.FIG. 2B is a lithography process using an N + source / drain impurity implantation mask to form a photoresist pattern 5 such that a region where a drain is to be formed covers 0.1 to 0.3 μm from one side of the gate electrode 4, and then N + Carrying out a source / drain ion implantation process is shown.
N+소오스/드레인 이온주입공정은 As75를 6.0E15의 도우즈로 60KeV의 에너지에 의해 반도체 기판(1)의 소오스가 형성될 영역과 드레인이 형성될 영역의 노출된 부위에 주입한다.The N + source / drain ion implantation process injects As 75 into an exposed portion of the region where the source of the semiconductor substrate 1 is to be formed and the region where the drain is to be formed by a 60 KeV energy with a dose of 6.0E15.
제2c도는 포토레지스트 패턴(5)을 제거하고, 열처리공정을 실시하여 상기 공정에서 주입된 LDD 이온 및 N+소오스/드레인 불순물 이온을 반도체 기판(1)내부로 확산시켜 N-이온 영역과 N+이온 영역으로 된 드레인(6A)과 N+이온으로 된 소오스(6B)를 형성한 것이 도시된다.2C shows that the photoresist pattern 5 is removed and the heat treatment process is performed to diffuse the LDD ions and the N + source / drain impurity ions implanted in the process into the semiconductor substrate 1 to form the N − ion region and the N +. The formation of the drain 6A of the ion region and the source 6B of the N + ions is shown.
상술한 바와같이 본 발명은 드레인을 N-이온영역 또는 N-/N+이온 영역으로 형성하여 N+이온영역으로 된 소오스에 대하여 비대칭 LDD 구조를 갖도록 하므로써, 반도체 소자에서 구동능력을 높이고, 핫 캐리어 효과를 감소시킬 수 있다.The present invention provides a drain as described above, N - ion region or the N - / N + By forming the ion region so as to have an asymmetrical LDD structure with respect to the source of N + ions area, increase the driving capability in a semiconductor device, hot carriers The effect can be reduced.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006094A KR100187673B1 (en) | 1995-03-22 | 1995-03-22 | Method for fabricating semiconductor device |
| CN96105548A CN1073280C (en) | 1995-03-22 | 1996-03-22 | Method of making MOS transistor having LDD structure |
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| KR1019950006094A KR100187673B1 (en) | 1995-03-22 | 1995-03-22 | Method for fabricating semiconductor device |
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| KR960035914A KR960035914A (en) | 1996-10-28 |
| KR100187673B1 true KR100187673B1 (en) | 1999-06-01 |
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| CN101414554B (en) * | 2007-10-17 | 2010-04-14 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation method |
| CN101452853B (en) * | 2007-12-07 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor forming method |
| CN101621006B (en) * | 2008-07-03 | 2011-01-12 | 中芯国际集成电路制造(上海)有限公司 | Method for forming P-type light doping drain electrode region by pre-noncrystallization processing of germanium |
| CN101989551B (en) * | 2009-08-06 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming asymmetrical transistor |
| CN103247528B (en) * | 2012-02-03 | 2015-09-02 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of metal oxide semiconductor field effect tube |
| CN107134409B (en) * | 2016-02-26 | 2020-07-14 | 北大方正集团有限公司 | Transistor and ion implantation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5061975A (en) * | 1988-02-19 | 1991-10-29 | Mitsubishi Denki Kabushiki Kaisha | MOS type field effect transistor having LDD structure |
| JPH0320081A (en) * | 1989-06-16 | 1991-01-29 | Matsushita Electron Corp | Semiconductor integrated circuit |
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1995
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| CN1073280C (en) | 2001-10-17 |
| KR960035914A (en) | 1996-10-28 |
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