JPH0320081A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a current from concentrating in a contact window and from causing thermal breakdown by constituting a drain diffusion layer of a transistor whereto a high voltage is applied only by a diffusion layer of low concentration in LDD structure. CONSTITUTION:A device is composed of a P-type silicon substrate 1, a polysilicon gate electrode 2, a gate oxide film 3, an N-type diffusion layer 4 of low concentration, a sidewall 5, an N-type diffusion layer 6 of high concentration, a layer insulating film 7, a source electrode 8, and a drain electrode 9. A drain diffusion layer of a transistor where a voltage of at least source voltage is applied to a drain terminal is constituted only by the diffusion layer 4 of low concentration in LDD structure. Therefore, a series resistance is inserted between a contact window of a drain terminal and a channel; the parasitic series resistance prevents a current from concentrating to one contact window and operates to distribute the current to each contact window uniformly. Thereby, an integrated circuit can be protected against thermal breakdown.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a semiconductor MOS in which MOS transistors are integrated.
It concerns integrated circuits.

2. Description of the Related Art In recent years, MOS integrated circuits have come to be used in large quantities not only in large-scale information systems such as computers, but also in home appliances. The power supply voltage of these integrated circuits is generally the same as before.
sV has been followed, and as design rules have been reduced, drain breakdown voltage has been secured. In order to alleviate characteristic deterioration caused by hot carriers, the structure of MOS transistors has changed from a single drain structure to a double diffused drain structure. Furthermore, there has been a shift to a drain structure (hereinafter referred to as LDD structure) having a low concentration region.

Hereinafter, with reference to the drawings, the conventional LD as described above
A D-structure transistor will be explained.

FIG. 2 shows a structural sectional view of a conventional LDD structure transistor. In FIG. 2, 1 is a p-type silicon substrate on which a MOS integrated circuit is formed, 2 is a gate electrode made of polysilicon, 3 is a gate oxide film formed by thermally oxidizing the silicon substrate, and 41d is a polysilicon gate. This is a low concentration drain diffusion layer formed by ion implantation using electrode 2 as a mask. 6 is a side wall made of a silicon dioxide film formed in a self-aligned manner on the side wall of the polysilicon gate electrode Wi2; 6 is a high concentration drain diffusion layer formed in the form of side wall 5 or by subsequent ion implantation; 7 is a high concentration drain diffusion layer formed by ion implantation; Interlayer insulating films 8 and 9 are source and drain electrodes formed by opening holes in the interlayer insulating film and depositing aluminum thereon.

The drain breakdown voltage of the conventional LDD structure constructed as described above will be explained.

When the gate potential is lower than the gate threshold voltage, the drain breakdown voltage is determined by aparanche breakdown between the drain diffusion layer and the substrate in the peripheral area of the transistor, since the substrate concentration under the field oxide film is usually high. It is observed that when a drain current is flowing such that the gate potential is higher than the threshold voltage, the drain withstand voltage is lower than the above-mentioned 7-paranche breakdown voltage. This is considered to be due to the parasitic bibolar effect between the source (n type), substrate (p type), and drain (n type).

That is, electrons flowing through the channel are multiplied by apalanche due to the strong electric field near the drain, and the trapped holes flow into the substrate and become a substrate current. This substrate current raises the substrate potential directly under the channel and biases the base potential of the parasitic bipolar transistor positively. Therefore, like the collector breakdown voltage of a bipolar transistor when a collector current flows, the drain breakdown voltage of the MOS transistor in the operating state decreases as well as the breakdown voltage at cut-off.

It is recognized that as the gate length becomes shorter, the current amplification factor of the parasitic Paibov transistor increases and b1 decreases as the gate length becomes shorter.
In the channel M transistor, the drain breakdown voltage during operation is about 8V, compared to 13V when cut off.

Problems to be Solved by the Invention Dynamic Random Access Memory (hereinafter abbreviated as DRAM) is a typical MO8 semiconductor integrated circuit.
In order to write/read the power supply voltage as information in the memory cell, it is necessary to apply a high voltage higher than the I/I power supply voltage to the gate of the access transistor.This high voltage is applied to the Gutstrap circuit in the peripheral circuitry within the chip. It is generated using .

When the above-mentioned conventional LDD structure transistor is used as a transistor in which a high voltage boosted to a level higher than the power supply voltage is applied to the drain terminal, a voltage higher than the drain breakdown voltage is sometimes applied to the drain terminal, causing an excessive current to flow. This had the disadvantage of destroying the integrated circuit. As a result of physical analysis of the destroyed device, it was found that the diffusion layer of one of the multiple contact windows had been thermally destroyed. This is the shape of the window among multiple contact windows. It is thought that current was concentrated in the 91 contact windows due to differences in contact resistance, etc., leading to the breakdown.

SUMMARY OF THE INVENTION In view of the above drawbacks, the present invention provides a semiconductor integrated circuit that can avoid current concentration in one contact window, prevent device destruction, and dramatically improve reliability.

Means for Solving the Problems In order to solve the above-mentioned problems, the semiconductor integrated circuit of the present invention has a structure in which the drain diffusion layer of a transistor to which a high voltage is applied is changed from only a low concentration diffusion layer to a high concentration diffusion layer applied to an LDD structure. This is because it does not have a diffusion layer.

Function: With this configuration, a series resistance is inserted from the contact window of the drain terminal to the channel, and this parasitic series resistance prevents the current from concentrating on one contact window, and distributes the current evenly to each contact window. Vcf# to allocate
Therefore, the integrated circuit is protected from thermal damage.

EXAMPLE Hereinafter, one concrete example of the present invention will be described with reference to the drawings.

FIG. 1 shows a cross-sectional view of the structure of a transistor to which a high voltage is applied according to an embodiment of the present invention. In FIG. 1, 1 is a p-type silicon substrate, 2 is a polysilicon gate electrode with a gate length of 1 μm, 3 is a gate oxide film with a thickness of 200 μm, and 4 is an impurity concentration I formed by phosphorus ion implantation.
Low concentration n-type diffusion layer of about X 1 0"r', 6 is CVD
7 is an interlayer insulating film formed from a silicon dioxide film containing boron and phosphorous, 8 and e
are source and drain electrodes formed of aluminum after opening holes in the interlayer insulating film. 6 is formed by covering the drain region with photoresist and implanting arsenic ions into 10.
A high-concentration n-type diffusion layer having a solid material concentration of about 20α-3 is formed only on the source side. Note that the N-channel transistor in the circuit to which no high voltage is applied has a conventional LDD structure.

As described above, in this embodiment, in a CMOS integrated circuit, the parasitic resistance from the drain contact window to the channel can be increased by simply changing the mask for arsenic implantation without increasing the number of steps, and the thermal resistance caused by high voltage application can be increased. We were able to prevent the destruction.

In this embodiment, the aluminum electrode was brought into direct contact with the low concentration drain diffusion layer through the contact window, but this has the disadvantage of increasing contact resistance.

For this reason, it is possible to form a highly doped diffusion layer at the position of the contact window, or to form a highly doped diffusion layer directly under the contact window by introducing impurities after opening the contact window, without increasing the contact resistance. It is possible to achieve the intended purpose.

Effects of the Invention As described above, the present invention provides a drain diffusion layer of a MOS transistor to which a voltage higher than the power supply voltage is applied to the drain terminal, by making it only a low concentration diffusion layer in an LDD structure. It is possible to prevent current from concentrating on the contact window and causing thermal breakdown, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a structural cross-sectional view of an N-channel MOS transistor according to an embodiment of the present invention, and FIG. 2 is a conventional LDD structure N
FIG. 2 is a cross-sectional view of the structure of a channel MOS transistor. 1...p-type silicon substrate, 2...polysilicon gate electrode, 3...gate oxide film, 4
......Low concentration n-type diffusion layer, 6...Side wall, 6...High concentration n-type diffusion layer, 7...
...Interlayer insulating film, 8...Source electrode, 9...
...Drain electrode.

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising an N-channel MOS transistor to which a voltage higher than a power supply voltage is applied to a drain terminal, and a drain diffusion layer of the MOS transistor is formed of a low concentration n-type diffusion layer.