KR970052271A - Contact Forming Method of Semiconductor Device - Google Patents

Contact Forming Method of Semiconductor Device Download PDF

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Publication number
KR970052271A
KR970052271A KR1019950050949A KR19950050949A KR970052271A KR 970052271 A KR970052271 A KR 970052271A KR 1019950050949 A KR1019950050949 A KR 1019950050949A KR 19950050949 A KR19950050949 A KR 19950050949A KR 970052271 A KR970052271 A KR 970052271A
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KR
South Korea
Prior art keywords
oxide film
etching
contact
forming
semiconductor device
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KR1019950050949A
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Korean (ko)
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KR100204017B1 (en
Inventor
손기근
구영모
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김주용
현대전자산업 주식회사
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Priority to KR1019950050949A priority Critical patent/KR100204017B1/en
Publication of KR970052271A publication Critical patent/KR970052271A/en
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Publication of KR100204017B1 publication Critical patent/KR100204017B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체장치의 콘택형성방법에 관한 것으로, 기판 전면에 산화막을 형성하는 단계와, 상기 산화막을 선택적으로 식각하되, 일정두께만큼 식각하고 일정두께만큼은 남기는 단계, 상기 잔존하는 산화막 부위에만 선택적으로 실리콘을 이온주입하는 단계, 상기 주입된 실리콘 이온을 활성화시키는 단계, 및 상기 잔존하는 산화막을 식각하여 콘택을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 콘택 형성방법을 제공함으로써 콘택 형성시 문제가 되는 과도식각 및 식각부족 현상을 방지하여 기판 손상에 의해 발생되는 콘택 페일 및 접합파괴로 인한 누설전류에 기인하는 문제점들을 해결할 수 있도록 한다.The present invention relates to a method for forming a contact in a semiconductor device, comprising the steps of forming an oxide film on the entire surface of the substrate, selectively etching the oxide film, etching by a predetermined thickness and leaving a predetermined thickness, and selectively only remaining portions of the oxide film. Implanting silicon, activating the implanted silicon ions, and etching the remaining oxide film to form a contact, thereby providing a contact forming method of a semiconductor device. It prevents the problem of excessive etching and lack of etching to solve the problems caused by leakage current due to contact failure and junction breakage caused by substrate damage.

Description

반도체장치의 콘택 형성방법Contact Forming Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 반도체장치의 콘택 형성방법을 도시한 공정순서 단면도이다.2 is a cross sectional view of a process sequence showing a contact forming method of a semiconductor device according to the present invention.

Claims (8)

기판 전면에 산화막을 형성하는 단계와, 상기 산화막을 선택적으로 식각하되, 일정두께만큼 식각하고 일정두께 만큼은 남기는 단계, 상기 잔존하는 산화막 부위에만 선택적으로 실리콘을 이온주입하는 단계, 상기 주입된 실리콘 이온을 활성화시키는 단계, 및 상기 잔존하는 산화막을 식각하여 콘택을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 콘택 형성방법.Forming an oxide film on the entire surface of the substrate, selectively etching the oxide film, etching by a predetermined thickness and leaving a predetermined thickness, selectively implanting silicon into the remaining oxide region, and implanting the implanted silicon ions And activating the remaining oxide film to form a contact. 제1항에 있어서, 상기 산화막을 선택적으로 식각하는 단계에서 산화막 식각두께의 80-110%를 식각 목표로 설정하여 식각을 행하는 것을 특징으로 하는 반도체장치의 콘택 형성방법.2. The method of claim 1, wherein in the step of selectively etching the oxide film, etching is performed by setting 80-110% of the oxide film etching thickness as an etching target. 제1항에 있어서, 상기 잔존하는 산화막의 두께가 300-1000Å정도가 되도록 산화막의 식각을 행하는 것을 특징으로 하는 반도체장치의 콘택형성방법.The contact forming method of a semiconductor device according to claim 1, wherein the oxide film is etched so that the thickness of the remaining oxide film is about 300-1000 kPa. 제1항에 있어서, 상기 실리콘은 10-20KeV정도의 에너지에 의해 E15 이상의 이온량으로 주입하는 것을 특징으로 하는 반도체장치의 콘택형성방법.The contact forming method of a semiconductor device according to claim 1, wherein the silicon is implanted in an amount of ions equal to or greater than E15 by an energy of about 10-20 KeV. 제1항에 있어서, 상기 실리콘 이온이 주입되어 활성화된 상기 잔존산화막이 폴리실리콘과 유사한 성질을 갖게 되는 것을 특징으로 하는 반도체장치의 콘택 형성방법.The method of claim 1, wherein the remaining oxide film activated by implanting the silicon ions has properties similar to those of polysilicon. 제1항에 있어서, 상기 주입된 실리콘 이온의 활성화는 열처리공정에 의해 이루어지도록 하는 것을 특징으로 하는 반도체장치의 콘택 형성방법.The method of claim 1, wherein activation of the implanted silicon ions is performed by a heat treatment process. 제6항에 있어서, 상기 열처리공정은 600-800℃의 온도로 행하는 것을 특징으로 하는 반도체장치의 콘택 형성방법.The method of forming a contact of a semiconductor device according to claim 6, wherein said heat treatment step is performed at a temperature of 600-800 캜. 반도체기판 전면에 산화막을 형성하는 단계와, 상기 산화막상에 소정의 감광막패턴을 형성하는 단계, 상기 감광막패턴을 마스크로 하여 상기 산화막을 1차 식각하여 일정두께만큼 제거하고, 일정두께만큼은 남기는 단계, 상기 잔존하는 산화막에 실리콘을 이온주입하는 단계, 상기 주입된 실리콘 이온을 활성화시키는 단계, 상기 감광막패턴을 마스크로 이용하여 상기 잔존하는 산화막을 2차식각에 의해 완전히 제거하여 콘택을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체장치의 콘택 형성방법.Forming an oxide film on the entire surface of the semiconductor substrate, forming a predetermined photoresist pattern on the oxide film, first etching the oxide film using the photoresist pattern as a mask, removing the oxide film by a predetermined thickness, and leaving a predetermined thickness; Implanting silicon into the remaining oxide film, activating the implanted silicon ions, and forming a contact by completely removing the remaining oxide film by secondary etching using the photosensitive film pattern as a mask. A contact forming method of a semiconductor device, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050949A 1995-12-16 1995-12-16 Method for forming a contact of a semiconductor device KR100204017B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950050949A KR100204017B1 (en) 1995-12-16 1995-12-16 Method for forming a contact of a semiconductor device

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KR970052271A true KR970052271A (en) 1997-07-29
KR100204017B1 KR100204017B1 (en) 1999-06-15

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KR100685889B1 (en) 2005-12-29 2007-02-26 동부일렉트로닉스 주식회사 Method for manufacturing a cmos image sensor

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