KR940001025Y1 - Structure of n-well bicmos - Google Patents

Structure of n-well bicmos Download PDF

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Publication number
KR940001025Y1
KR940001025Y1 KR2019890012334U KR890012334U KR940001025Y1 KR 940001025 Y1 KR940001025 Y1 KR 940001025Y1 KR 2019890012334 U KR2019890012334 U KR 2019890012334U KR 890012334 U KR890012334 U KR 890012334U KR 940001025 Y1 KR940001025 Y1 KR 940001025Y1
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KR
South Korea
Prior art keywords
well
bicmos
layer
resistance
type substrate
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KR2019890012334U
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Korean (ko)
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KR910004999U (en
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박허선
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금성일렉트론 주식회사
문정환
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Priority to KR2019890012334U priority Critical patent/KR940001025Y1/en
Publication of KR910004999U publication Critical patent/KR910004999U/en
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Publication of KR940001025Y1 publication Critical patent/KR940001025Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

N-웰 BICMOS 구조N-well BICMOS structure

제1도는 본고안의 BICMOS 구조도.1 is a BICMOS structure diagram of the present article.

제2도는 종래의 BICMOS 구조도.2 is a conventional BICMOS structure diagram.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : P형 기판 2 : N-웰1: P-type substrate 2: N-well

3 : N+매몰층3: N + buried layer

본 고안은 N-웰 BICMOS 구조에 관한 것으로 BICMOS 제조 공정시 필요한 에피층 성정 공정 없이도 바이폴라 소자의 콜렉터 저항을 감소시킬 수 있도록 한 것이다.The present invention relates to an N-well BICMOS structure to reduce the collector resistance of a bipolar device without the epilayer deposition process required for the BICMOS fabrication process.

일반적으로 BICMOS 제조공정시 P형기판에 N+매몰층 공정과 에피층을 성장시켜 바이폴라와 CMOS 소자를 제조하였는데 제2도와 같은 종래의 N-웰 BICMOS 공정에서는 N+매몰층 공정후 에피층 공정이 생략되는 장점이 있지만 바이폴라 소자의 콜렉터 저항이 증가하는 단점이 있었다.In general, bipolar and CMOS devices are manufactured by growing an N + buried layer process and an epi layer on a P-type substrate during a BICMOS manufacturing process. In the conventional N-well BICMOS process as shown in FIG. 2, an epi layer process after an N + buried layer process is performed. Although there is an advantage omitted, the collector resistance of the bipolar device is increased.

본 고안은 이와같은 종래의 단점을 감안하여 안출한 것으로 에피층을 성장시키지 않고서도 콜렉터 저항을 감소시킬 수 있는 BICMOS 구조를 제공코저 한것인바, 이를 첨부된 도면 제1도에 의하여 더욱 상세히 설명하면 다음과 같다.The present invention has been made in view of the above-mentioned drawbacks, and provides a BICMOS structure that can reduce the collector resistance without growing the epi layer, which will be described in more detail with reference to FIG. As follows.

본 고안은 P형기판(1)에 BICMOS를 형성한 것에 있어서, P형 기판(1)에 N-웰(2)을 형성시킨후 고에너지 이온 주입시 이 N-웰(2)내부에 N+매몰층(3)을 주입시켜서 구성된 것이다.In the present invention, the BICMOS is formed on the P-type substrate 1, and the N-well 2 is formed on the P-type substrate 1, and then N + inside the N-well 2 during high energy ion implantation. It is comprised by injecting the investment layer 3.

이와같이 구성되는 본 고안은 N-웰(2)의 면적이 콜렉터 저항으로 사용되었기 때문에 저항 및 커패시터가 상당히 커져 회로 구성시 콜렉터의 저항으로 인하여 속도가 저하되었으나 N+매몰층(3)이 N-웰(2)내부에 수평으로 형성되어 있어 에피층의 형성 없이도 바이폴라 소자의 콜렉터 저항을 감소시킬 수 있으며, 기존의 BICMOS N-웰만 사용할 경우에 부수적으로 생기는 레치 업(Latch-up)현상을 N+매몰층(3)에 의하여 방지할 수 있는 효과가 있다.Thus configured present design is used because the resistance in the collector area of the N- well (2) resistance and capacitor, but is significantly increased speed is reduced due to the resistance of the collector when the circuit configuration N + buried layer 3 is N- well is (2) It is horizontally formed inside, so that the collector resistance of the bipolar device can be reduced without forming an epitaxial layer, and N + investment is caused by the latch-up phenomenon that occurs when only the existing BICMOS N-well is used. There is an effect that can be prevented by the layer (3).

Claims (1)

BICMOS 구조에 있어서, P형기판(1)에 N-웰(2)을 형성시킨 후 고에너지 이온 주입시 이 N-웰(2)내부에 N+매몰층(3)을 주입시켜서 구성됨을 특징으로 하는 N-웰 BICMOS 구조.In the BICMOS structure, the N-well 2 is formed on the P-type substrate 1, and the N + buried layer 3 is injected into the N-well 2 during high energy ion implantation. N-well BICMOS structure.
KR2019890012334U 1989-08-23 1989-08-23 Structure of n-well bicmos KR940001025Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019890012334U KR940001025Y1 (en) 1989-08-23 1989-08-23 Structure of n-well bicmos

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019890012334U KR940001025Y1 (en) 1989-08-23 1989-08-23 Structure of n-well bicmos

Publications (2)

Publication Number Publication Date
KR910004999U KR910004999U (en) 1991-03-20
KR940001025Y1 true KR940001025Y1 (en) 1994-02-25

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KR2019890012334U KR940001025Y1 (en) 1989-08-23 1989-08-23 Structure of n-well bicmos

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KR910004999U (en) 1991-03-20

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