JPS54154282A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54154282A
JPS54154282A JP6291178A JP6291178A JPS54154282A JP S54154282 A JPS54154282 A JP S54154282A JP 6291178 A JP6291178 A JP 6291178A JP 6291178 A JP6291178 A JP 6291178A JP S54154282 A JPS54154282 A JP S54154282A
Authority
JP
Japan
Prior art keywords
layer
type
groove
buried
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6291178A
Other languages
Japanese (ja)
Inventor
Akihiko Furukawa
Minoru Taguchi
Hajime Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6291178A priority Critical patent/JPS54154282A/en
Publication of JPS54154282A publication Critical patent/JPS54154282A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE: To secure formation of the even layer in a short time by forming the high- density impurity layer of the same conducting type as the semiconductor layer along the V-groove provided to the semiconductor layer.
CONSTITUTION: The n+-buried layer 12 and n-epitaxial layer 13 are laminated on n-type Si substrate 11, and V-groove 14 is cut reaching the buried layer. Then n+-region 15 reaching the buried layer along groove 14 is formed into layer 13 by the ion injection method, and thus layer 15 can be formed with the even high density and in a short time over the entire region. Then p+-layer 16, p-layer 17 and n- layer 18 are formed within n-type island 13a, and the window is drilled to SiO2 19 with Al electrodes 15a∼18a attached. In such constitution, the inverter of I2L uses p-layer 17 and n-type island 13a which are common to the base and the collector of the injector as the base and emitter each and n-layer 18 as the collector. Thus, the satisfactory block effect is shown since n+-layer 15 features the even high density, enhancing amplification factor β by 10∼15% up.
COPYRIGHT: (C)1979,JPO&Japio
JP6291178A 1978-05-26 1978-05-26 Semiconductor device Pending JPS54154282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6291178A JPS54154282A (en) 1978-05-26 1978-05-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6291178A JPS54154282A (en) 1978-05-26 1978-05-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54154282A true JPS54154282A (en) 1979-12-05

Family

ID=13213903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6291178A Pending JPS54154282A (en) 1978-05-26 1978-05-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54154282A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910572A (en) * 1985-07-19 1990-03-20 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910572A (en) * 1985-07-19 1990-03-20 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of fabricating the same

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