KR930014891A - How to arrange indirect layers - Google Patents

How to arrange indirect layers Download PDF

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Publication number
KR930014891A
KR930014891A KR1019910023299A KR910023299A KR930014891A KR 930014891 A KR930014891 A KR 930014891A KR 1019910023299 A KR1019910023299 A KR 1019910023299A KR 910023299 A KR910023299 A KR 910023299A KR 930014891 A KR930014891 A KR 930014891A
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KR
South Korea
Prior art keywords
layer
alignment pattern
alignment
layers
aligned
Prior art date
Application number
KR1019910023299A
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Korean (ko)
Other versions
KR950000107B1 (en
Inventor
박대영
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910023299A priority Critical patent/KR950000107B1/en
Publication of KR930014891A publication Critical patent/KR930014891A/en
Application granted granted Critical
Publication of KR950000107B1 publication Critical patent/KR950000107B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

본 발명은 반도체기판의 기본층위에 여러층을 간접적으로 정렬할 때 정렬정도를 향상시키는 방법에 관한 것으로, 제1층 위에 제2층을 정렬할 때, 제2층의 제2정렬용 패턴(5)을 제1층의 제1정렬용 패턴(4) 위에 형성시키고, 제1정렬용 패턴(4)과 제2정렬용 패턴(5)으로부터 정렬용 신호 S를 얻어서 S의 처음 피크 P3와 최종피크 P6를 기준으로 하여 P3와 P6의 중앙에 제3층을 정렬시키는 방법이다.The present invention relates to a method for improving the degree of alignment when indirectly aligning a plurality of layers on the base layer of the semiconductor substrate, when the second layer is aligned on the first layer, the second alignment pattern (5) ) Is formed on the first alignment pattern 4 of the first layer, and an alignment signal S is obtained from the first alignment pattern 4 and the second alignment pattern 5 to obtain the first peak P3 and the final peak of S. The third layer is aligned with the center of P3 and P6 based on P6.

Description

간접층 정렬방법How to arrange indirect layers

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 간접층 정렬방법을 성명하기 위한 도면2 is a diagram for clarifying the indirect layer alignment method of the present invention.

Claims (1)

반도체 기판상에 간접층을 정렬하는 방법에 있어서, 기본층의 제1정렬용 패턴 중앙에 제2층을 정렬하면서 제1정렬용 패턴위에 제2정렬용 패턴을 형성하고, 제1정렬용 패턴과 제2정렬용 패턴의 합성인 합성정렬용 패턴의 중앙에 제3층을 정렬하는 것이 특징인 간접층 정렬방법.A method of aligning an indirect layer on a semiconductor substrate, comprising: forming a second alignment pattern on the first alignment pattern while aligning the second layer in the center of the first alignment pattern of the base layer; An indirect layer alignment method, characterized in that the third layer is aligned in the center of the synthesis alignment pattern, which is a synthesis of the second alignment pattern. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910023299A 1991-12-18 1991-12-18 Method of indirect layer alignment KR950000107B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910023299A KR950000107B1 (en) 1991-12-18 1991-12-18 Method of indirect layer alignment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910023299A KR950000107B1 (en) 1991-12-18 1991-12-18 Method of indirect layer alignment

Publications (2)

Publication Number Publication Date
KR930014891A true KR930014891A (en) 1993-07-23
KR950000107B1 KR950000107B1 (en) 1995-01-09

Family

ID=19325071

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910023299A KR950000107B1 (en) 1991-12-18 1991-12-18 Method of indirect layer alignment

Country Status (1)

Country Link
KR (1) KR950000107B1 (en)

Also Published As

Publication number Publication date
KR950000107B1 (en) 1995-01-09

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