KR930014817A - Overetching Method of Semiconductor Substrate - Google Patents

Overetching Method of Semiconductor Substrate Download PDF

Info

Publication number
KR930014817A
KR930014817A KR1019910022143A KR910022143A KR930014817A KR 930014817 A KR930014817 A KR 930014817A KR 1019910022143 A KR1019910022143 A KR 1019910022143A KR 910022143 A KR910022143 A KR 910022143A KR 930014817 A KR930014817 A KR 930014817A
Authority
KR
South Korea
Prior art keywords
semiconductor substrate
overetching
overetch
wafer
overetching method
Prior art date
Application number
KR1019910022143A
Other languages
Korean (ko)
Other versions
KR940007065B1 (en
Inventor
박태훈
김영관
고용선
안성규
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910022143A priority Critical patent/KR940007065B1/en
Publication of KR930014817A publication Critical patent/KR930014817A/en
Application granted granted Critical
Publication of KR940007065B1 publication Critical patent/KR940007065B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

건식식각에 의한 트랜체 구조 형성시 발생되는 내부의 손상 및 오염물질을 HNO3+HF+H2O2+H2O 시스팀을 이용한 과식각 방법으로 제거할 수 있다.Internal damage and contaminants generated during the formation of the trench structure by dry etching can be removed by the over-etching method using the HNO 3 + HF + H 2 O 2 + H 2 O system.

Description

반도체 기판의 과식각 방법Overetching Method of Semiconductor Substrate

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

첨부된 도면은 본 발명의 과 식각 방법을 설며하기 위한 과식각 장치의 구성도.The accompanying drawings are schematic diagrams of an over-etching apparatus for explaining the over-etching method of the present invention.

Claims (3)

과식각을 이용하여 웨이퍼에 발생된 손상을 치유하거나 웨이퍼 표면의 세정을 수행하는 것을 특징으로 하는 반도체 기판의 과식각 방법.A method of overetching a semiconductor substrate, wherein the damage caused to the wafer is repaired or the surface of the wafer is cleaned by using the overetch. 제1항에 있어서 과식각 시스팀으로 HNO3+HF+H2O2+H2O 로 구성되는 그룹 중 적어도 하나 이상을 포함하는 것을 특징으로 하는 반도체 기판의 과식각 방법.The method of claim 1, wherein the over-etching system comprises at least one or more of the group consisting of HNO 3 + HF + H 2 O 2 + H 2 O. 제2항에 있어서 과식각 용액 내에 H2O2를 공급하여 실리콘의 식각률을 조절하는 것을 특징으로 하는 반도체 기판의 과식각 방법.The method of claim 2, wherein the etching rate of silicon is controlled by supplying H 2 O 2 in the overetch solution. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910022143A 1991-12-04 1991-12-04 Overetching method of semiconductor substrate KR940007065B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910022143A KR940007065B1 (en) 1991-12-04 1991-12-04 Overetching method of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910022143A KR940007065B1 (en) 1991-12-04 1991-12-04 Overetching method of semiconductor substrate

Publications (2)

Publication Number Publication Date
KR930014817A true KR930014817A (en) 1993-07-23
KR940007065B1 KR940007065B1 (en) 1994-08-04

Family

ID=19324145

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910022143A KR940007065B1 (en) 1991-12-04 1991-12-04 Overetching method of semiconductor substrate

Country Status (1)

Country Link
KR (1) KR940007065B1 (en)

Also Published As

Publication number Publication date
KR940007065B1 (en) 1994-08-04

Similar Documents

Publication Publication Date Title
JPS5434751A (en) Washing method for silicon wafer
TW374203B (en) A method for forming a fine contact hole in a semiconductor device
KR930014817A (en) Overetching Method of Semiconductor Substrate
JPS5591138A (en) Die forming of semiconductor device
KR960005940A (en) Device isolation oxide film formation method
KR940027074A (en) Contact Hole Formation Method of Semiconductor Device by Inclined Etching
KR950007006A (en) Well cleaning process method of semiconductor device
KR930020600A (en) Polymer removal method after etching polysilicon
KR940001269A (en) Metal wiring formation method of semiconductor device
KR960026122A (en) Polysilicon layer formation method of semiconductor device
KR970023813A (en) Semiconductor device manufacturing method
KR960001910A (en) Method of removing etch damage area of semiconductor device
KR960019501A (en) Polysilicon layer formation method of semiconductor device
KR920001619A (en) How to remove etch damage of oxide layer
KR980005550A (en) Method of forming a contact hole in a semiconductor device
JPS6415951A (en) Manufacture of semiconductor device
KR960015076A (en) Silicon wet etching method
KR960015767A (en) Deglazing Method Before Silicide Thin Film Deposition
KR960012345A (en) Silicon Wafer Cleaning Method
KR970051889A (en) Method for forming self-aligned mask of semiconductor device
KR930001335A (en) Polycrystalline Silicon Layer Etching Method of Semiconductor Device
KR940009758A (en) How to remove residue after dry oxide etching
JPS61239629A (en) Manufacture of semiconductor device
KR960019538A (en) Etching method of layer formed over thickness
KR960019654A (en) Field oxide film formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060728

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee