KR970051889A - Method for forming self-aligned mask of semiconductor device - Google Patents

Method for forming self-aligned mask of semiconductor device Download PDF

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Publication number
KR970051889A
KR970051889A KR1019950056937A KR19950056937A KR970051889A KR 970051889 A KR970051889 A KR 970051889A KR 1019950056937 A KR1019950056937 A KR 1019950056937A KR 19950056937 A KR19950056937 A KR 19950056937A KR 970051889 A KR970051889 A KR 970051889A
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KR
South Korea
Prior art keywords
silicon nitride
forming
silicon oxide
nitride film
etching
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Application number
KR1019950056937A
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Korean (ko)
Inventor
김상용
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950056937A priority Critical patent/KR970051889A/en
Publication of KR970051889A publication Critical patent/KR970051889A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 원은 반도체 소자의 자기 정렬 마스크 형성방법을 개시한다. 개시된 본 발명은 반도체 기판상에 실리콘 산화막과 제1실리콘 질화막을 순차적으로 형성하는 단계; 상기 질화막 상부에 마스크 패턴을 형성하고, 그의 형태로 실리콘 질화막을 식각하는 단계; 상기 식각이 이루어진 실리콘 질화막의 형태로 하부의 실리콘 산화막을 식각하는 단계; 상기 전체 구조 상부에 제2실리콘 질화막을 형성하는 단계; 상기 제2실리콘 질화막을 실리콘 산화막이 노출될 때까지 제거하는 단계; 및 상기 반도체 기판상에 존재하는 실리콘 산화막을 제거하는 단계를 포함한다.The present application discloses a method of forming a self-aligning mask of a semiconductor device. The present invention discloses the steps of sequentially forming a silicon oxide film and a first silicon nitride film on a semiconductor substrate; Forming a mask pattern on the nitride film and etching the silicon nitride film in a form thereof; Etching the lower silicon oxide film in the form of the silicon nitride film formed with the etching; Forming a second silicon nitride film over the entire structure; Removing the second silicon nitride layer until the silicon oxide layer is exposed; And removing the silicon oxide film present on the semiconductor substrate.

Description

반도체 소자의 자기 정렬 마스크 형성방법Method for forming self-aligned mask of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 (가) 내지 (바)는 본 발명에 따른 반도체 소자의 자기 정렬 마스크 형성방법을 설명하기 위한 공정도.1 (a) to (bar) are process drawings for explaining a method of forming a self-aligning mask of a semiconductor device according to the present invention.

Claims (4)

반도체 기판상에 실리콘 산화막과 제1실리콘 질화막을 순차적으로 형성하는 단계; 상기 제1실리콘 질화막 상부에 마스크 패턴을 형성하고, 그의 형태로 실리콘 질화막을 식각하는 단계; 상기 식각이 이루어진 제1실리콘 질화막의 형태로 하부의 실리콘 산화막을 식각하는 단계; 상기 전체 구조 상부에 제2실리콘 질화막을 형성하는 단계; 상기 제2실리콘 질화막을 실리콘 산화막이 노출될 때까지 제거하는 단계; 및 상기 반도체 기판상에 존재하는 실리콘 산화막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 자기 정렬 마스크 형성방법.Sequentially forming a silicon oxide film and a first silicon nitride film on the semiconductor substrate; Forming a mask pattern on the first silicon nitride layer and etching the silicon nitride layer in a form thereof; Etching the lower silicon oxide layer in the form of the first silicon nitride layer in which the etching is performed; Forming a second silicon nitride film over the entire structure; Removing the second silicon nitride layer until the silicon oxide layer is exposed; And removing the silicon oxide film present on the semiconductor substrate. 제1항에 있어서, 상기 제1실리콘 질화막은 CVD 방법에 의하여 식각되는 것을 특징으로 하는 반도체 소자의 자기 정렬 마스크 형성방법.The method of claim 1, wherein the first silicon nitride layer is etched by a CVD method. 제1항 또는 제2항에 있어서, 상기 제2실리콘 질화막은 FECVD 방법에 의하여 식각되는 것을 특징으로 하는 반도체 소자의 자기 정렬 마스크 형성방법.The method of claim 1 or 2, wherein the second silicon nitride film is etched by a FECVD method. 제1항에 있어서, 상기 제2실리콘 질화막을 실리콘 산화막이 노출될때 까지 제거하는 방법은 CMP 방법인 것을 특징으로 하는 반도체 소자의 자기 정렬 마스크 형성방법.The method of claim 1, wherein the method of removing the second silicon nitride film until the silicon oxide film is exposed is a CMP method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950056937A 1995-12-26 1995-12-26 Method for forming self-aligned mask of semiconductor device KR970051889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950056937A KR970051889A (en) 1995-12-26 1995-12-26 Method for forming self-aligned mask of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950056937A KR970051889A (en) 1995-12-26 1995-12-26 Method for forming self-aligned mask of semiconductor device

Publications (1)

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KR970051889A true KR970051889A (en) 1997-07-29

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KR1019950056937A KR970051889A (en) 1995-12-26 1995-12-26 Method for forming self-aligned mask of semiconductor device

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228628A (en) * 1985-04-02 1986-10-11 Nec Corp Method for inversion of pattern
JPS63257249A (en) * 1987-04-14 1988-10-25 Mitsubishi Electric Corp Manufacture of semiconductor device
US4968640A (en) * 1987-02-10 1990-11-06 Industrial Technology Research Institute Isolation structures for integrated circuits
JPH07321193A (en) * 1994-05-27 1995-12-08 Nippon Steel Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228628A (en) * 1985-04-02 1986-10-11 Nec Corp Method for inversion of pattern
US4968640A (en) * 1987-02-10 1990-11-06 Industrial Technology Research Institute Isolation structures for integrated circuits
JPS63257249A (en) * 1987-04-14 1988-10-25 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH07321193A (en) * 1994-05-27 1995-12-08 Nippon Steel Corp Manufacture of semiconductor device

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