KR960042979A - Fine pattern formation method - Google Patents

Fine pattern formation method Download PDF

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KR960042979A
KR960042979A KR1019950013692A KR19950013692A KR960042979A KR 960042979 A KR960042979 A KR 960042979A KR 1019950013692 A KR1019950013692 A KR 1019950013692A KR 19950013692 A KR19950013692 A KR 19950013692A KR 960042979 A KR960042979 A KR 960042979A
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South Korea
Prior art keywords
insulating layer
conductive layer
pattern
forming
film
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KR1019950013692A
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Korean (ko)
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KR0165399B1 (en
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박규찬
김일권
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Abstract

미세패턴의 형성방법에 관하여 개시한다. 본 발명은 반도체 기판 상에 패턴 형성을 위한 제1도전층을 형성하는 단계와, 상기 제1도전층 상에 제1절연층 패턴을 형성하는 단계와, 상기 제1절연층 패턴이 형성된 기판의 전면에 제2도전층을 형성하는 단계와, 상기 제2도전층 상에 제2절연층을 형성하여 상기 제1절연층 패턴 사이를 매립하는 단계와, 상기 제2절연층을 전면식각하여 상기 제1절연층 패턴 상에 형성된 제2도전층을 노출시키는 제2절연층 패턴을 형성하는 단계와 상기 제2절연층 패턴과 제1절연층 패턴을 마스크로 상기 제2도전층과 제1도전층을 연속적으로 식각하는 단계를 구비한다. 본 발명에 의하면 해상도 이하의 미세패턴 형성이 가능한 효과가 있다.A method of forming a fine pattern is disclosed. The present invention provides a method of forming a first conductive layer for forming a pattern on a semiconductor substrate, forming a first insulating layer pattern on the first conductive layer, and a front surface of the substrate on which the first insulating layer pattern is formed. Forming a second conductive layer on the second conductive layer; forming a second insulating layer on the second conductive layer to fill the gap between the first insulating layer patterns; and etching the second insulating layer on the entire surface of the first conductive layer. Forming a second insulating layer pattern exposing the second conductive layer formed on the insulating layer pattern, and continuously forming the second conductive layer and the first conductive layer using the second insulating layer pattern and the first insulating layer pattern as a mask; Etching is carried out. According to the present invention, it is possible to form a fine pattern with a resolution or less.

Description

미세패턴 형성방법Fine pattern formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1F도는 본 발명에 의한 미세패턴 형성방법의 일예를 나타낸 단면도들이다.1A to 1F are cross-sectional views showing an example of the method for forming a micropattern according to the present invention.

Claims (13)

반도체 기판 상에 패턴 형성을 위한 제1도전층을 형성하는 단계; 상기 제1도전층 상에 제1절연층 패턴을 형성하는 단계; 상기 제1절연층 패턴이 형성된 기판의 전면에 제2도전층을 형성하는 단계; 상기 제2도전층상에 제2절연층을 형성하여 상기 제1절연층 패턴 사이를 매립하는 단계; 상깅 제2절연층을 전면식각하여 상기 제1절연층 패턴 상에 형성된 제2도전층을 노출시키는 제2절연층 패턴을 형성하는 단계; 및 상기 제2절연층 패턴과 제1절연층 패턴을 마스크로 상기 제2도전층과 제1도전층을 연속적으로 식각하는 단계를 구비하는 것을 특징으로 하는 미세패턴 형성방법.Forming a first conductive layer for pattern formation on the semiconductor substrate; Forming a first insulating layer pattern on the first conductive layer; Forming a second conductive layer on an entire surface of the substrate on which the first insulating layer pattern is formed; Forming a second insulating layer on the second conductive layer to fill a gap between the first insulating layer patterns; Forming a second insulating layer pattern exposing the second insulating layer on the first insulating layer pattern to expose the second conductive layer formed on the first insulating layer pattern; And continuously etching the second conductive layer and the first conductive layer by using the second insulating layer pattern and the first insulating layer pattern as a mask. 제1항에 있어서, 상기 제1도전층 및 제2도전층은 동일한 식각 특성을 갖는 막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 1, wherein the first conductive layer and the second conductive layer are formed of a film having the same etching characteristics. 제2항에 있어서, 상기 제1도전층은 단결정 실리콘막, 다결정실리콘막 및 고융점 금속의 실리사이드막으로 선택된 일군에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 2, wherein the first conductive layer is formed of one selected from a group selected from a single crystal silicon film, a polycrystalline silicon film, and a silicide film of a high melting point metal. 제2항에 있어서, 상기 제2도전층은 다결정 실리콘막 또는 고융점 실리사이막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 2, wherein the second conductive layer is formed of a polycrystalline silicon film or a high melting point silicide film. 제1항에 있어서, 상기 제1절연층 패턴 및 제2절연층은 동일한식각 특성을 갖는 막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 1, wherein the first insulating layer pattern and the second insulating layer are formed of a film having the same etching characteristics. 제5항에 있어서, 상기 제1절연층 패턴 및 제2절연층은 실리콘 질화막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 5, wherein the first insulating layer pattern and the second insulating layer are formed of a silicon nitride film. 반도체 기판 상에 패턴 형성을 위한 제1도전층을 형성하는 단계; 상기 제1도전층 상에 제1절연층을 형성하는 단계; 상기 제1절연층 상에 제2절연층 패턴을 형성하는 단계; 상기 제2절연층 패턴이 형성된 기판의 전면에 제2도전층을 형성하는 단계; 상기 제2도전층 상에 제3절연층을 형성하여 상기 제2절연층 패턴 사이를 매립하는 단계; 상기 제3절연층을 전면식각하여 상기 제2절연층 패턴 상에 형성된 제2도전층을 노출시키는 제3절연층 패턴을 형성하는 단계; 및 상기 제2절연층 패턴과 제3절연층 패턴을 마스크로 상기 제2도전층, 제1절연층 및 제1도전층을 연속적으로 식각하는 단계를 구비하는 것을 특징으로 하는 미세패턴 형성방법.Forming a first conductive layer for pattern formation on the semiconductor substrate; Forming a first insulating layer on the first conductive layer; Forming a second insulating layer pattern on the first insulating layer; Forming a second conductive layer on an entire surface of the substrate on which the second insulating layer pattern is formed; Filling a gap between the second insulating layer patterns by forming a third insulating layer on the second conductive layer; Etching a third surface of the third insulating layer to form a third insulating layer pattern exposing a second conductive layer formed on the second insulating layer pattern; And sequentially etching the second conductive layer, the first insulating layer, and the first conductive layer by using the second insulating layer pattern and the third insulating layer pattern as a mask. 제7항에 있어서, 상기 제1도전층 및 제2도전층 동일한 식각특성을 갖는 막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 7, wherein the first conductive layer and the second conductive layer are formed of a film having the same etching characteristics. 제8항에 있어서, 상기 제1도전층은 단결정 실리콘, 다결정 실리콘 및 고융점 금속의 실리사이드막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 8, wherein the first conductive layer is formed of a silicide film of monocrystalline silicon, polycrystalline silicon, and high melting point metal. 제7항에 있어서, 상기 제2도전층은 다결정실리콘막 또는 고융점 실리사이드막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 7, wherein the second conductive layer is formed of a polysilicon film or a high melting silicide film. 제7항에 있어서, 상기 제2절연층 패턴 및 제3절연층 패턴은 동일한 식각 특성을 갖는 막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법The method of claim 7, wherein the second insulating layer pattern and the third insulating layer pattern are formed of a film having the same etching characteristics. 제11항에 있어서, 상기 제2절연층 패턴 및 제3절연층 패턴은 실리콘 질화막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 11, wherein the second insulating layer pattern and the third insulating layer pattern are formed of a silicon nitride film. 제7항에 있어서, 상기 제1절연층은 실리콘 산화막으로 형성하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 7, wherein the first insulating layer is formed of a silicon oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950013692A 1995-05-29 1995-05-29 Fine patterning method KR0165399B1 (en)

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KR100640640B1 (en) 2005-04-19 2006-10-31 삼성전자주식회사 Method of forming fine pattern of semiconductor device using fine pitch hardmask
US20080048340A1 (en) 2006-03-06 2008-02-28 Samsung Electronics Co., Ltd. Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same
KR100714305B1 (en) 2005-12-26 2007-05-02 삼성전자주식회사 Method of forming self aligned double pattern
US7998874B2 (en) 2006-03-06 2011-08-16 Samsung Electronics Co., Ltd. Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same
US7892982B2 (en) 2006-03-06 2011-02-22 Samsung Electronics Co., Ltd. Method for forming fine patterns of a semiconductor device using a double patterning process
KR100790998B1 (en) 2006-10-02 2008-01-03 삼성전자주식회사 Method of forming pad pattern using self-align double patterning method, and method of forming contact hole using self-align double patterning method
KR100843236B1 (en) 2007-02-06 2008-07-03 삼성전자주식회사 Method of forming fine patterns of semiconductor device using double patterning process
KR100817088B1 (en) 2007-02-16 2008-03-26 삼성전자주식회사 Method of forming fine damascene metal pattern for semiconductor device

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