KR970052574A

KR970052574A - Dummy gate formation method for planarization of semiconductor device

Info

Publication number: KR970052574A
Application number: KR1019950059342A
Authority: KR
Inventors: 김윤기
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-27
Filing date: 1995-12-27
Publication date: 1997-07-29

Abstract

본 발명은 더미 게이트용 폴리실리콘막의 두께차에 따라 POCl₃에 의한 게이트 산화막의 페일을 유도하여 메탈 콘택 및 메탈 라인없는 더미 게이트라인을 기판에 연결시켜 줄 수 있는 평탄화를 위한 더미 게이트형성하는 반도체장치의 평탄화용 더미 게이트형성방법에 관한 것이다.According to an embodiment of the present invention, a semiconductor device for forming a dummy gate for planarization that can connect a dummy gate line without a metal contact and a metal line to a substrate by inducing a failure of a gate oxide film by POCl ₃ according to a thickness difference of a polysilicon film for a dummy gate. It relates to a method of forming a dummy gate for planarization.

본 발명은 반도체장치의 제조공정중 평탄화용 더미 게이트를 형성하는데 있어서, 실리콘 기판상에 게이트 산화막을 형성하는 공정과, 게이트 산화막상에 더미 게이트용 폴리실리콘막을 증착하는 공정과, 더미 게이트 오픈영역의 폴릭실리콘막을 일정 두께만큼 식각하여 주는 공정과, 기판으로 POCl₃를 침적시켜 두께가 낮은 폴리실리콘막 하부의 게이트 산화막에 페일을 유도하여 기판과 연결시켜 주는 공정을 포함한다.The present invention provides a planarization dummy gate during the manufacturing process of a semiconductor device, comprising: forming a gate oxide film on a silicon substrate; depositing a dummy gate polysilicon film on the gate oxide film; Etching the polysilicon film to a predetermined thickness; and depositing POCl ₃ onto the substrate to induce a fail in the gate oxide film under the low polysilicon film to connect the substrate to the substrate.

Description

Dummy gate formation method for planarization of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도(A)와 (B)는 더미 게이트를 이용한 반도체장치의 CMP평탄화공정도.2A and 2B are CMP flattening process diagrams of a semiconductor device using a dummy gate.

Claims

In forming a planarization dummy gate during the manufacturing process of a semiconductor device, a process of forming a gate oxide film 42 on a silicon substrate 41 and a polysilicon film 43 for a dummy gate on a gate oxide film 41 are performed. A process of depositing, etching the polysilicon film 43 in the dummy gate open region C by a predetermined thickness, and depositing POCL ₃ 46 on the substrate to lower the lower polysilicon film 43 '. And forming a fail in the gate oxide layer (42) of the gate oxide layer (42) to connect the substrate to the substrate.

The planarization dummy gate forming method according to claim 1, wherein the dummy gate polysilicon layer is etched to have a thickness such that a fail of the gate oxide layer 42 is induced.

※ Note: The disclosure is based on the initial application.