KR970030214A - Wafer Planarization Method - Google Patents

Wafer Planarization Method Download PDF

Info

Publication number
KR970030214A
KR970030214A KR1019950039932A KR19950039932A KR970030214A KR 970030214 A KR970030214 A KR 970030214A KR 1019950039932 A KR1019950039932 A KR 1019950039932A KR 19950039932 A KR19950039932 A KR 19950039932A KR 970030214 A KR970030214 A KR 970030214A
Authority
KR
South Korea
Prior art keywords
etch stop
stop layer
wafer
film
forming
Prior art date
Application number
KR1019950039932A
Other languages
Korean (ko)
Inventor
김영서
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950039932A priority Critical patent/KR970030214A/en
Publication of KR970030214A publication Critical patent/KR970030214A/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자 제조 공정에서의 웨이퍼 평탄화 방법에 있어서; 타포로지가 형성된 웨이퍼 전체구조 상부 표면을 따라 소정 두께 식각정지층을 형성하는 단계; 상기 식각정지층 상에 층간절연막을 형성하는 단계; 전체구조 상부에 감광막을 도포하는 단계; 상기 감광막과 상기 층간절연막을 상기 식각정지층이 식각되기 시작할 때까지 에치백하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 평탄화 방법에 관한 것으로, 한 웨이퍼 내의 두께 차이 감소(타포로지 완화)및 웨이퍼 대 웨이퍼의 균일성이 증가를 가져오는 효과가 있다.The present invention provides a wafer planarization method in a semiconductor device manufacturing process; Forming an etch stop layer having a predetermined thickness along the upper surface of the wafer overall structure on which the taripology is formed; Forming an interlayer insulating film on the etch stop layer; Applying a photoresist film on the entire structure; And etching back the photoresist and the interlayer dielectric layer until the etch stop layer begins to be etched. There is an effect of increasing the uniformity of the wafer.

Description

웨이퍼 평탄화 방법Wafer Planarization Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 웨이퍼 평탄화 공정 나타내는 일 예시도.2 is an exemplary view showing a wafer planarization process of the present invention.

Claims (4)

반도체 소자 제조 공정에서의 웨이퍼 평탄화 방법에 있어서; 타포로지가 형성된 웨이퍼 전체구조 상부 표면을 따라 소정 두께 식각정지층을 형성하는 단계; 상기 식각정지층 상에 층간절연막을 형성하는 단계; 전체구조 상부에 감광막을 도포하는 단계; 상기 감광막과 상기 층간절연막을 상기 식각되기 시작할 때까지 에치벡하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 평탄화 방법.A wafer planarization method in a semiconductor device manufacturing process; Forming an etch stop layer having a predetermined thickness along the upper surface of the wafer overall structure on which the taripology is formed; Forming an interlayer insulating film on the etch stop layer; Applying a photoresist film on the entire structure; And etching the photosensitive film and the interlayer insulating film until the etching begins. 제1항에 있어서, 상기 식각정지층은 상기 층간절연막과 식각 선택비를 갖는 것을 특징으로 하는 웨이퍼 평탄화 방법.The method of claim 1, wherein the etch stop layer has an etch selectivity with the interlayer insulating layer. 제2항에 있어서; 상기 식각정지층은 절연막인 것을 특징으로 하는 웨이퍼 평탄화 방법.The method of claim 2; And the etch stop layer is an insulating film. 제2항에 있어서; 상기 식각정지층은 질화막 또는 폴리실리콘막인 것을 특징으로 하는 웨이퍼 평탄화 방법.The method of claim 2; And the etch stop layer is a nitride film or a polysilicon film.
KR1019950039932A 1995-11-06 1995-11-06 Wafer Planarization Method KR970030214A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950039932A KR970030214A (en) 1995-11-06 1995-11-06 Wafer Planarization Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950039932A KR970030214A (en) 1995-11-06 1995-11-06 Wafer Planarization Method

Publications (1)

Publication Number Publication Date
KR970030214A true KR970030214A (en) 1997-06-26

Family

ID=66586973

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950039932A KR970030214A (en) 1995-11-06 1995-11-06 Wafer Planarization Method

Country Status (1)

Country Link
KR (1) KR970030214A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59217339A (en) * 1983-05-26 1984-12-07 Toshiba Corp Manufacture of semiconductor device
JPH0482263A (en) * 1990-07-25 1992-03-16 Sharp Corp Semiconductor storage device
JPH06267985A (en) * 1993-03-17 1994-09-22 Fujitsu Ltd Method of manufacturing semiconductor device
JPH0745616A (en) * 1993-07-29 1995-02-14 Nec Corp Manufacture of semiconductor device
JPH07240466A (en) * 1994-03-02 1995-09-12 Fujitsu Ltd Fabrication of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59217339A (en) * 1983-05-26 1984-12-07 Toshiba Corp Manufacture of semiconductor device
JPH0482263A (en) * 1990-07-25 1992-03-16 Sharp Corp Semiconductor storage device
JPH06267985A (en) * 1993-03-17 1994-09-22 Fujitsu Ltd Method of manufacturing semiconductor device
JPH0745616A (en) * 1993-07-29 1995-02-14 Nec Corp Manufacture of semiconductor device
JPH07240466A (en) * 1994-03-02 1995-09-12 Fujitsu Ltd Fabrication of semiconductor device

Similar Documents

Publication Publication Date Title
KR940010205A (en) Contact hole formation method of highly integrated semiconductor device
KR970054033A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970030214A (en) Wafer Planarization Method
KR970051844A (en) Method for forming alignment key pattern of semiconductor device
KR970030404A (en) Interlayer insulating film planarization method of semiconductor device
KR940010366A (en) Method for manufacturing contact hole of semiconductor device
KR960039285A (en) Semiconductor device manufacturing method
KR0151191B1 (en) Manufacture of semiconductor memory device
KR970052386A (en) Metal wiring formation method of semiconductor device
KR960036043A (en) MOS transistor manufacturing method having a multilayer gate electrode
KR970077456A (en) Method of forming a contact hole in a semiconductor device
KR970060387A (en) Method for manufacturing semiconductor device
KR960005957A (en) How to Form Multilayer Wiring
KR970024299A (en) Semiconductor device manufacturing method
KR970003520A (en) Contact hole formation method of a fine semiconductor device
KR960030327A (en) Contact hole formation method of semiconductor device
KR970030363A (en) Manufacturing method of semiconductor device
KR960026568A (en) Device isolation insulating film manufacturing method of semiconductor device
KR980005466A (en) Metal wiring formation method of semiconductor device
KR970053372A (en) Device Separation Method of Semiconductor Device
KR970030355A (en) Method of forming interlayer insulating film for forming highly reliable via contact
KR970067637A (en) Method of manufacturing gate of semiconductor device
KR970023755A (en) Insulation method between conductive layers in semiconductor devices
KR970052415A (en) Contact formation method of a semiconductor device using a double insulating film
KR940004836A (en) Contact hole formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application