KR930005652B1 - Nand 게이트 회로 - Google Patents

Nand 게이트 회로 Download PDF

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Publication number
KR930005652B1
KR930005652B1 KR1019890015523A KR890015523A KR930005652B1 KR 930005652 B1 KR930005652 B1 KR 930005652B1 KR 1019890015523 A KR1019890015523 A KR 1019890015523A KR 890015523 A KR890015523 A KR 890015523A KR 930005652 B1 KR930005652 B1 KR 930005652B1
Authority
KR
South Korea
Prior art keywords
nand gate
driving
gate circuit
transistor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019890015523A
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English (en)
Korean (ko)
Other versions
KR900007188A (ko
Inventor
마사노부 요시다
Original Assignee
후지쓰 가부시끼가이샤
야마모도 다꾸마
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼가이샤, 야마모도 다꾸마 filed Critical 후지쓰 가부시끼가이샤
Publication of KR900007188A publication Critical patent/KR900007188A/ko
Application granted granted Critical
Publication of KR930005652B1 publication Critical patent/KR930005652B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Dram (AREA)
KR1019890015523A 1988-10-27 1989-10-27 Nand 게이트 회로 Expired - Lifetime KR930005652B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-269408 1988-10-27
JP63269408A JP2555165B2 (ja) 1988-10-27 1988-10-27 ナンド回路

Publications (2)

Publication Number Publication Date
KR900007188A KR900007188A (ko) 1990-05-09
KR930005652B1 true KR930005652B1 (ko) 1993-06-23

Family

ID=17471999

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890015523A Expired - Lifetime KR930005652B1 (ko) 1988-10-27 1989-10-27 Nand 게이트 회로

Country Status (5)

Country Link
US (1) US5059825A (enExample)
EP (1) EP0366489B1 (enExample)
JP (1) JP2555165B2 (enExample)
KR (1) KR930005652B1 (enExample)
DE (1) DE68923343T2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2928651B2 (ja) * 1991-03-19 1999-08-03 株式会社日立製作所 通信機能を備えた制御装置
US5146115A (en) * 1991-07-26 1992-09-08 Zilog, Inc. Domino-logic decoder
US5391941A (en) * 1993-09-23 1995-02-21 Cypress Semiconductor Corporation Decoder circuitry with balanced propagation delay and minimized input capacitance
US7821866B1 (en) 2007-11-14 2010-10-26 Cypress Semiconductor Corporation Low impedance column multiplexer circuit and method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5315055A (en) * 1976-07-27 1978-02-10 Toshiba Corp Logic circuit
US4250406A (en) * 1978-12-21 1981-02-10 Motorola, Inc. Single clock CMOS logic circuit with selected threshold voltages
JPS5767333A (en) * 1980-10-15 1982-04-23 Matsushita Electric Ind Co Ltd Mos integrated circuit
JPS5979487A (ja) * 1982-10-27 1984-05-08 Nec Corp デコ−ダ回路
US4649296A (en) * 1984-07-13 1987-03-10 At&T Bell Laboratories Synthetic CMOS static logic gates
JPS61265794A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体記憶装置のデコ−ダ回路
FR2596595B1 (fr) * 1986-03-28 1988-05-13 Radiotechnique Compelec Porte logique mos du type domino
JPS63228494A (ja) * 1987-03-18 1988-09-22 Fujitsu Ltd ダイナミツク型デコ−ダ回路
US4797580A (en) * 1987-10-29 1989-01-10 Northern Telecom Limited Current-mirror-biased pre-charged logic circuit
US4851716A (en) * 1988-06-09 1989-07-25 National Semiconductor Corporation Single plane dynamic decoder

Also Published As

Publication number Publication date
EP0366489A2 (en) 1990-05-02
KR900007188A (ko) 1990-05-09
DE68923343T2 (de) 1995-11-23
US5059825A (en) 1991-10-22
EP0366489A3 (en) 1990-08-16
JP2555165B2 (ja) 1996-11-20
JPH02117212A (ja) 1990-05-01
US5059825B1 (enExample) 1992-11-10
DE68923343D1 (de) 1995-08-10
EP0366489B1 (en) 1995-07-05

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