KR930003551A - 순간 테스트 모드 지정회로 - Google Patents

순간 테스트 모드 지정회로 Download PDF

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Publication number
KR930003551A
KR930003551A KR1019910012043A KR910012043A KR930003551A KR 930003551 A KR930003551 A KR 930003551A KR 1019910012043 A KR1019910012043 A KR 1019910012043A KR 910012043 A KR910012043 A KR 910012043A KR 930003551 A KR930003551 A KR 930003551A
Authority
KR
South Korea
Prior art keywords
signal
output
level
ground
test mode
Prior art date
Application number
KR1019910012043A
Other languages
English (en)
Other versions
KR930009490B1 (ko
Inventor
김학근
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910012043A priority Critical patent/KR930009490B1/ko
Priority to DE4223127A priority patent/DE4223127C2/de
Priority to JP4186773A priority patent/JP3006961B2/ja
Priority to TW081105604A priority patent/TW201371B/zh
Priority to US07/913,323 priority patent/US5402063A/en
Publication of KR930003551A publication Critical patent/KR930003551A/ko
Application granted granted Critical
Publication of KR930009490B1 publication Critical patent/KR930009490B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

내용 없음.

Description

순간 테스트 모드 지정회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 순간 테스트 모드 지정회로의 블록 구성도,
제3도는 제2도의 상세 회로도.

Claims (1)

  1. 그라운드 레벨이하의 입력신호(VIN)를 받아 이를 클램핑 다이오드(M12)에 의해 그라운드의 전위로 변환하고 그라운드 이상의 입력(VIN)이 인가되면 이를 검출하여 전원 전압(VDD)의 레벨로 출력하는 레벨 검출부(10)와, 상기 레벨 검출부(10)의 출력신호를 인가받아 완만한 입력파형을 정상적인 구형파로 변환하는 쉬미트 트리거부(20)와, 상기 쉬미트 트리거부(20)의 출력을 클럭신호(CK)로 인가받아서 클럭신호(K)가 인가될 때마다 데스트 인에이블 신호(TESTEN)와 디스에이블 신호를 교번 출력하고 파워의 온시에 발생하는 리세트 신호(RST)를 인가받아 출력(TESTEN)을 클리어하여 정상 동작상태가 되게하는 래치부(30)를 포함하여 구성한 것을 특징으로 하는 순간 테스트 모드 지정회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910012043A 1991-07-15 1991-07-15 순간 테스트 모드 지정회로 KR930009490B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019910012043A KR930009490B1 (ko) 1991-07-15 1991-07-15 순간 테스트 모드 지정회로
DE4223127A DE4223127C2 (de) 1991-07-15 1992-07-14 Schaltkreis zum Herbeiführen eines Prüfbetriebszustands für Halbleiterschaltungen
JP4186773A JP3006961B2 (ja) 1991-07-15 1992-07-14 瞬間テストモード指定回路
TW081105604A TW201371B (ko) 1991-07-15 1992-07-15
US07/913,323 US5402063A (en) 1991-07-15 1992-07-15 Momentary test mode enabling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910012043A KR930009490B1 (ko) 1991-07-15 1991-07-15 순간 테스트 모드 지정회로

Publications (2)

Publication Number Publication Date
KR930003551A true KR930003551A (ko) 1993-02-24
KR930009490B1 KR930009490B1 (ko) 1993-10-04

Family

ID=19317293

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910012043A KR930009490B1 (ko) 1991-07-15 1991-07-15 순간 테스트 모드 지정회로

Country Status (5)

Country Link
US (1) US5402063A (ko)
JP (1) JP3006961B2 (ko)
KR (1) KR930009490B1 (ko)
DE (1) DE4223127C2 (ko)
TW (1) TW201371B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459227B1 (ko) * 2002-07-08 2004-12-03 매그나칩 반도체 유한회사 다이나믹 로직 회로

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US5982188A (en) * 1994-07-29 1999-11-09 Stmicroelectronics, Inc. Test mode control circuit of an integrated circuit device
KR0138233B1 (ko) * 1994-12-16 1998-06-15 김광호 마이크로 컨트롤러의 테스트회로
KR100239692B1 (ko) * 1996-07-27 2000-01-15 김영환 반도체 장치의 출력회로
US6037792A (en) * 1996-12-21 2000-03-14 Stmicroelectronics, Inc. Burn-in stress test mode
US5804996A (en) * 1997-02-13 1998-09-08 Ramtron International Corporation Low-power non-resetable test mode circuit
US6046617A (en) * 1998-06-25 2000-04-04 National Semiconductor Corporation CMOS level detection circuit with hysteresis having disable/enable function and method
DE10064478B4 (de) * 2000-12-22 2005-02-24 Atmel Germany Gmbh Verfahren zur Prüfung einer integrierten Schaltung und Schaltungsanordnung
JP4887928B2 (ja) * 2006-06-21 2012-02-29 株式会社デンソー 車両用通信システムの受信装置
JP4299856B2 (ja) * 2006-12-14 2009-07-22 エルピーダメモリ株式会社 半導体装置
KR101171561B1 (ko) * 2010-09-29 2012-08-06 삼성전기주식회사 펄스 폭에 따라 동작하는 슈미트 트리거 회로
WO2015094374A1 (en) * 2013-12-20 2015-06-25 Intel Corporation Apparatus for charge recovery during low power mode
CN110632285B (zh) * 2019-09-23 2022-09-06 三诺生物传感股份有限公司 血糖仪设备
US11144104B2 (en) * 2020-02-14 2021-10-12 Silicon Laboratories Inc. Mode selection circuit for low-cost integrated circuits such as microcontrollers
CN114545021A (zh) * 2022-02-25 2022-05-27 南京理工大学 高精度瞬态爆速测量装置
CN116256622B (zh) * 2023-05-15 2023-08-08 苏州贝克微电子股份有限公司 一种芯片的测试模式控制电路及控制方法

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DE2905294A1 (de) * 1979-02-12 1980-08-21 Philips Patentverwaltung Integrierte schaltungsanordnung in mos-technik mit feldeffekttransistoren
US4295062A (en) * 1979-04-02 1981-10-13 National Semiconductor Corporation CMOS Schmitt trigger and oscillator
US4301379A (en) * 1979-10-17 1981-11-17 Ncr Corporation Latching Schmitt trigger circuit
US4471235A (en) * 1982-05-03 1984-09-11 Data General Corporation Short pulse width noise immunity discriminator circuit
JPS58207711A (ja) * 1982-05-28 1983-12-03 Nec Corp フリツプフロツプ回路
JPS58215134A (ja) * 1982-06-08 1983-12-14 Mitsubishi Electric Corp インバ−タ回路
US4816757A (en) * 1985-03-07 1989-03-28 Texas Instruments Incorporated Reconfigurable integrated circuit for enhanced testing in a manufacturing environment
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
US4733168A (en) * 1986-03-21 1988-03-22 Harris Corporation Test enabling circuit for enabling overhead test circuitry in programmable devices
JP2721151B2 (ja) * 1986-04-01 1998-03-04 株式会社東芝 半導体集積回路装置
US4727270A (en) * 1986-05-08 1988-02-23 North American Philips Corporation Noise immune circuit for use with frequency sensor
JPS6339200A (ja) * 1986-08-04 1988-02-19 Sony Corp 集積回路装置
US5051995A (en) * 1988-03-14 1991-09-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a test mode setting circuit
JPH01248073A (ja) * 1988-03-29 1989-10-03 Nec Corp テスト信号発生回路
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459227B1 (ko) * 2002-07-08 2004-12-03 매그나칩 반도체 유한회사 다이나믹 로직 회로

Also Published As

Publication number Publication date
JPH05217399A (ja) 1993-08-27
JP3006961B2 (ja) 2000-02-07
US5402063A (en) 1995-03-28
TW201371B (ko) 1993-03-01
DE4223127C2 (de) 2001-01-04
DE4223127A1 (de) 1993-01-21
KR930009490B1 (ko) 1993-10-04

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