KR920700430A - 2원신호의 다수결 선택의 로직 네트워크내의 잠재착오를 회피하는 방법 - Google Patents

2원신호의 다수결 선택의 로직 네트워크내의 잠재착오를 회피하는 방법

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Publication number
KR920700430A
KR920700430A KR1019900702565A KR900702565A KR920700430A KR 920700430 A KR920700430 A KR 920700430A KR 1019900702565 A KR1019900702565 A KR 1019900702565A KR 900702565 A KR900702565 A KR 900702565A KR 920700430 A KR920700430 A KR 920700430A
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KR
South Korea
Prior art keywords
logic
devices
nand
majority vote
operations
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KR1019900702565A
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English (en)
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KR950005528B1 (ko
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렌나르트 하우린 토오드
Original Assignee
에케 스타브링 타게 뢰브그랜
테레포오낙티이에보라겟트 엘엠엘리크썬
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Publication of KR920700430A publication Critical patent/KR920700430A/ko
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/187—Voting techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Logic Circuits (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Hardware Redundancy (AREA)
  • Radio Transmission System (AREA)
  • Small-Scale Networks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음

Description

2원 신호의 다수결 선택의 로직 네트워크내의 잠재착오를 회피하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 3중장치의 부분을 예시하는 도면,
제2도와 제3도는 제1도에서 보여준 장치내에 종합된 다수결 선택 장치의 2개의 상이한 예의 실시예를 예시한 도면.

Claims (5)

  1. 3중장치에서 2원신호의 다수결 선택로직 네트워크에서의 잠재착오를 회피하는 방법으로 그 로직네트워크는 로직조작 즉 NAND- 또는 NOR 조작을 수행하는 복수의 분할로직장치를 포함하고, 각 분할로직장치에는 병렬연결 반도체 부품들을 포함하며, 각기 그들은 각 로직입력신호를 수신하고 또한 직렬연결 반도체 부품들을 포함하고 각기 그들은 각 로직 입력신호를 수신하며, 상기한 각 로직장치들(21-24, 31-34, 71-74, 81-84, 91-94, 101-104)은 그러한 방법으로 반복하여 스위치 절환을 하기때문에 그들 반도체 부품들은 병렬연결되어 있어, 직렬연결, 그리고 그 반대로도 되게 스위치 절환되고, 그것으로 상기한 각 로직장치는 서로가 2중 통신인, 즉 NAND- 와 NOR 조작인 교체적 로직조작을 수행하는데 양측의 각 장치내의 같은 반도체 부품의 도움으로 되며 그것으로 실제로 다수결 선택이 2개의 상호 상이한 로직네트워크의 도움으로 교체적 효력을 내게되며 각기 다른 것의 2중 통신이 되어있게 하는 것을 특징으로 하는 잠재착오 회피방법.
  2. 제1항에 있어서, 4개의 로직 NAND- 장치(21-24)와 4개의 로직 NOR- 장치(31-34)로 교대적으로 다수결 선택효력을 내는 것을 특징으로 하는 잠재착오 회피방법.
  3. 제1항에 있어서, 상기한 다수결 선택이 한쪽에서 3개의 로직 NAND- 장치(81-83)로서 효력을 내는데 각기 각 후속변환기(85-87)와 후속변환기(88)를 갖인 로직 NOR- 장치(85)를 갖이며, 3개의 로직 NOR 장치(91-93)를 갖는 제2폭에서, 각기 각 후속변환기(85-87)를 갖고, 후속변환기(88)를 갖인 로직 NAND- 장치(94)를 갖는 것을 특징으로 하는 잠재착오 회피방법.
  4. 제1항에 있어서, 상기한 다수결 선택이 교대적으로 한쪽에서는 3개의 로직 AND-장치(71-73)와 로직 OR-장치(74)의 도움으로 효력을 내고 다른쪽에서는 3개의 로직 OR-장치(101-103)와 로직 AND-장치(104)의 도움으로 효력을 내는 것을 특징으로 하는 잠재착오 회피방법.
  5. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900702565A 1989-05-12 1990-05-03 이진신호의 다수결선택에 대한 논리회로망에서의 잠재성에러를 방지하는 방법 KR950005528B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE8901723A SE465056B (sv) 1989-05-12 1989-05-12 Foerfarande foer att undvika latenta fel i ett logiknaet foer majoritetsval av binaera signaler
SE8901723-0 1989-05-12
PCT/SE1990/000290 WO1990013869A1 (en) 1989-05-12 1990-05-03 A method for avoiding latent errors in a logic network for majority selection of binary signals

Publications (2)

Publication Number Publication Date
KR920700430A true KR920700430A (ko) 1992-02-19
KR950005528B1 KR950005528B1 (ko) 1995-05-25

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Application Number Title Priority Date Filing Date
KR1019900702565A KR950005528B1 (ko) 1989-05-12 1990-05-03 이진신호의 다수결선택에 대한 논리회로망에서의 잠재성에러를 방지하는 방법

Country Status (15)

Country Link
US (1) US5140594A (ko)
EP (1) EP0397632B1 (ko)
JP (1) JP2963763B2 (ko)
KR (1) KR950005528B1 (ko)
AU (1) AU622029B2 (ko)
BR (1) BR9006762A (ko)
CA (1) CA2032519C (ko)
DE (1) DE69010275T2 (ko)
DK (1) DK0397632T3 (ko)
ES (1) ES2055405T3 (ko)
FI (1) FI98571C (ko)
IE (1) IE66200B1 (ko)
NO (1) NO178557C (ko)
SE (1) SE465056B (ko)
WO (1) WO1990013869A1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100728954B1 (ko) * 2005-06-03 2007-06-15 주식회사 하이닉스반도체 디지털 방식의 다수결 판정 회로

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3229135B2 (ja) * 1994-09-14 2001-11-12 三菱電機株式会社 アナログ／デジタル変換装置
US5568067A (en) * 1995-06-30 1996-10-22 Cyrix Corporation Configurable XNOR/XOR element
TW325608B (en) * 1996-04-17 1998-01-21 Toshiba Co Ltd Timing signal generation circuit and a display device using such a circuit
US5982199A (en) * 1998-01-13 1999-11-09 Advanced Micro Devices, Inc. Faster NAND for microprocessors utilizing unevenly sub-nominal P-channel and N-channel CMOS transistors with reduced overlap capacitance
US7363546B2 (en) * 2002-07-31 2008-04-22 Sun Microsystems, Inc. Latent fault detector
US7333099B2 (en) * 2003-01-06 2008-02-19 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit, display device, and electronic apparatus
US7308605B2 (en) * 2004-07-20 2007-12-11 Hewlett-Packard Development Company, L.P. Latent error detection
US7236005B1 (en) * 2005-02-09 2007-06-26 Intel Corporation Majority voter circuit design
US8739010B2 (en) * 2010-11-19 2014-05-27 Altera Corporation Memory array with redundant bits and memory element voting circuits
RU2618192C1 (ru) * 2016-03-09 2017-05-02 федеральное государственное бюджетное образовательное учреждение высшего образования "Пермский национальный исследовательский политехнический университет" Мажоритарное устройство
WO2018048723A1 (en) 2016-09-09 2018-03-15 The Charles Stark Draper Laboratory, Inc. Methods and systems for achieving trusted fault tolerance of a system of untrusted subsystems

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4375683A (en) * 1980-11-12 1983-03-01 August Systems Fault tolerant computational system and voter circuit
GB2093614B (en) * 1981-02-19 1984-10-17 Plessey Co Ltd Triply redundant microprocessor system
US4355683A (en) * 1981-05-11 1982-10-26 Midland-Ross Corporation System of moisture and temperature conditioning air using a solar pond
US4555721A (en) * 1981-05-19 1985-11-26 International Business Machines Corporation Structure of stacked, complementary MOS field effect transistor circuits
US4468574A (en) * 1982-05-03 1984-08-28 General Electric Company Dual gate CMOS transistor circuits having reduced electrode capacitance
JPS5985153A (ja) * 1982-11-08 1984-05-17 Hitachi Ltd 冗長化制御装置
US4617475A (en) * 1984-03-30 1986-10-14 Trilogy Computer Development Partners, Ltd. Wired logic voting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100728954B1 (ko) * 2005-06-03 2007-06-15 주식회사 하이닉스반도체 디지털 방식의 다수결 판정 회로

Also Published As

Publication number Publication date
DE69010275T2 (de) 1994-10-13
IE901680L (en) 1990-11-12
AU622029B2 (en) 1992-03-26
JPH03506089A (ja) 1991-12-26
IE66200B1 (en) 1995-12-13
FI910022A0 (fi) 1991-01-02
NO178557C (no) 1996-04-17
EP0397632A1 (en) 1990-11-14
CA2032519C (en) 2000-07-11
DE69010275D1 (de) 1994-08-04
SE465056B (sv) 1991-07-15
SE8901723D0 (sv) 1989-05-12
NO910014L (no) 1991-01-03
AU5674090A (en) 1990-11-29
WO1990013869A1 (en) 1990-11-15
CA2032519A1 (en) 1990-11-13
EP0397632B1 (en) 1994-06-29
JP2963763B2 (ja) 1999-10-18
NO910014D0 (no) 1991-01-03
NO178557B (no) 1996-01-08
FI98571B (fi) 1997-03-27
FI98571C (sv) 1997-07-10
KR950005528B1 (ko) 1995-05-25
BR9006762A (pt) 1991-08-13
DK0397632T3 (da) 1994-10-31
SE8901723L (ko) 1990-11-13
ES2055405T3 (es) 1994-08-16
US5140594A (en) 1992-08-18

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