SE8901723D0 - Foerfarande foer att undvika latenta fel i ett logiknaet foer majoritetsval av binaera signaler och styrbart i logikorgen foer utfoerande av en logisk operation - Google Patents

Foerfarande foer att undvika latenta fel i ett logiknaet foer majoritetsval av binaera signaler och styrbart i logikorgen foer utfoerande av en logisk operation

Info

Publication number
SE8901723D0
SE8901723D0 SE19898901723A SE8901723A SE8901723D0 SE 8901723 D0 SE8901723 D0 SE 8901723D0 SE 19898901723 A SE19898901723 A SE 19898901723A SE 8901723 A SE8901723 A SE 8901723A SE 8901723 D0 SE8901723 D0 SE 8901723D0
Authority
SE
Sweden
Prior art keywords
logic
errors
binary signals
majority selection
controllable
Prior art date
Application number
SE19898901723A
Other languages
English (en)
Other versions
SE8901723L (sv
SE465056B (sv
Inventor
L * Haulin T
Original Assignee
Telefonaktiebolaget L M Ericsson Patent-Och Varumaerkesa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget L M Ericsson Patent-Och Varumaerkesa filed Critical Telefonaktiebolaget L M Ericsson Patent-Och Varumaerkesa
Priority to SE8901723A priority Critical patent/SE465056B/sv
Publication of SE8901723D0 publication Critical patent/SE8901723D0/sv
Priority to US07/510,831 priority patent/US5140594A/en
Priority to JP2508091A priority patent/JP2963763B2/ja
Priority to DE69010275T priority patent/DE69010275T2/de
Priority to BR909006762A priority patent/BR9006762A/pt
Priority to CA002032519A priority patent/CA2032519C/en
Priority to AU56740/90A priority patent/AU622029B2/en
Priority to EP90850162A priority patent/EP0397632B1/en
Priority to DK90850162.0T priority patent/DK0397632T3/da
Priority to PCT/SE1990/000290 priority patent/WO1990013869A1/en
Priority to ES90850162T priority patent/ES2055405T3/es
Priority to KR1019900702565A priority patent/KR950005528B1/ko
Priority to IE168090A priority patent/IE66200B1/en
Publication of SE8901723L publication Critical patent/SE8901723L/xx
Priority to FI910022A priority patent/FI98571C/sv
Priority to NO910014A priority patent/NO178557C/no
Publication of SE465056B publication Critical patent/SE465056B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/187—Voting techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Hardware Redundancy (AREA)
  • Radio Transmission System (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Small-Scale Networks (AREA)
SE8901723A 1989-05-12 1989-05-12 Foerfarande foer att undvika latenta fel i ett logiknaet foer majoritetsval av binaera signaler SE465056B (sv)

Priority Applications (15)

Application Number Priority Date Filing Date Title
SE8901723A SE465056B (sv) 1989-05-12 1989-05-12 Foerfarande foer att undvika latenta fel i ett logiknaet foer majoritetsval av binaera signaler
US07/510,831 US5140594A (en) 1989-05-12 1990-04-18 Method and device for avoiding latent errors in a logic network for majority selection of binary signals
KR1019900702565A KR950005528B1 (ko) 1989-05-12 1990-05-03 이진신호의 다수결선택에 대한 논리회로망에서의 잠재성에러를 방지하는 방법
AU56740/90A AU622029B2 (en) 1989-05-12 1990-05-03 A method for avoiding latent errors in a logic network for majority selection of binary signals
PCT/SE1990/000290 WO1990013869A1 (en) 1989-05-12 1990-05-03 A method for avoiding latent errors in a logic network for majority selection of binary signals
BR909006762A BR9006762A (pt) 1989-05-12 1990-05-03 Processo para evitar erros latentes em uma rede logica para selecao majoritaria de sinais binarios
CA002032519A CA2032519C (en) 1989-05-12 1990-05-03 Avoiding latent errors in a logic network for majority select ion of binary signals
JP2508091A JP2963763B2 (ja) 1989-05-12 1990-05-03 二進信号を多数決選択する論理回路網に潜在する誤りを除去する方法
EP90850162A EP0397632B1 (en) 1989-05-12 1990-05-03 Method for avoiding latent errors in a logic network for majority selection of binary signals
DK90850162.0T DK0397632T3 (da) 1989-05-12 1990-05-03 Fremgangsmåde til undgåelse af latente fejl i et logisk netværk til majoritetsudvælgelse af binære signaler
DE69010275T DE69010275T2 (de) 1989-05-12 1990-05-03 Methode zur Verhinderung von latenten Fehlern in einem logischen Netzwerk für Mehrheitsauswahl von binären Signalen.
ES90850162T ES2055405T3 (es) 1989-05-12 1990-05-03 Metodo para evitar errores latentes en una red logica para la seleccion mayoritaria de señales binarias.
IE168090A IE66200B1 (en) 1989-05-12 1990-05-09 A method for avoiding latent errors in a logic network for majority selection of binary signals
FI910022A FI98571C (sv) 1989-05-12 1991-01-02 Förfarade för att undvika latenta fel i ett logiknät för majoritetsvalav binära signaler
NO910014A NO178557C (no) 1989-05-12 1991-01-03 Fremgangsmåte for å unngå latente feil i et logikknettverk for majoritetsselektering av binære signaler

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8901723A SE465056B (sv) 1989-05-12 1989-05-12 Foerfarande foer att undvika latenta fel i ett logiknaet foer majoritetsval av binaera signaler

Publications (3)

Publication Number Publication Date
SE8901723D0 true SE8901723D0 (sv) 1989-05-12
SE8901723L SE8901723L (sv) 1990-11-13
SE465056B SE465056B (sv) 1991-07-15

Family

ID=20375945

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8901723A SE465056B (sv) 1989-05-12 1989-05-12 Foerfarande foer att undvika latenta fel i ett logiknaet foer majoritetsval av binaera signaler

Country Status (15)

Country Link
US (1) US5140594A (sv)
EP (1) EP0397632B1 (sv)
JP (1) JP2963763B2 (sv)
KR (1) KR950005528B1 (sv)
AU (1) AU622029B2 (sv)
BR (1) BR9006762A (sv)
CA (1) CA2032519C (sv)
DE (1) DE69010275T2 (sv)
DK (1) DK0397632T3 (sv)
ES (1) ES2055405T3 (sv)
FI (1) FI98571C (sv)
IE (1) IE66200B1 (sv)
NO (1) NO178557C (sv)
SE (1) SE465056B (sv)
WO (1) WO1990013869A1 (sv)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3229135B2 (ja) * 1994-09-14 2001-11-12 三菱電機株式会社 アナログ／デジタル変換装置
US5568067A (en) * 1995-06-30 1996-10-22 Cyrix Corporation Configurable XNOR/XOR element
TW325608B (en) * 1996-04-17 1998-01-21 Toshiba Co Ltd Timing signal generation circuit and a display device using such a circuit
US5982199A (en) * 1998-01-13 1999-11-09 Advanced Micro Devices, Inc. Faster NAND for microprocessors utilizing unevenly sub-nominal P-channel and N-channel CMOS transistors with reduced overlap capacitance
US7363546B2 (en) * 2002-07-31 2008-04-22 Sun Microsystems, Inc. Latent fault detector
US7333099B2 (en) * 2003-01-06 2008-02-19 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit, display device, and electronic apparatus
US7308605B2 (en) * 2004-07-20 2007-12-11 Hewlett-Packard Development Company, L.P. Latent error detection
US7236005B1 (en) * 2005-02-09 2007-06-26 Intel Corporation Majority voter circuit design
KR100728954B1 (ko) * 2005-06-03 2007-06-15 주식회사 하이닉스반도체 디지털 방식의 다수결 판정 회로
US8739010B2 (en) 2010-11-19 2014-05-27 Altera Corporation Memory array with redundant bits and memory element voting circuits
RU2618192C1 (ru) * 2016-03-09 2017-05-02 федеральное государственное бюджетное образовательное учреждение высшего образования "Пермский национальный исследовательский политехнический университет" Мажоритарное устройство
WO2018048720A1 (en) 2016-09-09 2018-03-15 The Charles Stark Draper Laboratory, Inc. Voting circuits and methods for trusted fault tolerance of a system of untrusted subsystems

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4375683A (en) * 1980-11-12 1983-03-01 August Systems Fault tolerant computational system and voter circuit
GB2093614B (en) * 1981-02-19 1984-10-17 Plessey Co Ltd Triply redundant microprocessor system
US4355683A (en) * 1981-05-11 1982-10-26 Midland-Ross Corporation System of moisture and temperature conditioning air using a solar pond
US4555721A (en) * 1981-05-19 1985-11-26 International Business Machines Corporation Structure of stacked, complementary MOS field effect transistor circuits
US4468574A (en) * 1982-05-03 1984-08-28 General Electric Company Dual gate CMOS transistor circuits having reduced electrode capacitance
JPS5985153A (ja) * 1982-11-08 1984-05-17 Hitachi Ltd 冗長化制御装置
US4617475A (en) * 1984-03-30 1986-10-14 Trilogy Computer Development Partners, Ltd. Wired logic voting circuit

Also Published As

Publication number Publication date
ES2055405T3 (es) 1994-08-16
SE8901723L (sv) 1990-11-13
JP2963763B2 (ja) 1999-10-18
FI98571C (sv) 1997-07-10
AU5674090A (en) 1990-11-29
IE901680L (en) 1990-11-12
NO178557C (no) 1996-04-17
CA2032519C (en) 2000-07-11
NO178557B (no) 1996-01-08
FI910022A0 (sv) 1991-01-02
EP0397632A1 (en) 1990-11-14
CA2032519A1 (en) 1990-11-13
NO910014L (no) 1991-01-03
BR9006762A (pt) 1991-08-13
IE66200B1 (en) 1995-12-13
WO1990013869A1 (en) 1990-11-15
SE465056B (sv) 1991-07-15
DK0397632T3 (da) 1994-10-31
EP0397632B1 (en) 1994-06-29
JPH03506089A (ja) 1991-12-26
AU622029B2 (en) 1992-03-26
DE69010275T2 (de) 1994-10-13
KR920700430A (ko) 1992-02-19
US5140594A (en) 1992-08-18
KR950005528B1 (ko) 1995-05-25
NO910014D0 (no) 1991-01-03
FI98571B (sv) 1997-03-27
DE69010275D1 (de) 1994-08-04

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