KR920013981A - 스크램블/디스크램블 회로 - Google Patents

스크램블/디스크램블 회로 Download PDF

Info

Publication number
KR920013981A
KR920013981A KR1019910022566A KR910022566A KR920013981A KR 920013981 A KR920013981 A KR 920013981A KR 1019910022566 A KR1019910022566 A KR 1019910022566A KR 910022566 A KR910022566 A KR 910022566A KR 920013981 A KR920013981 A KR 920013981A
Authority
KR
South Korea
Prior art keywords
bits
circuit
outputting
input
scramble
Prior art date
Application number
KR1019910022566A
Other languages
English (en)
Inventor
유이찌 고지마
Original Assignee
오오가 노리오
소니 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오오가 노리오, 소니 가부시끼가이샤 filed Critical 오오가 노리오
Publication of KR920013981A publication Critical patent/KR920013981A/ko

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/582Pseudo-random number generators
    • G06F7/584Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03866Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling
    • H04L25/03872Parallel scrambling or descrambling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/581Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/582Parallel finite field implementation, i.e. at least partially parallel implementation of finite field arithmetic, generating several new bits or trits per step, e.g. using a GF multiplier

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Error Detection And Correction (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음

Description

스크램블/디스크램블 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 스크램블/디스크램블 회로의 한 실시예의 구성을 나타내는 회로도, 제2도는 생성다항식의 갈로아체의 설명도, 제3도는 예에 대한 레지스터 출력의 설명도.

Claims (1)

  1. 차수n의 최대장계열을 사용하여, m비트를 병렬로 비트 스크램블 또는 디스크램블 하는 스크램블/디스크램블 회로에서, m비트의 입력데이타가 각각 한쪽의 입력에 공급되는 m개의 익스크루시브 오아게이트와, 차수(n)의 최대장계열의 생성 다항식에 의하여 부여되는 갈로아체상에서, 그 원을 α로 할때, 입력된 데이타에 αm를 승산하여 출력하는 p개의 승산회로와, 상기 승산회로에서 출력되는 n×p(m)비트의 데이타를 래치하고, 래치한 n×p비트를 재차 상기 승산회로에 출력하고, 래치한 데이타중, m비트의 데이타를, 상기 익스크루시브 오아게이트의 다른쪽 입력에 출력하는 n×p개의 레지스터를 가지는 것을 특징으로 하는 스크램블/디스크램블 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910022566A 1990-12-10 1991-12-10 스크램블/디스크램블 회로 KR920013981A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-409771 1990-12-10
JP2409771A JPH04213245A (ja) 1990-12-10 1990-12-10 スクランブル/デスクランブル回路

Publications (1)

Publication Number Publication Date
KR920013981A true KR920013981A (ko) 1992-07-30

Family

ID=18519057

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1019910022566A KR920013981A (ko) 1990-12-10 1991-12-10 스크램블/디스크램블 회로
KR1019910022566D KR950002753B1 (ko) 1990-12-10 1991-12-10 스크램블/디스크램블 회로

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1019910022566D KR950002753B1 (ko) 1990-12-10 1991-12-10 스크램블/디스크램블 회로

Country Status (5)

Country Link
US (1) US5231667A (ko)
EP (1) EP0490618B1 (ko)
JP (1) JPH04213245A (ko)
KR (2) KR920013981A (ko)
DE (1) DE69117154T2 (ko)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377270A (en) * 1993-06-30 1994-12-27 United Technologies Automotive, Inc. Cryptographic authentication of transmitted messages using pseudorandom numbers
US5363448A (en) * 1993-06-30 1994-11-08 United Technologies Automotive, Inc. Pseudorandom number generation and cryptographic authentication
US5680131A (en) * 1993-10-29 1997-10-21 National Semiconductor Corporation Security system having randomized synchronization code after power up
US5398284A (en) * 1993-11-05 1995-03-14 United Technologies Automotive, Inc. Cryptographic encoding process
US5844989A (en) * 1995-06-05 1998-12-01 Matsushita Electric Industrial Co., Ltd. Data scrambling method, data scrambling apparatus, data descrambling method, and data descrambling apparatus
KR100219481B1 (ko) * 1996-05-23 1999-09-01 윤종용 시디롬 디코더의 디스크램블링 데이타 생성방법 및그장치와이를이용한디스크램블러
US5966447A (en) * 1996-06-04 1999-10-12 Matsushita Electric Industrial Co., Ltd. Data scrambling method, data scrambling apparatus, data descrambling method, and data descrambling apparatus
JPH1041830A (ja) * 1996-07-24 1998-02-13 Matsushita Electric Ind Co Ltd 誤り訂正符号化回路とそれを用いた変調装置
SG76578A1 (en) * 1997-12-19 2000-11-21 Texas Instruments Inc A buffer bandwidth-saving implementation of dvd ecc
US5974144A (en) * 1998-02-25 1999-10-26 Cipheractive Ltd. System for encryption of partitioned data blocks utilizing public key methods and random numbers
DE19963962C1 (de) * 1999-12-31 2001-03-22 Bosch Gmbh Robert Pseudozufallsgenerator und Rundfunksender und Rundfunkempfänger
US7415112B2 (en) * 2002-09-18 2008-08-19 Zarbana Digital Fund Llc Parallel scrambler/descrambler
US20040091106A1 (en) * 2002-11-07 2004-05-13 Moore Frank H. Scrambling of data streams having arbitrary data path widths
DE102014209689A1 (de) * 2014-05-21 2015-11-26 Siemens Aktiengesellschaft Vorrichtung und Verfahren zum Erzeugen von Zufallsbits

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3784743A (en) * 1972-08-23 1974-01-08 Bell Telephone Labor Inc Parallel data scrambler
GB1597218A (en) * 1976-12-11 1981-09-03 Nat Res Dev Apparatus for electronic encypherment of digital data
US4797921A (en) * 1984-11-13 1989-01-10 Hitachi, Ltd. System for enciphering or deciphering data
US4815130A (en) * 1986-10-03 1989-03-21 Communications Satellite Corporation Stream cipher system with feedback
US4918638A (en) * 1986-10-15 1990-04-17 Matsushita Electric Industrial Co., Ltd. Multiplier in a galois field
JPH0783337B2 (ja) * 1988-03-01 1995-09-06 日本電気株式会社 スクランブル−デスクランブル方式
US4965881A (en) * 1989-09-07 1990-10-23 Northern Telecom Limited Linear feedback shift registers for data scrambling

Also Published As

Publication number Publication date
EP0490618A1 (en) 1992-06-17
DE69117154T2 (de) 1996-08-01
US5231667A (en) 1993-07-27
JPH04213245A (ja) 1992-08-04
KR950002753B1 (ko) 1995-03-24
EP0490618B1 (en) 1996-02-14
DE69117154D1 (de) 1996-03-28

Similar Documents

Publication Publication Date Title
KR920013981A (ko) 스크램블/디스크램블 회로
KR920001518A (ko) 반도체 집적회로
KR840005228A (ko) 갈로이스계의 원소 제산용 장치
KR920020971A (ko) 디지틀 전송 테스트 신호 발생 회로
KR960027615A (ko) 의사난수 잡음 발생 장치 및 방법
KR970029772A (ko) 비트-시리얼 메트릭스 전치를 위한 초대규모 집적회로
KR880011802A (ko) 반도체장치
KR940004464A (ko) 의사-난수 발생 장치 및 방법
KR910014805A (ko) 디지탈신호처리장치
JP2792242B2 (ja) 反転回路付きスクランブラ
KR0151913B1 (ko) 마스크 제어 이진 수열 발생기
KR100307705B1 (ko) 계층화된 직교부호 발생장치 및 그 방법
KR970012120A (ko) 룩업 테이블과 마스킹 회로를 이용한 비.알.엠(brm)장치
Fitzpatrick et al. Embedding group amalgams
KR920001325A (ko) 갈로이스 필드 2m에서의 곱셈 및 나눗셈 회로
KR970049467A (ko) 병렬 스크램블링 장치
KR960033140A (ko) 제로-런 디벨럽핑 run/level 세트용 회로와 제로-런 디벨럽핑 방법
SU445040A1 (ru) Устройство дл сравнени двоичных чисел
KR970053879A (ko) 스태틱 전류소모가 없는 반도체장치의 레벨쉬프터
KR0182166B1 (ko) 원하는 범위내의 데이타를 통과시키는 회로
KR970022730A (ko) 고속 가산 회로
KR980006901A (ko) 2비트 전가산기
KR920015247A (ko) 자동차량 추적장치의 메세지 떨림 방지회로
KR970004351A (ko) 주기적 직렬 신호 발생 장치
KR970056151A (ko) 병렬 스크램블러/디스크램블러

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090310

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee