KR920013726A - Stack Capacitor Cell Manufacturing Method - Google Patents

Stack Capacitor Cell Manufacturing Method Download PDF

Info

Publication number
KR920013726A
KR920013726A KR1019900021637A KR900021637A KR920013726A KR 920013726 A KR920013726 A KR 920013726A KR 1019900021637 A KR1019900021637 A KR 1019900021637A KR 900021637 A KR900021637 A KR 900021637A KR 920013726 A KR920013726 A KR 920013726A
Authority
KR
South Korea
Prior art keywords
oxide film
film
gate
forming
etching
Prior art date
Application number
KR1019900021637A
Other languages
Korean (ko)
Other versions
KR930006979B1 (en
Inventor
승성표
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900021637A priority Critical patent/KR930006979B1/en
Publication of KR920013726A publication Critical patent/KR920013726A/en
Application granted granted Critical
Publication of KR930006979B1 publication Critical patent/KR930006979B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

스택커패시터 셀 제조방법Stack Capacitor Cell Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 공정단면도2 is a cross-sectional view of the process of the present invention.

Claims (2)

기판위에 통상의 방법으로 필드산화막을 형성하고 게이트 산화막과 게이트 폴리실리콘막 및 게이트 캡 산화막을 차례로 형성하는 단계, 질화막을 전체적으로 증착하고 이를 에치하여 게이트 측벽질화막을 형성하는 단계,절연용 산화막을 전체적으로 이 위에 매몰콘택트 마스킹 공정을 거쳐 에치공정을 실시하여 매몰콘택트를 형성함과 동시에 자기정렬로 상기 게이트 캡 산화막의 표면일부를 제거하는 단계,게이트 캡 산화막과 매몰콘텍트 위에 커패시터 유전체막과 플레이트용 폴리실리콘막을 차례로 형성하는 단계가 차례로 포함됨을 특징으로 하는 스택커패시터 셀 제조방법.Forming a field oxide film on a substrate by a conventional method, sequentially forming a gate oxide film, a gate polysilicon film, and a gate cap oxide film, depositing a nitride film as a whole, and etching the nitride film to form a gate sidewall nitride film; Performing an etch process through an investment contact masking process to form an investment contact, and simultaneously removing a portion of the surface of the gate cap oxide film by self-alignment, and forming a capacitor dielectric film and a polysilicon film for a plate on the gate cap oxide film and the investment contact. Stack capacitor cell manufacturing method comprising the step of forming in sequence. 제 1항에 있어서, 상기 매몰콘택트 마스킹 공정후의 에치공정은 상기 절연용 산화막을 등방성 에치한다음 게이트 캡 산화막의 표면일부를 습식에치하는 순으로 진행되는 것을 특징으로 하는 스택 커패시터 셀 제조방법.The method of claim 1, wherein the etching process after the investment contact masking process is performed by isotropically etching the insulating oxide film and wet etching a portion of the surface of the gate cap oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900021637A 1990-12-24 1990-12-24 Method for fabricating of stacked capacitor cell KR930006979B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021637A KR930006979B1 (en) 1990-12-24 1990-12-24 Method for fabricating of stacked capacitor cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021637A KR930006979B1 (en) 1990-12-24 1990-12-24 Method for fabricating of stacked capacitor cell

Publications (2)

Publication Number Publication Date
KR920013726A true KR920013726A (en) 1992-07-29
KR930006979B1 KR930006979B1 (en) 1993-07-24

Family

ID=19308339

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021637A KR930006979B1 (en) 1990-12-24 1990-12-24 Method for fabricating of stacked capacitor cell

Country Status (1)

Country Link
KR (1) KR930006979B1 (en)

Also Published As

Publication number Publication date
KR930006979B1 (en) 1993-07-24

Similar Documents

Publication Publication Date Title
KR920013726A (en) Stack Capacitor Cell Manufacturing Method
KR920007143A (en) Fin-Stack Cell Manufacturing Method
KR950007106A (en) DRAM Cell Capacitor Manufacturing Method
KR940008072A (en) Capacitor manufacturing method having high storage capacity of semiconductor device
KR930008884B1 (en) Manufacturing method of stack capacitor cell
KR910017602A (en) Stack Cell Manufacturing Method
KR920007243A (en) Cylindrical Stack Capacitor Cell Manufacturing Method
KR920007070A (en) Method for manufacturing DRAM cell using self-aligned investment contact
KR960043155A (en) Method for manufacturing charge storage electrode of capacitor
KR920015596A (en) Stack Capacitor Manufacturing Method
KR970018556A (en) Capacitor Manufacturing Method of Semiconductor Memory Device
KR970030817A (en) Capacitor Manufacturing Method of Semiconductor Device
KR910013550A (en) High capacity stack cell manufacturing method
KR930003364A (en) Manufacturing Method of Semiconductor Device
KR970018585A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054044A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054043A (en) Capacitor Manufacturing Method of Semiconductor Memory Device
KR910013260A (en) DRAM manufacturing method
KR900017141A (en) Method of forming buried contacts during semiconductor device manufacturing
KR970054126A (en) Capacitor manufacturing method
KR930018721A (en) Method for manufacturing capacitor storage electrode of DRAM cell
KR960009152A (en) Semiconductor Memory Manufacturing Method
KR950021469A (en) Method of forming charge storage electrode of capacitor
KR970054132A (en) Cylindrical Capacitor Manufacturing Method
KR970024179A (en) Method for forming charge storage electrode of capacitor

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020618

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee