KR920007070A - Method for manufacturing DRAM cell using self-aligned investment contact - Google Patents

Method for manufacturing DRAM cell using self-aligned investment contact Download PDF

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Publication number
KR920007070A
KR920007070A KR1019900014385A KR900014385A KR920007070A KR 920007070 A KR920007070 A KR 920007070A KR 1019900014385 A KR1019900014385 A KR 1019900014385A KR 900014385 A KR900014385 A KR 900014385A KR 920007070 A KR920007070 A KR 920007070A
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KR
South Korea
Prior art keywords
polycrystalline silicon
self
dram cell
oxide film
cvd oxide
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KR1019900014385A
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Korean (ko)
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KR930008842B1 (en
Inventor
박준영
노재성
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문정환
금성일렉트론 주식회사
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Priority to KR1019900014385A priority Critical patent/KR930008842B1/en
Publication of KR920007070A publication Critical patent/KR920007070A/en
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Publication of KR930008842B1 publication Critical patent/KR930008842B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

자기정렬 매몰 콘택트를 이용한 디램 셀의 제조방법Manufacturing method of DRAM cell using self-aligned investment contact

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 종래의 제조공정을 나타낸 단면도.1 is a cross-sectional view showing a conventional manufacturing process.

제 2 도는 본발명의 제조공정을 나타낸 단면도.2 is a cross-sectional view showing a manufacturing process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 필드산화막1 substrate 2 field oxide film

3 : 게이트 4 : 질화막3: gate 4: nitride film

5 : CVD 산화막 6 : P/R5: CVD oxide film 6: P / R

7, 8, 10 : 다결정 실리콘 9 : 유전체막7, 8, 10: polycrystalline silicon 9: dielectric film

Claims (3)

기판위에 게이트 형성후 측벽을 형성한 것에 있어서, 상기 위에 질화막, CVD 산화막을 차례로 증착하는 공정 ; 이어 매몰 콘택트 P/R을 정의한 후 CVD 산화막을 식각하는 공정 ; 상기 질화막을 식각하여 매몰 콘택트를 형성하는 공정 ; 커패시터 노드로 사용될 다결정 실리콘을 형성하고 As이온 도핑 후 노드를 정의하여 건식식각하고 다시 다결정 실리콘을 형성하는 공정 ; 상기 다결정 실리콘을 RIE 건식식각하여 측벽을 형성하는 공정 ; 이어 통상의 유전체막, 플레이트용 다결정 실리콘을 형성하는 공정을 차례로 실시함을 특징으로 하는 자기정열 매몰 콘택트를 이용한 디램 셀의 제조방법.Forming a sidewall after the gate is formed on the substrate, comprising: depositing a nitride film and a CVD oxide film sequentially on the substrate; Subsequently etching the CVD oxide film after defining the buried contact P / R; Etching the nitride film to form a buried contact; Forming polycrystalline silicon to be used as a capacitor node, defining a node after doping As ion, and dry etching and forming polycrystalline silicon again; Dry etching the polycrystalline silicon to form sidewalls; Next, a method for manufacturing a DRAM cell using a self-aligned buried contact, which is performed in order to form a normal dielectric film and polycrystalline silicon for a plate. 제 1 항에 있어서, CVD 산화막은 10 : 1HF 용액에서 습식 식각함을 특징으로 하는 자기정열 매몰 콘택트를 이용한 디램 셀의 제조방법.The method of claim 1, wherein the CVD oxide film is wet etched in a 10: 1 HF solution. 제 1 항에 있어서, 질화막은 인산용액에서 습식 식각함을 특징으로 하는 자기정열 매몰 콘택트를 이용한 디램 셀의 제조방법.The method of claim 1, wherein the nitride film is wet etched in a phosphate solution. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900014385A 1990-09-12 1990-09-12 Dram cell manufacturing method KR930008842B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900014385A KR930008842B1 (en) 1990-09-12 1990-09-12 Dram cell manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900014385A KR930008842B1 (en) 1990-09-12 1990-09-12 Dram cell manufacturing method

Publications (2)

Publication Number Publication Date
KR920007070A true KR920007070A (en) 1992-04-28
KR930008842B1 KR930008842B1 (en) 1993-09-16

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Application Number Title Priority Date Filing Date
KR1019900014385A KR930008842B1 (en) 1990-09-12 1990-09-12 Dram cell manufacturing method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210156570A (en) 2020-06-18 2021-12-27 한국전력공사 Structure for Underground Power Line Branch Box of Pelletized Type Large Capacity

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210156570A (en) 2020-06-18 2021-12-27 한국전력공사 Structure for Underground Power Line Branch Box of Pelletized Type Large Capacity

Also Published As

Publication number Publication date
KR930008842B1 (en) 1993-09-16

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