KR0156096B1 - Trench stack dram device & its manufacturing method - Google Patents
Trench stack dram device & its manufacturing methodInfo
- Publication number
- KR0156096B1 KR0156096B1 KR1019890018825A KR890018825A KR0156096B1 KR 0156096 B1 KR0156096 B1 KR 0156096B1 KR 1019890018825 A KR1019890018825 A KR 1019890018825A KR 890018825 A KR890018825 A KR 890018825A KR 0156096 B1 KR0156096 B1 KR 0156096B1
- Authority
- KR
- South Korea
- Prior art keywords
- trench
- oxide film
- polysilicon
- silicon substrate
- nitride film
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 239000003990 capacitor Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
내용없음No content
Description
제1도는 종래의 스택 셀을 나타낸 것으로 (a)는 단면도, (b)는 회로도.Figure 1 shows a conventional stack cell, (a) is a cross-sectional view, (b) is a circuit diagram.
제2도는 본 발명의 트랜치-스택 디램 셀을 나타낸 것으로 (a)는 단면도, (b)는 회로도.2 shows a trench-stack DRAM cell of the present invention, where (a) is a sectional view and (b) is a circuit diagram.
제3도는 (a)내지 (b)는 본 발명의 공정 순서도이다.3 is a process flow chart of the present invention (a) to (b).
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 드레인 2 : 소오스1: drain 2: source
3 : 게이트 4,6,7,14 : 폴리 실리콘3: gate 4,6,7,14: polysilicon
5 : 질화 실리콘막 8 : 게이트 산화막5: silicon nitride film 8: gate oxide film
9,11 : 산화막 10 : 실리콘 기판9,11 oxide film 10 silicon substrate
12 : 질화막 13 : 트렌치12: nitride film 13: trench
15 : 접촉창15: contact window
본 발명은 트랜치-스택 디램 셀(Trench Stack D-Ram Cell)의 구조 및 그 제조방법에 관한 것으로 특히 고집적도의 디렘 셀을 용이하게 형성함은 물론 대용량의 커패시터를 형성할 수 있도록 한 것이다.The present invention relates to a structure of a trench stack D-Ram cell and a method of manufacturing the same. In particular, it is possible to easily form a high-density DRAM cell and to form a large capacity capacitor.
일반적으로 정보의 기억에 다이나믹형의 메모리 셀을 이용하는 램을 다이나믹 램(약칭하여 디램)이라고 부르며 전형적인 메모리 셀의 회로는 제1도의 (b)에 도시된 바와같이 전하 축적용의 용량 소자인 커패시터(4-6으로 구성)와 전하 입출력 제어용 모스 트랜지스터(1-3으로 구성)로 되어 있다.Generally, a RAM that uses a dynamic memory cell for storing information is called a dynamic RAM (abbreviated DRAM). A circuit of a typical memory cell includes a capacitor, which is a capacitor for charge storage, as shown in FIG. 4-6) and a MOS transistor for charge input / output control (configured in 1-3).
또한 메모리 셀의 구조에는 트렌치형 메모리 셀과 스택형 메모리 셀이 있는데 전자는 트랜지스터의 소오스단에 가로,세로의 비(aspect ratio)가 아주 큰 (예를들어 폭 1μ, 깊이 3μ) 트렌치를 형성하고 이 트렌치에 측벽도핑을 하여 트렌치의 측벽을 커패시터로 이용하였으며 (이의 회로구성은 제1도의 (b)와 동일), 이때 측벽도핑의 농도에 따라 커패시터으 용량,특성이 결정되었다. 한편, 후자는 트랜지스터의 표면에 2-3층의 폴리 실리콘을 형성하여 커패시터로 이용하였으며 이를 제1도의 (a)를 참조하여 더욱 상세히 설명하면 셀 트랜지스터의 소오스(2)단에 두 번째 폴리 실리콘(6)을 형성하고 이 폴리 실리콘(6) 표면에 질화 실리콘막(5)을 형성한 후 다시 세 번째 폴리 실리콘(4)을 덮어 이들 폴리 실리콘(4)(6)과 질화 실리콘막(5)으로 하나의 커패시터를 구성하므로 이미 드레인(1), 소오스(2), 게이트(3) (첫 번째 폴리 실리콘)로 구성된 모스 트랜지스터와 아울러 디램 메모리 셀을 형성하였다. 그러나, 전술한 바와같은 종래 기술에 있어서는 트렌치형 메모리 셀의 경우 트렌치 형성시 폭과 깊이의 비에서 폭은 작고 깊이가 깊은 트렌치를 형성하기가 어렵고 트렌치 측벽을 적정농도로 도핑 하기가 어려운 결점이 있으며 스택형 메모리 셀의 경우 적정용량(40 fF 이상)의 커패시터를 확보하기가 어려울뿐만 아니라 피일드 산화막(16)과 이에 의해 형성되는 새부리(BIRD'S BEAK) 형상(17)이 형성되어 고집적화를 기할 수 없고 표면 스탭이 평탄하지 못하게되는 결점이 있었다.In addition, the structure of the memory cell includes a trench type memory cell and a stack type memory cell. The former forms a trench having a very large aspect ratio (for example, a width of 1μ and a depth of 3μ) at the source end of the transistor. The trench was sidewall-doped and the trench sidewall was used as a capacitor (its circuit configuration is the same as in (b) of FIG. 1), where the capacity and characteristics of the capacitor were determined according to the concentration of the sidewall doping. On the other hand, the latter forms 2-3 layers of polysilicon on the surface of the transistor and used it as a capacitor, which will be described in more detail with reference to (a) of FIG. 1. 6) and a silicon nitride film 5 formed on the surface of the polysilicon 6, and then covered with a third polysilicon 4 to form the polysilicon 4 and the silicon nitride film 5, respectively. Since one capacitor is formed, a DRAM memory cell is formed together with a MOS transistor composed of a drain 1, a source 2, and a gate 3 (first polysilicon). However, in the conventional technology as described above, in the case of the trench type memory cell, it is difficult to form a trench having a small width and a deep depth at a ratio of width and depth when forming the trench, and it is difficult to dope the trench sidewalls to an appropriate concentration. In the case of a stacked memory cell, it is difficult to secure a capacitor having an appropriate capacity (40 fF or more), and the oxide film 16 and the BIRD'S BEAK shape 17 formed therefrom cannot be formed to achieve high integration. The drawback was that the surface staff became uneven.
본 발명은 이와같은 트렌치형 메모리 셀과 스택형 메모리 셀의 제반 결점을 감안하여 안출한 것으로 디램 셀의 커패시터 형성에 있어서 트렌치의 폭을 크게하여 이 트렌치의 중심부에 격리를 위한 중간벽을 형셩함과 함께 트렌치의 내부에는 스택 셀을 형성하여서된 것이바, 이와같은 본 발명의 공정순서를 첨부된 도면 제2도와 제3도에 의하여 더욱 상세히 설명하면 다음과 같다.The present invention has been made in view of the above-mentioned shortcomings of the trench type memory cell and the stacked type memory cell, and in forming the capacitor of the DRAM cell, the width of the trench is increased to form an intermediate wall for isolation in the center of the trench. In addition, the stack cell is formed inside the trench, which will be described in more detail with reference to FIGS. 2 and 3 of the accompanying drawings.
먼저 (a)와같은 실리콘 기판(10)의 표면에 (b)와같이 Sio₂의 산화막(11)을 도포하고 Si₃N₄의 질화막(12)을 디포지션 한다.First, an oxide film 11 of Sio2 is applied to the surface of the silicon substrate 10 as shown in (a), and the nitride film 12 of Si₃N₄ is deposited.
다음에 (c)와같이 P/R(Photo Resist)을 사용하여 산화막(11)과 질화막(12)의 일부를 식각한 후 (d)와같이 실리콘 기판(10) 내부로 트렌치(13)를 폭을 크게하여 형성한다. 그리고 (e)와같이 Sio₂의 산화막(14)을 도포하여 (f)와같이 식각하여 트렌치(13) 내부에만 Sio₂의 산화막(14)이 잔존하게 한다.Next, the oxide film 11 and part of the nitride film 12 are etched using P / R (Photo Resist) as shown in (c), and then the trench 13 is widened into the silicon substrate 10 as shown in (d). Form by increasing. Then, as shown in (e), the oxide film 14 of Sio₂ is coated and etched as shown in (f) so that the oxide film 14 of Sio₂ remains only in the trench 13.
이후 산화막(14)이 측벽으로 형성된 트렌치(13)의 내부와 질화막(12)의 표면에 (g)와같이 폴리 실리콘(7)을 디포지션하고 (h)와같이 산화막(14) 사이에 있는 폴리 실리콘(7)만 남도록 식각한다.The polysilicon 7 is then deposited on the inside of the trench 13 in which the oxide film 14 is formed as a sidewall and on the surface of the nitride film 12 as shown in (g), and the poly between the oxide film 14 as shown in (h). Etch so that only silicon 7 remains.
다음에 (i)와같이 트렌치(13) 측벽의 산화막(14)을 식각하여 트렌치(13) 내부에는 폴리 실리콘(7)만 남게하고 (j)와같이 실리콘 기판(10) 표면에 형성되어있는 Si₃N₄의 질화막(12)과 Sio₂의 산화막(11)을 제거한다.Next, as shown in (i), the oxide film 14 of the sidewalls of the trench 13 is etched to leave only polysilicon 7 inside the trench 13, and Si₃N₄ formed on the surface of the silicon substrate 10 as shown in (j). The nitride film 12 of and the oxide film 11 of Sio₂ are removed.
또한, 실리콘 기판(10)과 트렌치(13) 내부에 형성된 폴리 실리콘(7)의 표면에는 (k)와같이 Sio₂의 산화막(9)을 도포한 후 이 산화막(9) 위에 다시 첫 번째 폴리 실리콘(4)을 디포지션하므로 트렌치(13) 내부에 형성된 폴리 실리콘(7)이 중간벽 역할을 하게 한다.In addition, after the oxide film 9 of Sio₂ is applied to the surface of the polysilicon 7 formed in the silicon substrate 10 and the trench 13 as shown in (k), the first polysilicon ( By depositing 4), the polysilicon 7 formed inside the trench 13 serves as an intermediate wall.
그리고 (l)와같이 P/R의해 식각을 실시하여 게이트(3)를 형성하고 N+이온을 주입하여 상기 게이트(3)의 밑면양측으로 소오스(2)와 드레인(1)을 형성하므로 모스 트랜지스터가 이루어지게하며, 질화 실리콘막(5)을 형성한 후 (m)와같이 식각에 의해 콘택창(15)을 형성한 상태에서 두 번째 폴리 실리콘(6)을 디포지션 한다.As shown in (l), the gate 3 is formed by etching by P / R, and the source 2 and the drain 1 are formed on both sides of the bottom surface of the gate 3 by implanting N + ions. After the silicon nitride film 5 is formed, the second polysilicon 6 is deposited while the contact window 15 is formed by etching as shown in (m).
이후 마지막 공정으로 (n)와같이 P/R을 사용한 식각을 하므로 트렌치(13) 내부에 폴리 실리콘(7)에 의한 중간벽이 형성된 상태에서 트렌치(13) 하나에 첫 번째 폴리 실리콘(4)-질화 실리콘막(5)-두 번째 폴리실리콘(6)의 구조를 갖는 2개의 셀 커패시터가 형성된다.Since the last process is etching using P / R as in (n), the first polysilicon (4)-in the trench (13) with the intermediate wall formed by polysilicon (7) inside the trench Two cell capacitors having the structure of the silicon nitride film 5 -second polysilicon 6 are formed.
따라서, 본 발명에 의하면 트렌치(13)의 폭을 크게하므로 트렌치 형성이 용이해지고 이러한 트렌치(13) 내부에 스택형 커패시터가 형성되어 트렌치(13)의 측벽 도핑이 필요없어지며 두 번째 폴리 실리콘(6)의 거의 전표면이 커패시터가 되므로 트렌치 셀 정도의 대용량 커패시터를 형성할 수 있음은 물론 트렌치(13) 내부의 중간벽과 Vss 전위로 바이어스된 첫 번째 폴리 실리콘(4)에 의해 자동적으로 격리가 형성되어 LOCOS(Local Oxidation of Silicon) 공정에 의한 피일드 산화막이 필요없어져 이러한 LOCOS에 의해 발생되는 새부리 형상이 없어지므로 고집적화를 기할 수 있으며 특히 스택 커패시터가 트렌치(13) 내부에서 형성되어 대단히 평탄한 표면구조를 얻을 수 있는 효과를 갖는다.Therefore, according to the present invention, the width of the trench 13 is increased to facilitate trench formation, and a stacked capacitor is formed inside the trench 13, so that sidewall doping of the trench 13 is not necessary and the second polysilicon 6 is formed. Since almost the entire surface of) becomes a capacitor, it is possible to form a large-capacity capacitor as much as a trench cell, as well as isolation by the first polysilicon (4) biased to the Vss potential and the intermediate wall inside the trench (13). This eliminates the need for a film oxide film by LOCOS (Local Oxidation of Silicon) process and eliminates the beak shape generated by LOCOS, which enables high integration. In particular, a stack capacitor is formed inside the trench 13 to form a very flat surface structure. It has an effect that can be obtained.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890018825A KR0156096B1 (en) | 1989-12-18 | 1989-12-18 | Trench stack dram device & its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890018825A KR0156096B1 (en) | 1989-12-18 | 1989-12-18 | Trench stack dram device & its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910013548A KR910013548A (en) | 1991-08-08 |
| KR0156096B1 true KR0156096B1 (en) | 1998-10-15 |
Family
ID=19293093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019890018825A KR0156096B1 (en) | 1989-12-18 | 1989-12-18 | Trench stack dram device & its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0156096B1 (en) |
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1989
- 1989-12-18 KR KR1019890018825A patent/KR0156096B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR910013548A (en) | 1991-08-08 |
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