KR920005952Y1 - 반도체장치 - Google Patents

반도체장치 Download PDF

Info

Publication number
KR920005952Y1
KR920005952Y1 KR2019870007249U KR870007249U KR920005952Y1 KR 920005952 Y1 KR920005952 Y1 KR 920005952Y1 KR 2019870007249 U KR2019870007249 U KR 2019870007249U KR 870007249 U KR870007249 U KR 870007249U KR 920005952 Y1 KR920005952 Y1 KR 920005952Y1
Authority
KR
South Korea
Prior art keywords
chip
wiring board
thick
ceramic wiring
semiconductor device
Prior art date
Application number
KR2019870007249U
Other languages
English (en)
Korean (ko)
Other versions
KR880003791U (ko
Inventor
미키야 고바야시
Original Assignee
소니 가부시키가이샤
오가 노리오
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소니 가부시키가이샤, 오가 노리오 filed Critical 소니 가부시키가이샤
Publication of KR880003791U publication Critical patent/KR880003791U/ko
Application granted granted Critical
Publication of KR920005952Y1 publication Critical patent/KR920005952Y1/ko

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
KR2019870007249U 1986-07-06 1987-05-13 반도체장치 KR920005952Y1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP86-105213 1986-07-06
JP1986105213U JPH0735389Y2 (ja) 1986-07-09 1986-07-09 半導体装置

Publications (2)

Publication Number Publication Date
KR880003791U KR880003791U (ko) 1988-04-14
KR920005952Y1 true KR920005952Y1 (ko) 1992-08-27

Family

ID=14401389

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019870007249U KR920005952Y1 (ko) 1986-07-06 1987-05-13 반도체장치

Country Status (3)

Country Link
JP (1) JPH0735389Y2 (it)
KR (1) KR920005952Y1 (it)
MY (1) MY102308A (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002222914A (ja) * 2001-01-26 2002-08-09 Sony Corp 半導体装置及びその製造方法
JP4489137B1 (ja) * 2009-01-20 2010-06-23 パナソニック株式会社 回路モジュール及び電子機器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272468A (en) * 1975-12-15 1977-06-16 Matsushita Electric Ind Co Ltd Printed circuit board
JPS629728Y2 (it) * 1981-05-07 1987-03-06
JPS58150862U (ja) * 1982-04-01 1983-10-08 パイオニア株式会社 チツプ部品取付装置
JPS60114844U (ja) * 1984-01-10 1985-08-03 三菱電機株式会社 サ−マルヘツド
JPS6181140U (it) * 1984-11-01 1986-05-29

Also Published As

Publication number Publication date
JPH0735389Y2 (ja) 1995-08-09
MY102308A (en) 1992-05-28
JPS6310550U (it) 1988-01-23
KR880003791U (ko) 1988-04-14

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