KR920005333A - 반도체회로 제조장치 및 방법 - Google Patents

반도체회로 제조장치 및 방법 Download PDF

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Publication number
KR920005333A
KR920005333A KR1019910014127A KR910014127A KR920005333A KR 920005333 A KR920005333 A KR 920005333A KR 1019910014127 A KR1019910014127 A KR 1019910014127A KR 910014127 A KR910014127 A KR 910014127A KR 920005333 A KR920005333 A KR 920005333A
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KR
South Korea
Prior art keywords
semiconductor
wiring
manufacturing apparatus
semiconductor circuit
forming
Prior art date
Application number
KR1019910014127A
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English (en)
Other versions
KR960010930B1 (ko
Inventor
에이지 마스다
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR920005333A publication Critical patent/KR920005333A/ko
Application granted granted Critical
Publication of KR960010930B1 publication Critical patent/KR960010930B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

내용 없음

Description

반도체회로 제조장치 및 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 반도체회로 제조장치의 개략적인 블럭도,
제5도는 본 발명에 따른 제조공정에 의해 형성된 MOS형 반도체출력회로.

Claims (2)

  1. 반도체기판상에 반도체소자를 형성하고, 형성된 반도체소자를 배선접속시켜 반도체회로를 제조하는 반도체 회로 제조장치에 있어서, 소자의 형상이 약간다른 복수개의 반도체소자 또는 소자군을 형성하는 소자형성수단(1)과, 형성된 소자의 형상으로 측정하는 수단(3) 및, 상기 측정수단의 측정데이터를 바탕으로 반도체소자 또는 소자군을 선택적으로 배선접속하는 배선수단(5)을구비한 것을 특징으로 하는 반도체회로 제조장치.
  2. 반도체기판상에 반도체소자를 형성하고, 형성된 반도체소자를 배선접속시켜 반도체회로를 제조하는 반도체 회로 제조장치에 있어서, 소자의 형상이 약간다른 복수개의 반도체소자 또는 소자군을 형성하는 소자형성스텝(스텝 105)과 형성된 소자의 형상을 측정하는 측정스텝(스텝 107) 및, 상기 측정스텝(스텝 107)의 측정데이터를 바탕으로 반도체소자 또는 소자군을 선택적으로 배선접속하는 배선스텝(스텝 109,111)을 구비한 것을 특징으로 하는 반도체 회로 제조장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910014127A 1990-08-21 1991-08-16 반도체회로 제조장치 및 방법 KR960010930B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2218100A JP2505918B2 (ja) 1990-08-21 1990-08-21 半導体回路製造装置、半導体回路製造方法、及び該方法により製造される半導体回路
JP02-218100 1990-08-21

Publications (2)

Publication Number Publication Date
KR920005333A true KR920005333A (ko) 1992-03-28
KR960010930B1 KR960010930B1 (ko) 1996-08-13

Family

ID=16714634

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910014127A KR960010930B1 (ko) 1990-08-21 1991-08-16 반도체회로 제조장치 및 방법

Country Status (3)

Country Link
US (1) US5252508A (ko)
JP (1) JP2505918B2 (ko)
KR (1) KR960010930B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5970310A (en) * 1996-06-12 1999-10-19 Hitachi, Ltd. Method for manufacturing multilayer wiring board and wiring pattern forming apparatus
US5837557A (en) * 1997-03-14 1998-11-17 Advanced Micro Devices, Inc. Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern
US6071749A (en) * 1997-12-19 2000-06-06 Advanced Micro Devices, Inc. Process for forming a semiconductor device with controlled relative thicknesses of the active region and gate electrode
US7703067B2 (en) * 2006-03-31 2010-04-20 Synopsys, Inc. Range pattern definition of susceptibility of layout regions to fabrication issues
US7503029B2 (en) * 2006-03-31 2009-03-10 Synopsys, Inc. Identifying layout regions susceptible to fabrication issues by using range patterns
US8347239B2 (en) * 2006-06-30 2013-01-01 Synopsys, Inc. Fast lithography compliance check for place and route optimization

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58122771A (ja) * 1982-01-14 1983-07-21 Nec Corp 半導体集積回路装置
JPS594150A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd 論理集積回路の特性変化方法
JPS62272553A (ja) * 1986-05-20 1987-11-26 Fujitsu Ltd ウエ−ハ集積回路の製造方法
JPS63237610A (ja) * 1987-03-25 1988-10-04 Nec Corp 半導体集積回路
US5010029A (en) * 1989-02-22 1991-04-23 Advanced Micro Devices, Inc. Method of detecting the width of spacers and lightly doped drain regions
US4956611A (en) * 1989-04-26 1990-09-11 Ron Maltiel Electrical measurements of properties of semiconductor devices during their manufacturing process

Also Published As

Publication number Publication date
JP2505918B2 (ja) 1996-06-12
JPH04101457A (ja) 1992-04-02
KR960010930B1 (ko) 1996-08-13
US5252508A (en) 1993-10-12

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