KR900015469A - Afc 회로 - Google Patents

Afc 회로 Download PDF

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Publication number
KR900015469A
KR900015469A KR1019900002828A KR900002828A KR900015469A KR 900015469 A KR900015469 A KR 900015469A KR 1019900002828 A KR1019900002828 A KR 1019900002828A KR 900002828 A KR900002828 A KR 900002828A KR 900015469 A KR900015469 A KR 900015469A
Authority
KR
South Korea
Prior art keywords
divider
afc
circuit
controlled oscillator
signal
Prior art date
Application number
KR1019900002828A
Other languages
English (en)
Other versions
KR960016381B1 (ko
Inventor
히데오 사도미
Original Assignee
이우에 사또시
산요오 덴끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이우에 사또시, 산요오 덴끼 가부시끼가이샤 filed Critical 이우에 사또시
Publication of KR900015469A publication Critical patent/KR900015469A/ko
Application granted granted Critical
Publication of KR960016381B1 publication Critical patent/KR960016381B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof
    • H04N5/932—Regeneration of analogue synchronisation signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronizing For Television (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

내용 없음.

Description

AFC 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예를 도시한 회로도.

Claims (3)

  1. 전압제어형발진기와, 이 전압제어형발진기의 발진출력신호를 분주하는 분주기와, 이 분주기의 분주 출력신호와 입력신호와의 위상 비교를 행하고, 상기 전압제어 발진기의 발진주파수의 제어를 행하는 위상비교 회로와, 상기 전압제어형 발진기가 미스록크상태인 것을 검출하는 미스록크 검출회로를 설치하여, 이 미스록크검출회로의 검출출력에 따라서 상기 분주기의 분주동작을 정지시켜 정지후, 도래하는 상기 입력신호에 따라서 다시 분주동작을 개시시켜 AFC 루우프를 강제적으로 록크상태로 한 것을 특징으로 하는 AFC 회로.
  2. 제1항에 있어서, 상기 미스록크 검출회로의 검출출력에 따라서 상기 입력신호의 계수를 행하는 카운터와, 상기 미스록크 검출회로의 검출출력과 상기 카운터의 출력신호에 따라서 AFC 마스크 펄스를 작성하는 AFC 마스크 펄스작성회로를 설치하고 상기 AFC 마스크 펄스작성회로의 출력신호에 따라서 상기 위상비교회로의 출력신호가 상기 전압제어형 발진기에 가하여지는 것을 금지한 것을 특징으로 하는 AFC 회로.
  3. 제2항에 있어서, 상기 미스록크검출회로에 인가되는 상기 분주기의 분주 출력신호의 발생기간중에 발생하는 상기 분주기로부터의 분주기 스톱용신호와, 상기 AFC 마스크 펄스작성회로에서 얻어지는 AFC 마스크 펄스에 따라서 게이트 신호를 작성하는 게이트 신호 작성회로를 설치하고, 이 게이트신호 작성회로에서 얻어지는 게이트 신호의 발생기간, 상기 분주기의 분주 동작을 정지시키도록한 것을 특징으로 하는 AFC 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900002828A 1989-03-16 1990-03-05 자동주파수 제어회로 KR960016381B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1065528A JP2975607B2 (ja) 1989-03-16 1989-03-16 Ａｆｃ回路
JP1-65528 1989-03-16

Publications (2)

Publication Number Publication Date
KR900015469A true KR900015469A (ko) 1990-10-27
KR960016381B1 KR960016381B1 (ko) 1996-12-09

Family

ID=13289603

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900002828A KR960016381B1 (ko) 1989-03-16 1990-03-05 자동주파수 제어회로

Country Status (7)

Country Link
US (1) US5005079A (ko)
EP (1) EP0389894B1 (ko)
JP (1) JP2975607B2 (ko)
KR (1) KR960016381B1 (ko)
CA (1) CA2012280C (ko)
DE (1) DE69024687T2 (ko)
ES (1) ES2084609T3 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260812A (en) * 1991-11-26 1993-11-09 Eastman Kodak Company Clock recovery circuit
DE69216578D1 (de) * 1992-02-11 1997-02-20 Ibm Vorrichtung für Signalverarbeitung
GB2268656B (en) * 1992-07-03 1995-10-18 British Broadcasting Corp Synchronising signal separator
FR2704373B1 (fr) * 1993-04-20 1995-06-30 Bouvier Jacky Procede pour favoriser l'activation d'une boucle a verrouillage de phase et boucle correspondante.
US5418573A (en) * 1993-07-22 1995-05-23 Philips Electronics North America Corporation Apparatus and method for producing periodic synchronization references forming a synchronization signal
US5796392A (en) 1997-02-24 1998-08-18 Paradise Electronics, Inc. Method and apparatus for clock recovery in a digital display unit
JP3523069B2 (ja) * 1998-06-30 2004-04-26 株式会社東芝 遅延型位相同期回路
WO2007110219A1 (en) * 2006-03-27 2007-10-04 Ablynx N.V. Medical delivery device for therapeutic proteins based on single domain antibodies

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092672A (en) * 1976-11-15 1978-05-30 Rca Corporation Master oscillator synchronizing system
DE2856211A1 (de) * 1978-12-27 1980-07-03 Licentia Gmbh Digitale phasenregelschaltung mit einer hilfsschaltung
DE2932049A1 (de) * 1979-08-07 1981-02-12 Rohde & Schwarz Frequenz- und phasengeregelter hochfrequenzoszillator
JPH0746770B2 (ja) * 1983-09-21 1995-05-17 ソニー株式会社 ビデオ信号の周波数変換回路
US4812783A (en) * 1986-08-26 1989-03-14 Matsushita Electric Industrial Co., Ltd. Phase locked loop circuit with quickly recoverable stability
US4843469A (en) * 1987-04-13 1989-06-27 The Grass Valley Group, Inc. Rapid signal acquisition and phase averaged horizontal timing from composite sync

Also Published As

Publication number Publication date
CA2012280A1 (en) 1990-09-16
CA2012280C (en) 1999-08-31
JP2975607B2 (ja) 1999-11-10
ES2084609T3 (es) 1996-05-16
US5005079A (en) 1991-04-02
EP0389894B1 (en) 1996-01-10
EP0389894A1 (en) 1990-10-03
DE69024687D1 (de) 1996-02-22
DE69024687T2 (de) 1996-09-19
KR960016381B1 (ko) 1996-12-09
JPH02244892A (ja) 1990-09-28

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