KR900010956A - 복수 테스트모드 선택회로 - Google Patents

복수 테스트모드 선택회로

Info

Publication number
KR900010956A
KR900010956A KR1019880016648A KR880016648A KR900010956A KR 900010956 A KR900010956 A KR 900010956A KR 1019880016648 A KR1019880016648 A KR 1019880016648A KR 880016648 A KR880016648 A KR 880016648A KR 900010956 A KR900010956 A KR 900010956A
Authority
KR
South Korea
Prior art keywords
selection circuit
mode selection
test mode
multiple test
circuit
Prior art date
Application number
KR1019880016648A
Other languages
English (en)
Other versions
KR910006241B1 (ko
Inventor
조성희
도재영
김진기
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR1019880016648A priority Critical patent/KR910006241B1/ko
Priority to US07/357,989 priority patent/US5036272A/en
Priority to JP1164076A priority patent/JPH02190783A/ja
Publication of KR900010956A publication Critical patent/KR900010956A/ko
Application granted granted Critical
Publication of KR910006241B1 publication Critical patent/KR910006241B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1019880016648A 1988-12-14 1988-12-14 복수 테스트모드 선택회로 KR910006241B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019880016648A KR910006241B1 (ko) 1988-12-14 1988-12-14 복수 테스트모드 선택회로
US07/357,989 US5036272A (en) 1988-12-14 1989-05-30 Plural test mode selection circuit
JP1164076A JPH02190783A (ja) 1988-12-14 1989-06-28 複数テストモード選択回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880016648A KR910006241B1 (ko) 1988-12-14 1988-12-14 복수 테스트모드 선택회로

Publications (2)

Publication Number Publication Date
KR900010956A true KR900010956A (ko) 1990-07-11
KR910006241B1 KR910006241B1 (ko) 1991-08-17

Family

ID=19280144

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880016648A KR910006241B1 (ko) 1988-12-14 1988-12-14 복수 테스트모드 선택회로

Country Status (3)

Country Link
US (1) US5036272A (ko)
JP (1) JPH02190783A (ko)
KR (1) KR910006241B1 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07113655B2 (ja) * 1989-11-28 1995-12-06 株式会社東芝 テスト容易化回路
US5161159A (en) * 1990-08-17 1992-11-03 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with multiple clocking for test mode entry
EP0475588B1 (en) * 1990-08-17 1996-06-26 STMicroelectronics, Inc. A semiconductor memory with inhibited test mode entry during power-up
US5363383A (en) * 1991-01-11 1994-11-08 Zilog, Inc. Circuit for generating a mode control signal
US5294882A (en) * 1992-07-28 1994-03-15 Sharp Kabushiki Kaisha Integrated circuit capable of testing reliability
JP2639319B2 (ja) * 1993-09-22 1997-08-13 日本電気株式会社 半導体装置
US5754879A (en) * 1996-09-23 1998-05-19 Motorola, Inc. Integrated circuit for external bus interface having programmable mode select by selectively bonding one of the bond pads to a reset terminal via a conductive wire
KR100532391B1 (ko) * 1998-08-27 2006-01-27 삼성전자주식회사 패드수를 최소화하는 테스트 모드선택회로
KR100286101B1 (ko) 1999-04-17 2001-03-15 윤종용 반도체 장치의 신호 발생회로

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2905294A1 (de) * 1979-02-12 1980-08-21 Philips Patentverwaltung Integrierte schaltungsanordnung in mos-technik mit feldeffekttransistoren
DE2944149C2 (de) * 1979-11-02 1985-02-21 Philips Patentverwaltung Gmbh, 2000 Hamburg Integrierte Schaltungsanordnung in MOS-Technik
JPS5928986B2 (ja) * 1980-02-13 1984-07-17 日本電気株式会社 半導体集積回路
JPS5745942A (en) * 1980-09-02 1982-03-16 Toshiba Corp Semiconductor integrated circuit device
JPS57133656A (en) * 1981-02-12 1982-08-18 Nec Corp Semiconductor integrated circuit incorporated with test circuit
JPS57197480A (en) * 1981-05-29 1982-12-03 Seiko Instr & Electronics Ltd Test circuit for integrated circuit
JPS61265829A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体集積回路
JPS61292755A (ja) * 1985-06-20 1986-12-23 Fujitsu Ltd 半導体集積回路
US4752729A (en) * 1986-07-01 1988-06-21 Texas Instruments Incorporated Test circuit for VSLI integrated circuits
JPS6337270A (ja) * 1986-07-31 1988-02-17 Fujitsu Ltd 半導体装置
JPH06105285B2 (ja) * 1986-08-22 1994-12-21 三菱電機株式会社 半導体集積回路装置
JP2628154B2 (ja) * 1986-12-17 1997-07-09 富士通株式会社 半導体集積回路
US4866714A (en) * 1987-10-15 1989-09-12 Westinghouse Electric Corp. Personal computer-based dynamic burn-in system

Also Published As

Publication number Publication date
JPH02190783A (ja) 1990-07-26
US5036272A (en) 1991-07-30
KR910006241B1 (ko) 1991-08-17

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Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070801

Year of fee payment: 17

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