KR900006785B1 - 반도체장치의 시간지연 회로 - Google Patents

반도체장치의 시간지연 회로 Download PDF

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Publication number
KR900006785B1
KR900006785B1 KR1019870000849A KR870000849A KR900006785B1 KR 900006785 B1 KR900006785 B1 KR 900006785B1 KR 1019870000849 A KR1019870000849 A KR 1019870000849A KR 870000849 A KR870000849 A KR 870000849A KR 900006785 B1 KR900006785 B1 KR 900006785B1
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KR
South Korea
Prior art keywords
circuit
delay
level
circuits
gate
Prior art date
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Expired
Application number
KR1019870000849A
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English (en)
Korean (ko)
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KR870008439A (ko
Inventor
아쓰시 다께우찌
Original Assignee
후지쓰 가부시끼가이샤
야마모도 다꾸마
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 후지쓰 가부시끼가이샤, 야마모도 다꾸마 filed Critical 후지쓰 가부시끼가이샤
Publication of KR870008439A publication Critical patent/KR870008439A/ko
Application granted granted Critical
Publication of KR900006785B1 publication Critical patent/KR900006785B1/ko
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/061—Sense amplifier enabled by a address transition detection related control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00247—Layout of the delay element using circuits having two logic levels using counters

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Read Only Memory (AREA)
KR1019870000849A 1986-02-04 1987-02-03 반도체장치의 시간지연 회로 Expired KR900006785B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP22528 1981-02-18
JP61022528A JPS62180607A (ja) 1986-02-04 1986-02-04 半導体集積回路
JP61022528 1986-02-04

Publications (2)

Publication Number Publication Date
KR870008439A KR870008439A (ko) 1987-09-26
KR900006785B1 true KR900006785B1 (ko) 1990-09-21

Family

ID=12085292

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870000849A Expired KR900006785B1 (ko) 1986-02-04 1987-02-03 반도체장치의 시간지연 회로

Country Status (5)

Country Link
US (1) US4800304A (enExample)
EP (1) EP0233550B1 (enExample)
JP (1) JPS62180607A (enExample)
KR (1) KR900006785B1 (enExample)
DE (1) DE3786683T2 (enExample)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
JP2525455B2 (ja) * 1988-05-30 1996-08-21 富士通株式会社 半導体メモリ装置
US4953130A (en) * 1988-06-27 1990-08-28 Texas Instruments, Incorporated Memory circuit with extended valid data output time
US5193076A (en) * 1988-12-22 1993-03-09 Texas Instruments Incorporated Control of sense amplifier latch timing
US4970507A (en) * 1989-03-17 1990-11-13 Gte Laboratories Incorporated Broadband switching matrix for delay equalization and elimination of inversion
US5003310A (en) * 1989-09-29 1991-03-26 Westinghouse Electric Corp. Analog data acquisition circuit with digital logic control
JPH0793558B2 (ja) * 1989-12-15 1995-10-09 安藤電気株式会社 タイミング信号遅延回路
KR930006622B1 (ko) * 1990-09-04 1993-07-21 삼성전자 주식회사 반도체 메모리장치
US5124951A (en) * 1990-09-26 1992-06-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequenced latched row line repeaters
JPH04309107A (ja) * 1991-04-08 1992-10-30 Nec Ic Microcomput Syst Ltd 半導体集積回路
US5184032A (en) * 1991-04-25 1993-02-02 Texas Instruments Incorporated Glitch reduction in integrated circuits, systems and methods
IT1253678B (it) * 1991-07-31 1995-08-22 St Microelectronics Srl Architettura antirumore per memoria
US5374894A (en) * 1992-08-19 1994-12-20 Hyundai Electronics America Transition detection circuit
US5301165A (en) * 1992-10-28 1994-04-05 International Business Machines Corporation Chip select speedup circuit for a memory
FR2699023B1 (fr) * 1992-12-09 1995-02-24 Texas Instruments France Circuit à retard commandé.
US5424985A (en) * 1993-06-30 1995-06-13 Sgs-Thomson Microelectronics, Inc. Compensating delay element for clock generation in a memory device
GB2315347B (en) * 1993-08-23 1998-04-01 Advanced Risc Mach Ltd Testing integrated circuits
US5666079A (en) * 1994-05-06 1997-09-09 Plx Technology, Inc. Binary relative delay line
GB2300773B (en) * 1994-06-06 1998-07-22 Seiko Epson Corp Display data processing device and method of processing display data
US5784072A (en) * 1994-06-06 1998-07-21 Seiko Epson Corporation Oscillation device, display data processing device, matrix-type display device, oscillation signal generation method, and display data processing method
JP3275554B2 (ja) * 1994-08-09 2002-04-15 ヤマハ株式会社 半導体記憶装置
US5757718A (en) * 1996-02-28 1998-05-26 Nec Corporation Semiconductor memory device having address transition detection circuit for controlling sense and latch operations
DE69630108D1 (de) * 1996-04-29 2003-10-30 St Microelectronics Srl Zur Erreichung von Minimal-Funktionalitätsbedingungen von Speicherzellen und Leseschaltungen, insbesondere für nichtflüchtige Speicher, synchronisierte Speicherleseaktivierungsschaltung
US5818277A (en) * 1997-01-28 1998-10-06 Advantest Corporation Temperature balanced circuit
US6037817A (en) * 1997-08-07 2000-03-14 Lockheed Martin Energy Research Corporation Apparatus and method for digital delays without dead time
DE69728148D1 (de) * 1997-11-05 2004-04-22 St Microelectronics Srl Verfahren und Schaltung zur Erzeugung eines Adressenübergangssignals ATD zur Regulierung des Zugriffs auf einen nichtflüchtigen Speicher
JP4231230B2 (ja) * 2002-02-05 2009-02-25 セイコーエプソン株式会社 パルス波形成形装置、レーザープリンタ、パルス波形成形方法およびレーザープリンタのシリアルビデオデータ生成方法
US6882206B2 (en) * 2003-04-30 2005-04-19 Eastman Kodak Company Enabling method to prevent glitches in waveform of arbitrary phase
US7167400B2 (en) * 2004-06-22 2007-01-23 Micron Technology, Inc. Apparatus and method for improving dynamic refresh in a memory device
JP4478674B2 (ja) 2006-12-26 2010-06-09 カワサキプラントシステムズ株式会社 セメント焼成プラント廃熱発電システム
US9613714B1 (en) 2016-01-19 2017-04-04 Ememory Technology Inc. One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method
CN112438020B (zh) 2018-08-01 2022-05-17 美光科技公司 半导体装置、延迟电路和相关方法
CN112557883B (zh) * 2021-02-26 2021-05-25 坤元微电子(南京)有限公司 一种脉冲信号参数测试系统

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675049A (en) * 1970-04-24 1972-07-04 Western Electric Co Variable digital delay using multiple parallel channels and a signal-driven bit distributor
JPS53114651A (en) * 1977-03-17 1978-10-06 Fujitsu Ltd Electronic circuit
JPS54150064A (en) * 1978-05-18 1979-11-24 Toshiba Corp Pulse generation circuit
US4340943A (en) * 1979-05-31 1982-07-20 Tokyo Shibaura Denki Kabushiki Kaisha Memory device utilizing MOS FETs
JPS6032911B2 (ja) * 1979-07-26 1985-07-31 株式会社東芝 半導体記憶装置
US4425633A (en) * 1980-10-06 1984-01-10 Mostek Corporation Variable delay circuit for emulating word line delay
US4556961A (en) * 1981-05-26 1985-12-03 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory with delay means to reduce peak currents
JPS58169383A (ja) * 1982-03-30 1983-10-05 Fujitsu Ltd 半導体記憶装置
JPS59221891A (ja) * 1983-05-31 1984-12-13 Toshiba Corp スタテイツク型半導体記憶装置
JPS60253091A (ja) * 1984-05-30 1985-12-13 Fujitsu Ltd 半導体記憶装置
US4670665A (en) * 1985-07-31 1987-06-02 Rca Corporation Digital pulse width detector

Also Published As

Publication number Publication date
KR870008439A (ko) 1987-09-26
EP0233550B1 (en) 1993-07-28
EP0233550A2 (en) 1987-08-26
DE3786683T2 (de) 1994-02-24
US4800304A (en) 1989-01-24
JPS62180607A (ja) 1987-08-07
DE3786683D1 (de) 1993-09-02
EP0233550A3 (en) 1990-05-23
JPH0381327B2 (enExample) 1991-12-27

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