KR880013062A - 코프로세서 및 그 제어방법 - Google Patents

코프로세서 및 그 제어방법 Download PDF

Info

Publication number
KR880013062A
KR880013062A KR1019880004369A KR880004369A KR880013062A KR 880013062 A KR880013062 A KR 880013062A KR 1019880004369 A KR1019880004369 A KR 1019880004369A KR 880004369 A KR880004369 A KR 880004369A KR 880013062 A KR880013062 A KR 880013062A
Authority
KR
South Korea
Prior art keywords
coprocessor
microprocessor
protocol
control method
floating point
Prior art date
Application number
KR1019880004369A
Other languages
English (en)
Other versions
KR950012117B1 (ko
Inventor
시게기 모리나가
노리오 나가가와
미쓰루 와다베
마모루 오오바
히로유기 기다
히사시 가지와라
다게시 아사이
준이찌 다데사기
Original Assignee
미쓰다 가쓰시게
가부시끼가이샤 히다찌 세이사꾸쇼
야마사끼 세이지
히다찌 엔지니어링 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미쓰다 가쓰시게, 가부시끼가이샤 히다찌 세이사꾸쇼, 야마사끼 세이지, 히다찌 엔지니어링 가부시끼가이샤 filed Critical 미쓰다 가쓰시게
Publication of KR880013062A publication Critical patent/KR880013062A/ko
Application granted granted Critical
Publication of KR950012117B1 publication Critical patent/KR950012117B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음

Description

코프로세서 및 그 제어방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예가 되는 코프로세서를 포함하는 마이크로 컴퓨터 시스템도, 제2도는 본 발명이 되는 부동 소수점 연산 프로세서의 블록의 일실시예도, 제3도는 포맷변환 기능의 설명도, 제4도는 본 발명이 되는 코맨드 파이프라인 제어의 타이밍도, 제5도는 버스 컨트롤 유니트의 내부블록의 일실시예도.

Claims (4)

  1. 마이크로 프로세서와 접속되는 코프로세서에 있어서 마이크로 프로세서에 의하여 제어되어 코프로세서에 보내지는 코맨드 및 오퍼랜드를 선입 선출(FIFO(First In First Out))형 메모리에 넣는 것을 특징으로 하는 코프로세서의 제어방법.
  2. 제1항에 있어서, 코프로세서의 처리기능을 분할하여 파이프라인 제어를 행하는 것을 특징으로 하는 코프로세서의 제어방법.
  3. 마이크로 프로세서와 접속되는 코프로세서에 있어서 코맨드 전송 프로토콜과 오퍼랜드 전송 프로토콜에 프로토콜을 분할한 것을 특징으로 하는 코프로세서의 제어방법.
  4. 부동 소수점 연산 프로세서에 있어서 프로토콜 제어부, 포맷 변환부와 부동소수점 연산부를 파이프라인 제어하는 것을 특징으로 하는 코프로세서.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880004369A 1987-04-17 1988-04-16 코프로세서 및 그 제어방법 KR950012117B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62093098A JPS63259727A (ja) 1987-04-17 1987-04-17 コプロセツサのインタ−フエイス方式
JP62-93098 1987-04-17

Publications (2)

Publication Number Publication Date
KR880013062A true KR880013062A (ko) 1988-11-29
KR950012117B1 KR950012117B1 (ko) 1995-10-14

Family

ID=14073044

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880004369A KR950012117B1 (ko) 1987-04-17 1988-04-16 코프로세서 및 그 제어방법

Country Status (5)

Country Link
US (1) US5504912A (ko)
EP (1) EP0287115B1 (ko)
JP (1) JPS63259727A (ko)
KR (1) KR950012117B1 (ko)
DE (1) DE3852056T2 (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2656710A1 (fr) * 1989-12-29 1991-07-05 Radiotechnique Compelec Microcontroleur pour l'execution rapide d'un grand nombre d'operations decomposable en sequence d'operations de meme nature.
JPH0785219B2 (ja) * 1990-11-15 1995-09-13 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理システム及びデータ制御方法
RU95107478A (ru) * 1995-05-18 1997-02-10 А.И. Грушин Способ устранения старших незначащих цифр при вычислениях с плавающей запятой и устройство для его осуществления
US5808926A (en) * 1995-06-01 1998-09-15 Sun Microsystems, Inc. Floating point addition methods and apparatus
US5878266A (en) * 1995-09-26 1999-03-02 Advanced Micro Devices, Inc. Reservation station for a floating point processing unit
US5761105A (en) * 1995-09-26 1998-06-02 Advanced Micro Devices, Inc. Reservation station including addressable constant store for a floating point processing unit
US6154760A (en) * 1995-11-27 2000-11-28 Intel Corporation Instruction to normalize redundantly encoded floating point numbers
US5983340A (en) * 1995-12-07 1999-11-09 Conexant Systems, Inc. Microprocessor system with flexible instruction controlled by prior instruction
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
AUPO648397A0 (en) * 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6505290B1 (en) * 1997-09-05 2003-01-07 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
US5923893A (en) * 1997-09-05 1999-07-13 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
GB2387932B (en) * 2002-04-26 2005-06-22 Motorola Inc Apparatus and method for scheduling tasks in a communications network
US7441106B2 (en) 2004-07-02 2008-10-21 Seagate Technology Llc Distributed processing in a multiple processing unit environment
US7330964B2 (en) * 2005-11-14 2008-02-12 Texas Instruments Incorporated Microprocessor with independent SIMD loop buffer
US7788470B1 (en) * 2008-03-27 2010-08-31 Xilinx, Inc. Shadow pipeline in an auxiliary processor unit controller
CN101980149B (zh) * 2010-10-15 2013-09-18 无锡中星微电子有限公司 主处理器与协处理器通信系统及通信方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2291545A1 (fr) * 1974-02-20 1976-06-11 Honeywell Bull Soc Ind Dispositif de commande de transferts de donnees entre des unites centrales de traitement
US4270167A (en) * 1978-06-30 1981-05-26 Intel Corporation Apparatus and method for cooperative and concurrent coprocessing of digital information
US4298936A (en) * 1979-11-15 1981-11-03 Analogic Corporation Array Processor
US4547849A (en) * 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
US4509116A (en) * 1982-04-21 1985-04-02 Digital Equipment Corporation Special instruction processing unit for data processing system
US4821231A (en) * 1983-04-18 1989-04-11 Motorola, Inc. Method and apparatus for selectively evaluating an effective address for a coprocessor
US4589067A (en) * 1983-05-27 1986-05-13 Analogic Corporation Full floating point vector processor with dynamically configurable multifunction pipelined ALU
JPH081604B2 (ja) * 1983-07-25 1996-01-10 株式会社日立製作所 マイクロプロセッサ
US4947316A (en) * 1983-12-29 1990-08-07 International Business Machines Corporation Internal bus architecture employing a simplified rapidly executable instruction set
US4766536A (en) * 1984-04-19 1988-08-23 Rational Computer bus apparatus with distributed arbitration
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
JPH065528B2 (ja) * 1985-09-20 1994-01-19 日本電気株式会社 情報処理システム
US4745544A (en) * 1985-12-12 1988-05-17 Texas Instruments Incorporated Master/slave sequencing processor with forced I/O
IT1184015B (it) * 1985-12-13 1987-10-22 Elsag Sistema multiprocessore a piu livelli gerarchici
US4777613A (en) * 1986-04-01 1988-10-11 Motorola Inc. Floating point numeric data processor
US4774659A (en) * 1986-04-16 1988-09-27 Astronautics Corporation Of America Computer system employing virtual memory
US4811208A (en) * 1986-05-16 1989-03-07 Intel Corporation Stack frame cache on a microprocessor chip
US4760525A (en) * 1986-06-10 1988-07-26 The United States Of America As Represented By The Secretary Of The Air Force Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction
US4879676A (en) * 1988-02-29 1989-11-07 Mips Computer Systems, Inc. Method and apparatus for precise floating point exceptions

Also Published As

Publication number Publication date
KR950012117B1 (ko) 1995-10-14
DE3852056T2 (de) 1995-03-16
EP0287115A3 (en) 1992-03-11
EP0287115B1 (en) 1994-11-09
US5504912A (en) 1996-04-02
DE3852056D1 (de) 1994-12-15
JPS63259727A (ja) 1988-10-26
EP0287115A2 (en) 1988-10-19

Similar Documents

Publication Publication Date Title
KR880013062A (ko) 코프로세서 및 그 제어방법
EP0263288A3 (en) Extended floating point operations supporting emulation of source instruction execution
JPS55112651A (en) Virtual computer system
KR880008150A (ko) 느슨하게 결합된 파이프라인 프로세서
KR950704730A (ko) 고속 프로그램가능 로직 컨트롤러(plc)(high speed programmable logic controller)
JPS57176456A (en) Data processing system
KR900006853A (ko) 마이크로 프로세서
KR870007461A (ko) 데이타 처리 시스템 동작방법
JPS57182257A (en) Data interchange system of data processing system
KR900005303A (ko) 데이타 처리 장치
JPS57136206A (en) Sequence controller
JPS6474617A (en) Floating-point arithmetic system
JPS57113144A (en) Stored program computer
JPS578849A (en) Adjusting system for instruction execution speed
KR900015007A (ko) 마이크로 프로세서 시스템 및 마이크로 프로세서 시스템에서의 전송제어 방법
JPS6417129A (en) Control system for input/output interruption of virtual computer
JPS5654509A (en) Sequence controller
JPS5663657A (en) Memory switching system
KR890016798A (ko) 디스크 드라이버와 호스트 컴퓨터 간의 데이타 전송시스템
JPS5563423A (en) Data transfer system
EP0278263A3 (en) Multiple bus dma controller
JPS61166631A (ja) マイクロプログラム制御処理方法
JPS54114945A (en) Information processing system
JPS6437649A (en) Input/output control system
JPS55121542A (en) Arithmetic control system

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20021002

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee