DE3852056T2 - Koprozessor und Verfahren zu dessen Steuerung. - Google Patents

Koprozessor und Verfahren zu dessen Steuerung.

Info

Publication number
DE3852056T2
DE3852056T2 DE3852056T DE3852056T DE3852056T2 DE 3852056 T2 DE3852056 T2 DE 3852056T2 DE 3852056 T DE3852056 T DE 3852056T DE 3852056 T DE3852056 T DE 3852056T DE 3852056 T2 DE3852056 T2 DE 3852056T2
Authority
DE
Germany
Prior art keywords
coprocessor
controlling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3852056T
Other languages
English (en)
Other versions
DE3852056D1 (de
Inventor
Shigeki Morinaga
Norio Nakagawa
Mitsuru Watabe
Mamoru Ohba
Hiroyuki Kida
Hisashi Kajiwara
Takeshi Asai
Junichi Tatezaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Application granted granted Critical
Publication of DE3852056D1 publication Critical patent/DE3852056D1/de
Publication of DE3852056T2 publication Critical patent/DE3852056T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
DE3852056T 1987-04-17 1988-04-15 Koprozessor und Verfahren zu dessen Steuerung. Expired - Fee Related DE3852056T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62093098A JPS63259727A (ja) 1987-04-17 1987-04-17 コプロセツサのインタ−フエイス方式

Publications (2)

Publication Number Publication Date
DE3852056D1 DE3852056D1 (de) 1994-12-15
DE3852056T2 true DE3852056T2 (de) 1995-03-16

Family

ID=14073044

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3852056T Expired - Fee Related DE3852056T2 (de) 1987-04-17 1988-04-15 Koprozessor und Verfahren zu dessen Steuerung.

Country Status (5)

Country Link
US (1) US5504912A (de)
EP (1) EP0287115B1 (de)
JP (1) JPS63259727A (de)
KR (1) KR950012117B1 (de)
DE (1) DE3852056T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2656710A1 (fr) * 1989-12-29 1991-07-05 Radiotechnique Compelec Microcontroleur pour l'execution rapide d'un grand nombre d'operations decomposable en sequence d'operations de meme nature.
JPH0785219B2 (ja) * 1990-11-15 1995-09-13 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理システム及びデータ制御方法
RU95107478A (ru) * 1995-05-18 1997-02-10 А.И. Грушин Способ устранения старших незначащих цифр при вычислениях с плавающей запятой и устройство для его осуществления
US5808926A (en) * 1995-06-01 1998-09-15 Sun Microsystems, Inc. Floating point addition methods and apparatus
US5761105A (en) * 1995-09-26 1998-06-02 Advanced Micro Devices, Inc. Reservation station including addressable constant store for a floating point processing unit
US5878266A (en) * 1995-09-26 1999-03-02 Advanced Micro Devices, Inc. Reservation station for a floating point processing unit
US6154760A (en) * 1995-11-27 2000-11-28 Intel Corporation Instruction to normalize redundantly encoded floating point numbers
US5983340A (en) * 1995-12-07 1999-11-09 Conexant Systems, Inc. Microprocessor system with flexible instruction controlled by prior instruction
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
AUPO648397A0 (en) * 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6505290B1 (en) * 1997-09-05 2003-01-07 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
US5923893A (en) * 1997-09-05 1999-07-13 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
GB2387932B (en) * 2002-04-26 2005-06-22 Motorola Inc Apparatus and method for scheduling tasks in a communications network
US7441106B2 (en) 2004-07-02 2008-10-21 Seagate Technology Llc Distributed processing in a multiple processing unit environment
US7330964B2 (en) * 2005-11-14 2008-02-12 Texas Instruments Incorporated Microprocessor with independent SIMD loop buffer
US7788470B1 (en) * 2008-03-27 2010-08-31 Xilinx, Inc. Shadow pipeline in an auxiliary processor unit controller
CN101980149B (zh) * 2010-10-15 2013-09-18 无锡中星微电子有限公司 主处理器与协处理器通信系统及通信方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2291545A1 (fr) * 1974-02-20 1976-06-11 Honeywell Bull Soc Ind Dispositif de commande de transferts de donnees entre des unites centrales de traitement
US4270167A (en) * 1978-06-30 1981-05-26 Intel Corporation Apparatus and method for cooperative and concurrent coprocessing of digital information
US4298936A (en) * 1979-11-15 1981-11-03 Analogic Corporation Array Processor
US4547849A (en) * 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
US4509116A (en) * 1982-04-21 1985-04-02 Digital Equipment Corporation Special instruction processing unit for data processing system
US4821231A (en) * 1983-04-18 1989-04-11 Motorola, Inc. Method and apparatus for selectively evaluating an effective address for a coprocessor
US4589067A (en) * 1983-05-27 1986-05-13 Analogic Corporation Full floating point vector processor with dynamically configurable multifunction pipelined ALU
JPH081604B2 (ja) * 1983-07-25 1996-01-10 株式会社日立製作所 マイクロプロセッサ
US4947316A (en) * 1983-12-29 1990-08-07 International Business Machines Corporation Internal bus architecture employing a simplified rapidly executable instruction set
US4766536A (en) * 1984-04-19 1988-08-23 Rational Computer bus apparatus with distributed arbitration
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
JPH065528B2 (ja) * 1985-09-20 1994-01-19 日本電気株式会社 情報処理システム
US4745544A (en) * 1985-12-12 1988-05-17 Texas Instruments Incorporated Master/slave sequencing processor with forced I/O
IT1184015B (it) * 1985-12-13 1987-10-22 Elsag Sistema multiprocessore a piu livelli gerarchici
US4777613A (en) * 1986-04-01 1988-10-11 Motorola Inc. Floating point numeric data processor
US4774659A (en) * 1986-04-16 1988-09-27 Astronautics Corporation Of America Computer system employing virtual memory
US4811208A (en) * 1986-05-16 1989-03-07 Intel Corporation Stack frame cache on a microprocessor chip
US4760525A (en) * 1986-06-10 1988-07-26 The United States Of America As Represented By The Secretary Of The Air Force Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction
US4879676A (en) * 1988-02-29 1989-11-07 Mips Computer Systems, Inc. Method and apparatus for precise floating point exceptions

Also Published As

Publication number Publication date
EP0287115B1 (de) 1994-11-09
US5504912A (en) 1996-04-02
EP0287115A2 (de) 1988-10-19
DE3852056D1 (de) 1994-12-15
JPS63259727A (ja) 1988-10-26
KR950012117B1 (ko) 1995-10-14
KR880013062A (ko) 1988-11-29
EP0287115A3 (de) 1992-03-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee