KR880008521A - 디지탈 회로장치 - Google Patents
디지탈 회로장치 Download PDFInfo
- Publication number
- KR880008521A KR880008521A KR1019870014064A KR870014064A KR880008521A KR 880008521 A KR880008521 A KR 880008521A KR 1019870014064 A KR1019870014064 A KR 1019870014064A KR 870014064 A KR870014064 A KR 870014064A KR 880008521 A KR880008521 A KR 880008521A
- Authority
- KR
- South Korea
- Prior art keywords
- coupled
- input
- output
- quantizer
- adder stage
- Prior art date
Links
- 238000013139 quantization Methods 0.000 claims 2
- 238000001914 filtration Methods 0.000 claims 1
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
- H03M7/3042—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
- H03M7/3026—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Communication Control (AREA)
- Noise Elimination (AREA)
Abstract
Description
Claims (4)
- 이산-진폭샘플의 시퀀스로 나타나는 디지털 입력 신호를 특정 샘플링 비율로 오버샘플링하기 위한 보간 필터(1)와, 출력은 양자화기(7)에 결합되고 제1입력은 보간 필터(1)에 결합되어 있으며 제2입력은 양자 화기의 양자화 에러 신호를 여파하기 위한 제2차 필터장치(4)에 결합되는 가산기단(3)을 포함하는 잡음 정형기(2)와, 양자화기(7)의 출력에 결합된 디지털-아날로그 변환기(8)를 구비하는 디지털 회로장치에 있어서, 라미터(10)가 가산기단(3)의 제2입력전에 배치되는 것을 특징으로 하는 디지털 회로장치.
- 제1항에 있어서 상기 디지털 회로장치가 양자화 에러 신호를 발생하기 위한 감산기(6)를 구비하되, 상기 감산기(6)의 제1입력은 가산기단(3)의 출력에 결합되고, 제2입력은 양자화기(7)의 출력에 결합되며, 그 출력은 가산기단(3)의 제2입력에 결합된 출력을 갖는 필터장치(4)의 입력에 결합되는 출력을 갖는 리미터(10)의 입력에 결합되는 것을 특징으로 하는 디지털 회로장치.
- 제2항에 있어서, 상기 필터장치(4)는 입력이 리미터(10)에 결합되고 출력이 증폭기(13)와 제2레지스터(14)에 결합되는 제1레지스터(12)를 구비하고, 또한 상기 필터장치(4)는 제1입력이 제2레지스터(14)에 결합되고 제2입력이 증폭기(13)에 결합되며 출력이 필터장치(4)의 출력에 결합되는 다른 감산기(16)를 구비하는 것을 특징으로 하는 디지털 회로장치.
- 제1항, 2항 또는 제3항에 있어서, 상기 양자화기(7)는 만일 상기 가산기단(3)의 출력 신호가 정이면 제1상태를 취하고 상기 가산기단(3)의 출력이 부이면 제2상태를 취하는 1비트 신호를 발생하기 적합한 것을 특징으로 하는 디지털 회로장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NLP3642168.5 | 1986-12-10 | ||
DE19863642168 DE3642168A1 (de) | 1986-12-10 | 1986-12-10 | Digitale schaltungsanordnung zur verringerung des quantisierungsrauschens |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880008521A true KR880008521A (ko) | 1988-08-31 |
KR960006644B1 KR960006644B1 (en) | 1996-05-22 |
Family
ID=6315880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR87014064A KR960006644B1 (en) | 1986-12-10 | 1987-12-10 | Digital circuit device |
Country Status (7)
Country | Link |
---|---|
US (1) | US4859883A (ko) |
EP (1) | EP0271166B1 (ko) |
JP (1) | JP2613900B2 (ko) |
KR (1) | KR960006644B1 (ko) |
AT (1) | ATE103435T1 (ko) |
BR (1) | BR8706707A (ko) |
DE (2) | DE3642168A1 (ko) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3744132A1 (de) * | 1987-12-24 | 1989-07-06 | Asea Brown Boveri | Verfahren und schaltung zur unterdrueckung des quantisierungsrauschens |
GB8829063D0 (en) * | 1988-12-13 | 1989-01-25 | British Telecomm | Predictive coding and decoding |
NL8901142A (nl) * | 1989-05-08 | 1990-12-03 | Philips Nv | Inrichting voor het uitlezen van een op een registratiedrager aangebracht informatiepatroon, alsmede een signaalverwerkingsschakeling voor toepassing in een dergelijke inrichting. |
US5057785A (en) * | 1990-01-23 | 1991-10-15 | International Business Machines Corporation | Method and circuitry to suppress additive disturbances in data channels |
GB9103777D0 (en) * | 1991-02-22 | 1991-04-10 | B & W Loudspeakers | Analogue and digital convertors |
AU682032B2 (en) * | 1993-06-29 | 1997-09-18 | Sony Corporation | Audio signal transmitting apparatus and the method thereof |
US5602874A (en) * | 1994-12-29 | 1997-02-11 | Motorola, Inc. | Method and apparatus for reducing quantization noise |
DE19509117C2 (de) * | 1995-03-17 | 1997-02-27 | Bosch Gmbh Robert | Verfahren zur Überwachung der Übertragungsqualität digitalisierter Signale |
US5708389A (en) * | 1996-03-15 | 1998-01-13 | Lucent Technologies Inc. | Integrated circuit employing quantized feedback |
DE19912447C2 (de) * | 1999-03-19 | 2002-02-28 | Micronas Gmbh | Anordnung zum Erzeugen eines in seiner Bitbreite begrenzten digitalen Signals und Digital/Analog-Umsetzer mit vergrößertem Wertebereich |
EP1505736A4 (en) * | 2002-05-09 | 2005-09-14 | Neuro Solution Corp | DIGITAL / ANALOG CONVERTER |
US7345606B2 (en) * | 2004-01-28 | 2008-03-18 | Nxp B.V. | DA-converter system and a method for converting a multi-bit digital signal to an analog signal |
US6956513B1 (en) * | 2004-10-22 | 2005-10-18 | Broadcom Corporation | Error feedback structure for delta-sigma modulators with improved stability |
EP3447922A4 (en) * | 2017-06-15 | 2019-02-27 | Shenzhen Goodix Technology Co., Ltd. | NOISE SHAPING CIRCUIT AND INTEGRATED TRIGONOMETRIC DIGITAL-TO-ANALOG CONVERTER |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4109110A (en) * | 1975-02-20 | 1978-08-22 | International Standard Electric Corporation | Digital-to-analog converter |
NL173339C (nl) * | 1978-11-30 | 1984-01-02 | Philips Nv | Digitaal-analoog omzetter. |
DE3021012C2 (de) * | 1980-06-03 | 1985-08-22 | ANT Nachrichtentechnik GmbH, 7150 Backnang | Verallgemeinertes interpolativers Verfahren zur Digital-Analog-Umsetzung von PCM Signalen |
GB8427325D0 (en) * | 1984-10-29 | 1984-12-05 | Plessey Co Plc | Digital to analogue conversion |
NL8600862A (nl) * | 1986-04-04 | 1987-11-02 | Philips Nv | Kodeerinrichting. |
-
1986
- 1986-12-10 DE DE19863642168 patent/DE3642168A1/de not_active Withdrawn
-
1987
- 1987-12-08 DE DE87202447T patent/DE3789426D1/de not_active Expired - Fee Related
- 1987-12-08 AT AT87202447T patent/ATE103435T1/de not_active IP Right Cessation
- 1987-12-08 US US07/130,367 patent/US4859883A/en not_active Expired - Fee Related
- 1987-12-08 EP EP87202447A patent/EP0271166B1/de not_active Expired - Lifetime
- 1987-12-10 JP JP62311120A patent/JP2613900B2/ja not_active Expired - Lifetime
- 1987-12-10 BR BR8706707A patent/BR8706707A/pt unknown
- 1987-12-10 KR KR87014064A patent/KR960006644B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0271166A3 (de) | 1991-06-26 |
JPS63161713A (ja) | 1988-07-05 |
EP0271166B1 (de) | 1994-03-23 |
ATE103435T1 (de) | 1994-04-15 |
KR960006644B1 (en) | 1996-05-22 |
JP2613900B2 (ja) | 1997-05-28 |
US4859883A (en) | 1989-08-22 |
DE3789426D1 (de) | 1994-04-28 |
EP0271166A2 (de) | 1988-06-15 |
DE3642168A1 (de) | 1988-06-16 |
BR8706707A (pt) | 1988-07-19 |
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Legal Events
Date | Code | Title | Description |
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PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19871210 |
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PG1501 | Laying open of application | ||
A201 | Request for examination | ||
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19921203 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19871210 Comment text: Patent Application |
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G160 | Decision to publish patent application | ||
PG1605 | Publication of application before grant of patent |
Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19960425 |
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E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19960731 |
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PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19960912 Patent event code: PR07011E01D |
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PR1002 | Payment of registration fee |
Payment date: 19960912 End annual number: 3 Start annual number: 1 |
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LAPS | Lapse due to unpaid annual fee | ||
PC1903 | Unpaid annual fee |