KR970702630A - 양자화 잡음을 줄이는 방법 및 장치(Method and Apparatus for Reducing Quantization Noise) - Google Patents

양자화 잡음을 줄이는 방법 및 장치(Method and Apparatus for Reducing Quantization Noise)

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KR970702630A
KR970702630A KR1019960705734A KR19960705734A KR970702630A KR 970702630 A KR970702630 A KR 970702630A KR 1019960705734 A KR1019960705734 A KR 1019960705734A KR 19960705734 A KR19960705734 A KR 19960705734A KR 970702630 A KR970702630 A KR 970702630A
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유다 예후다 루즈
제임스 프랭크 롱
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안쏘니 제이, 살리, 주니어
모토롤라, 인크.
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Publication of KR970702630A publication Critical patent/KR970702630A/ko

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Abstract

양자화 잡음 절감 회로(200)에 있어서, 양자화 잡음을 줄이기 위해 양자화 회로의 입력 신호(X)에 피드백 신호(W)가 부가된다. 피드백 신호는 N비트 신호(X′)의 샘플과, M〈N인, M비트 양자화된 신호의 동시간 샘플간의 필터링된 차이로서 발생된다. 피드백 신호는 양자화에 앞서 입력 신호(X)에서 감해짐으로써, 대역외 잡음을 입력 신호에 도입하여 양자화된 신호(Y) 중의 대역내 잡음을 절감한다.

Description

양자화 잡음을 줄이는 방법 및 장치(Method and Apparatus for Reducing Quantization Noise)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 종래의 16비트 대 12비트 양자화 회로의 블록도 표현,
제2도는 본 발명의 바람직한 실시예에 따른 양자화 회로의 블록도 표현,
제3도는 제2도에 도시된 양자화 회로에 사용하기 위한 필터의 전달 함수 표현.

Claims (10)

  1. N비트 입력 신호를 수신하도록 결합되는 제1입력을 갖는 제1가산기, 상기 제1가산기의 출력을 수신하도록 결합되는 입력을 갖는 N비트 래치, 상기 N비트 래치의 출력을 수신하도록 결합되는 입력 및, M〈N인, M비트 출력을 갖는 M비트 하드 퀀타이저(hard quantizer), 상기 N비트 래치로부터 N비트 샘플을 수신하도록 결합되는 제1입력 및 상기 M비트 하드 퀀타이저로부터 N비트 샘플을 수신하도록 결합되는 제2입력을 갖는 제2가산기로서, 상기 M비트 하드 쿼타이저로부터의 상기 N비트 샘플은 상기 N비트 샘플 중의 M비트 및 적어도 하나의 N-M제로 비트를 포함하는 제2가산기, 및 상기 제2가산기의 출력을 수신하도록 결합되는 입력 및 상기 제1가산기의 제2입력에 결합되는 출력을 갖는 필터를 포함하는 양자화 잡음(quantization noise)을 줄이기 위한 장치.
  2. 제1항에 있어서, 상기 제1가산기는 상기 제1입력과 상기 제2입력간의 차이를 취하도록 동작 가능한 양자화 잡음을 줄이기 위한 장치.
  3. 제1항에 있어서, 상기 제2가산기는 상기 제1입력과 상기 제2입력간의 차이를 취하도록 동작 가능한 양자화 잡음을 줄이기 위한 장치.
  4. 제1항에 있어서, 상기 필터는 저역 필터(low pass filter, LPF)인 양자화 잡음을 줄이기 위한 장치.
  5. 제1항에 있어서, 상기 필터는 사실상 N비트 입력 신호의 사용 가능한 대역 아래에 차단 주파수(cut-off frequency)를 갖는 양자화 잡음을 줄이기 위한 장치.
  6. 제1항에 있어서, 상기 필터는 1(unity)보다 큰 이득을 갖는 양자화 잡음을 줄이기 위한 장치.
  7. 제1항에 있어서, 상기 M비트 하드 퀀타이저로부터의 상기 N비트 샘플은 상기 N비트 래치로부터의 상기 N비트 샘플 중의 M비트의 최대 유효 비트를 및 적어도 하나의 N-M제로 비트를 포함하는 양자화 잡음을 줄이기 위한 장치.
  8. 제1항에 있어서, 상기 M비트 하드 퀀타이저로부터의 상기 N비트 샘플은 상기 N비트 래치로부터의 상기 N비트 샘플 중의 M비트의 최대 유효 비트들에 대응하는 M비트의 최대 유효 비트들 및 N-M제로 비트들을 포함하는 양자화 잡음을 줄이기 위한 장치.
  9. N비트 입력 신호의 N비트 샘플과, M〈N인, N비트 샘플의 M비트들 및 N-M제로 비트들을 포함하는 N비트 양자화된 샘플간의 차이를 취하는 단계, 상기 차이를 필터링하여 필터링된 차이를 형성하는 단계, 및 상기 필터링된 차이를 상기 N비트 입력 신호에서 빼는 단계를 포함하는 양자화 잡음을 줄이는 방법.
  10. 제9항에 있어서, 상기 차이를 취하는 단계는, N비트 입력 신호 중의 M비트의 최대 유효 비트들 및 N-M제로 비트들을 포함하는 N비트 양자화된 샘플과 상기 N비트 입력 신호의 N비트 샘플간의 차이를 취하는 단계를 포함하는 양자화 잡음을 줄이는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960705734A 1995-02-14 1995-12-28 양자화 잡음을 줄이는 방법 및 장치(Method and Apparatus for Reducing Quantization Noise) KR970702630A (ko)

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PCT/US1995/017018 WO1996025809A1 (en) 1995-02-14 1995-12-28 Method and apparatus for reducing quantization noise

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AU4610796A (en) 1996-09-04
CA2185026A1 (en) 1996-08-22
ITRM960095A0 (ko) 1996-02-09
SE9603698L (sv) 1996-11-27
DE19581576T1 (de) 1997-05-28
US5602874A (en) 1997-02-11
IL116661A0 (en) 1996-05-14
WO1996025809A1 (en) 1996-08-22
FI963491A0 (fi) 1996-09-06
GB9602899D0 (en) 1996-04-10
FI963491A (fi) 1996-09-06
FR2730590A1 (fr) 1996-08-14
IT1283923B1 (it) 1998-05-07
GB2298069A (en) 1996-08-21
CN1145707A (zh) 1997-03-19
SE9603698D0 (sv) 1996-10-10

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