KR860700165A - X×y 비트배열 배율기/어큐뮬레이터 회로 - Google Patents
X×y 비트배열 배율기/어큐뮬레이터 회로Info
- Publication number
- KR860700165A KR860700165A KR1019860700053A KR860700053A KR860700165A KR 860700165 A KR860700165 A KR 860700165A KR 1019860700053 A KR1019860700053 A KR 1019860700053A KR 860700053 A KR860700053 A KR 860700053A KR 860700165 A KR860700165 A KR 860700165A
- Authority
- KR
- South Korea
- Prior art keywords
- bit array
- accumulator circuit
- array multiplier
- multiplier
- accumulator
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3876—Alternation of true and inverted stages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
- G06F2207/4812—Multiplexers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49994—Sign extension
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US615.989 | 1984-05-31 | ||
US06/615,989 US4575812A (en) | 1984-05-31 | 1984-05-31 | X×Y Bit array multiplier/accumulator circuit |
PCT/US1985/000511 WO1985005705A1 (en) | 1984-05-31 | 1985-03-28 | AN XxY BIT ARRAY MULTIPLIER/ACCUMULATOR CIRCUIT |
Publications (2)
Publication Number | Publication Date |
---|---|
KR860700165A true KR860700165A (ko) | 1986-03-31 |
KR920007029B1 KR920007029B1 (ko) | 1992-08-24 |
Family
ID=24467600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860700053A KR920007029B1 (ko) | 1984-05-31 | 1985-03-28 | X×y 비트 배열 배율기/어큐뮬레이터 회로 |
Country Status (7)
Country | Link |
---|---|
US (1) | US4575812A (ko) |
EP (1) | EP0185025B1 (ko) |
JP (1) | JPS61502288A (ko) |
KR (1) | KR920007029B1 (ko) |
DE (1) | DE3583999D1 (ko) |
IT (1) | IT1181661B (ko) |
WO (1) | WO1985005705A1 (ko) |
Families Citing this family (103)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6068432A (ja) * | 1983-09-22 | 1985-04-19 | Hitachi Ltd | キヤリセ−ブアダ−の符号生成方式 |
JPS60237534A (ja) * | 1984-05-09 | 1985-11-26 | Toshiba Corp | 並列乗算器 |
JPS61114338A (ja) * | 1984-11-09 | 1986-06-02 | Hitachi Ltd | 乗算器 |
JPS6222146A (ja) * | 1985-07-23 | 1987-01-30 | Toshiba Corp | 並列乗算器 |
JPH0831025B2 (ja) * | 1986-03-29 | 1996-03-27 | 株式会社東芝 | 乗算回路 |
JPS62229440A (ja) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | 配列乗算器 |
JPS62229439A (ja) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | 並列乗算器 |
US4831577A (en) * | 1986-09-17 | 1989-05-16 | Intersil, Inc. | Digital multiplier architecture with triple array summation of partial products |
US4864529A (en) * | 1986-10-09 | 1989-09-05 | North American Philips Corporation | Fast multiplier architecture |
JPS63241634A (ja) * | 1987-03-30 | 1988-10-06 | Toshiba Corp | 並列型加算回路 |
US4817029A (en) * | 1987-05-11 | 1989-03-28 | United Technologies Corporation | Multiple-precision Booth's recode multiplier |
US4843585A (en) * | 1987-09-14 | 1989-06-27 | Motorola, Inc. | Pipelineable structure for efficient multiplication and accumulation operations |
US5103419A (en) * | 1989-02-02 | 1992-04-07 | Matsushita Electric Industrial Co., Ltd. | Circuit for calculating the sum of products of data |
US5038315A (en) * | 1989-05-15 | 1991-08-06 | At&T Bell Laboratories | Multiplier circuit |
US5184318A (en) * | 1989-09-05 | 1993-02-02 | Cyrix Corporation | Rectangular array signed digit multiplier |
US5144576A (en) * | 1989-09-05 | 1992-09-01 | Cyrix Corporation | Signed digit multiplier |
US5262976A (en) * | 1989-11-13 | 1993-11-16 | Harris Corporation | Plural-bit recoding multiplier |
DE69032391T2 (de) * | 1989-11-13 | 1998-10-29 | Harris Corp | Mehrere Bit umkodierender Multiplizierer |
US5113363A (en) * | 1989-12-29 | 1992-05-12 | Ail Systems, Inc. | Method and apparatus for computing arithmetic expressions using on-line operands and bit-serial processing |
CA2038422A1 (en) * | 1990-03-16 | 1991-09-17 | Tai Sato | Array multiplier |
US5151875A (en) * | 1990-03-16 | 1992-09-29 | C-Cube Microsystems, Inc. | MOS array multiplier cell |
KR920006323B1 (ko) * | 1990-05-31 | 1992-08-03 | 삼성전자 주식회사 | 스킵(Skip)배열과 수정형 월리스(Wallace)트리를 사용하는 병렬 승산기 |
US5138570A (en) * | 1990-09-20 | 1992-08-11 | At&T Bell Laboratories | Multiplier signed and unsigned overflow flags |
US5101372A (en) * | 1990-09-28 | 1992-03-31 | International Business Machines Corporation | Optimum performance standard cell array multiplier |
US5220525A (en) * | 1991-11-04 | 1993-06-15 | Motorola, Inc. | Recoded iterative multiplier |
EP0589148A1 (en) * | 1992-09-22 | 1994-03-30 | Motorola, Inc. | Multiplexer circuit for modified booth's multiplier or the like |
GB2317978B (en) * | 1994-03-02 | 1998-05-20 | Advanced Risc Mach Ltd | Electronic multiplying and adding apparatus and method |
US5436860A (en) * | 1994-05-26 | 1995-07-25 | Motorola, Inc. | Combined multiplier/shifter and method therefor |
US5442576A (en) * | 1994-05-26 | 1995-08-15 | Motorola, Inc. | Multibit shifting apparatus, data processor using same, and method therefor |
US5801978A (en) * | 1994-09-22 | 1998-09-01 | National Semiconductor Corporation | Overflow detection for integer-multiply instruction |
US5808927A (en) * | 1994-10-18 | 1998-09-15 | International Business Machines Corporation | Apparatus for performing two's complement and unsigned multiply accumulate |
US5598362A (en) * | 1994-12-22 | 1997-01-28 | Motorola Inc. | Apparatus and method for performing both 24 bit and 16 bit arithmetic |
US5666300A (en) * | 1994-12-22 | 1997-09-09 | Motorola, Inc. | Power reduction in a data processing system using pipeline registers and method therefor |
US5638313A (en) * | 1995-01-30 | 1997-06-10 | Cirrus Logic, Inc. | Booth multiplier with high speed output circuitry |
US5734601A (en) | 1995-01-30 | 1998-03-31 | Cirrus Logic, Inc. | Booth multiplier with low power, high performance input circuitry |
FR2734675B1 (fr) * | 1995-05-24 | 1997-08-14 | Sgs Thomson Microelectronics | Circuit logique combinatoire |
US5751619A (en) * | 1996-01-22 | 1998-05-12 | International Business Machines Corporation | Recurrent adrithmetical computation using carry-save arithmetic |
EP0798744B1 (en) * | 1996-03-29 | 2003-12-03 | STMicroelectronics S.r.l. | Timing characterization circuit and method for memory devices |
US6066178A (en) * | 1996-04-10 | 2000-05-23 | Lsi Logic Corporation | Automated design method and system for synthesizing digital multipliers |
US5773995A (en) * | 1996-04-22 | 1998-06-30 | Motorola, Inc. | Digital multiplexer circuit |
US5761106A (en) * | 1996-06-24 | 1998-06-02 | Motorola, Inc. | Horizontally pipelined multiplier circuit |
US5796645A (en) * | 1996-08-27 | 1998-08-18 | Tritech Microelectronics International Ltd. | Multiply accumulate computation unit |
JP3678512B2 (ja) * | 1996-08-29 | 2005-08-03 | 富士通株式会社 | 乗算回路、該乗算回路を構成する加算回路、該乗算回路の部分積ビット圧縮方法、および、該乗算回路を適用した大規模半導体集積回路 |
US5943250A (en) * | 1996-10-21 | 1999-08-24 | Samsung Electronics Co., Ltd. | Parallel multiplier that supports multiple numbers with different bit lengths |
EP0840207A1 (en) * | 1996-10-30 | 1998-05-06 | Texas Instruments Incorporated | A microprocessor and method of operation thereof |
US5835393A (en) * | 1996-11-19 | 1998-11-10 | Audiologic Hearing Systems, L.P. | Integrated pre-adder for a multiplier |
US5974437A (en) * | 1996-12-02 | 1999-10-26 | Synopsys, Inc. | Fast array multiplier |
US6055619A (en) * | 1997-02-07 | 2000-04-25 | Cirrus Logic, Inc. | Circuits, system, and methods for processing multiple data streams |
US6259957B1 (en) | 1997-04-04 | 2001-07-10 | Cirrus Logic, Inc. | Circuits and methods for implementing audio Codecs and systems using the same |
US6183122B1 (en) * | 1997-09-04 | 2001-02-06 | Cirrus Logic, Inc. | Multiplier sign extension |
US6029187A (en) * | 1997-10-28 | 2000-02-22 | Atmel Corporation | Fast regular multiplier architecture |
US6571268B1 (en) | 1998-10-06 | 2003-05-27 | Texas Instruments Incorporated | Multiplier accumulator circuits |
US6523055B1 (en) | 1999-01-20 | 2003-02-18 | Lsi Logic Corporation | Circuit and method for multiplying and accumulating the sum of two products in a single cycle |
US6215325B1 (en) | 1999-03-29 | 2001-04-10 | Synopsys, Inc. | Implementing a priority function using ripple chain logic |
DE60027149D1 (de) | 2000-08-01 | 2006-05-18 | St Microelectronics Sa | Aritmetik Einheit |
US20020114380A1 (en) * | 2000-12-21 | 2002-08-22 | Xiaoshu Qian | Combined pre-equalizer and nyquist filter |
US8620980B1 (en) | 2005-09-27 | 2013-12-31 | Altera Corporation | Programmable device with specialized multiplier blocks |
US8266198B2 (en) * | 2006-02-09 | 2012-09-11 | Altera Corporation | Specialized processing block for programmable logic device |
US8301681B1 (en) | 2006-02-09 | 2012-10-30 | Altera Corporation | Specialized processing block for programmable logic device |
US8266199B2 (en) * | 2006-02-09 | 2012-09-11 | Altera Corporation | Specialized processing block for programmable logic device |
US8041759B1 (en) | 2006-02-09 | 2011-10-18 | Altera Corporation | Specialized processing block for programmable logic device |
US7836117B1 (en) | 2006-04-07 | 2010-11-16 | Altera Corporation | Specialized processing block for programmable logic device |
US8386550B1 (en) | 2006-09-20 | 2013-02-26 | Altera Corporation | Method for configuring a finite impulse response filter in a programmable logic device |
FR2908905A1 (fr) * | 2006-11-20 | 2008-05-23 | R L Daniel Torno Sa | Procede et circuit multiplieur de nombres binaires |
US8386553B1 (en) | 2006-12-05 | 2013-02-26 | Altera Corporation | Large multiplier for programmable logic device |
US7930336B2 (en) | 2006-12-05 | 2011-04-19 | Altera Corporation | Large multiplier for programmable logic device |
US8650231B1 (en) | 2007-01-22 | 2014-02-11 | Altera Corporation | Configuring floating point operations in a programmable device |
US7865541B1 (en) | 2007-01-22 | 2011-01-04 | Altera Corporation | Configuring floating point operations in a programmable logic device |
US8645450B1 (en) | 2007-03-02 | 2014-02-04 | Altera Corporation | Multiplier-accumulator circuitry and methods |
US7949699B1 (en) | 2007-08-30 | 2011-05-24 | Altera Corporation | Implementation of decimation filter in integrated circuit device using ram-based data storage |
US8959137B1 (en) | 2008-02-20 | 2015-02-17 | Altera Corporation | Implementing large multipliers in a programmable integrated circuit device |
US8307023B1 (en) | 2008-10-10 | 2012-11-06 | Altera Corporation | DSP block for implementing large multiplier on a programmable integrated circuit device |
US8468192B1 (en) | 2009-03-03 | 2013-06-18 | Altera Corporation | Implementing multipliers in a programmable integrated circuit device |
US8645449B1 (en) | 2009-03-03 | 2014-02-04 | Altera Corporation | Combined floating point adder and subtractor |
US8706790B1 (en) | 2009-03-03 | 2014-04-22 | Altera Corporation | Implementing mixed-precision floating-point operations in a programmable integrated circuit device |
US8650236B1 (en) | 2009-08-04 | 2014-02-11 | Altera Corporation | High-rate interpolation or decimation filter in integrated circuit device |
US8396914B1 (en) | 2009-09-11 | 2013-03-12 | Altera Corporation | Matrix decomposition in an integrated circuit device |
US8412756B1 (en) | 2009-09-11 | 2013-04-02 | Altera Corporation | Multi-operand floating point operations in a programmable integrated circuit device |
US7948267B1 (en) | 2010-02-09 | 2011-05-24 | Altera Corporation | Efficient rounding circuits and methods in configurable integrated circuit devices |
US8539016B1 (en) | 2010-02-09 | 2013-09-17 | Altera Corporation | QR decomposition in an integrated circuit device |
US8601044B2 (en) * | 2010-03-02 | 2013-12-03 | Altera Corporation | Discrete Fourier Transform in an integrated circuit device |
US8484265B1 (en) | 2010-03-04 | 2013-07-09 | Altera Corporation | Angular range reduction in an integrated circuit device |
US8510354B1 (en) | 2010-03-12 | 2013-08-13 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8539014B2 (en) * | 2010-03-25 | 2013-09-17 | Altera Corporation | Solving linear matrices in an integrated circuit device |
US8589463B2 (en) | 2010-06-25 | 2013-11-19 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8862650B2 (en) | 2010-06-25 | 2014-10-14 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8577951B1 (en) | 2010-08-19 | 2013-11-05 | Altera Corporation | Matrix operations in an integrated circuit device |
US8645451B2 (en) | 2011-03-10 | 2014-02-04 | Altera Corporation | Double-clocked specialized processing block in an integrated circuit device |
US9600278B1 (en) | 2011-05-09 | 2017-03-21 | Altera Corporation | Programmable device using fixed and configurable logic to implement recursive trees |
US8812576B1 (en) | 2011-09-12 | 2014-08-19 | Altera Corporation | QR decomposition in an integrated circuit device |
US8949298B1 (en) | 2011-09-16 | 2015-02-03 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US9053045B1 (en) | 2011-09-16 | 2015-06-09 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US8762443B1 (en) | 2011-11-15 | 2014-06-24 | Altera Corporation | Matrix operations in an integrated circuit device |
US8543634B1 (en) | 2012-03-30 | 2013-09-24 | Altera Corporation | Specialized processing block for programmable integrated circuit device |
US9098332B1 (en) | 2012-06-01 | 2015-08-04 | Altera Corporation | Specialized processing block with fixed- and floating-point structures |
US8996600B1 (en) | 2012-08-03 | 2015-03-31 | Altera Corporation | Specialized processing block for implementing floating-point multiplier with subnormal operation support |
US9207909B1 (en) | 2012-11-26 | 2015-12-08 | Altera Corporation | Polynomial calculations optimized for programmable integrated circuit device structures |
US9189200B1 (en) | 2013-03-14 | 2015-11-17 | Altera Corporation | Multiple-precision processing block in a programmable integrated circuit device |
US9348795B1 (en) | 2013-07-03 | 2016-05-24 | Altera Corporation | Programmable device using fixed and configurable logic to implement floating-point rounding |
JP5951570B2 (ja) | 2013-09-13 | 2016-07-13 | 株式会社東芝 | 行列演算装置 |
US9684488B2 (en) | 2015-03-26 | 2017-06-20 | Altera Corporation | Combined adder and pre-adder for high-radix multiplier circuit |
US10459876B2 (en) * | 2018-01-31 | 2019-10-29 | Amazon Technologies, Inc. | Performing concurrent operations in a processing element |
US11960854B2 (en) | 2020-09-22 | 2024-04-16 | Advanced Micro Devices, Inc. | Time domain multiply and accumulate system |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4153938A (en) * | 1977-08-18 | 1979-05-08 | Monolithic Memories Inc. | High speed combinatorial digital multiplier |
US4168530A (en) * | 1978-02-13 | 1979-09-18 | Burroughs Corporation | Multiplication circuit using column compression |
FR2524175A1 (fr) * | 1982-03-25 | 1983-09-30 | Labo Cent Telecommunicat | Structure de multiplieur rapide en circuit integre mos |
-
1984
- 1984-05-31 US US06/615,989 patent/US4575812A/en not_active Expired - Lifetime
-
1985
- 1985-03-28 DE DE8585901830T patent/DE3583999D1/de not_active Expired - Lifetime
- 1985-03-28 KR KR1019860700053A patent/KR920007029B1/ko not_active IP Right Cessation
- 1985-03-28 EP EP85901830A patent/EP0185025B1/en not_active Expired - Lifetime
- 1985-03-28 WO PCT/US1985/000511 patent/WO1985005705A1/en active IP Right Grant
- 1985-03-28 JP JP60501558A patent/JPS61502288A/ja active Granted
- 1985-05-07 IT IT48053/85A patent/IT1181661B/it active
Also Published As
Publication number | Publication date |
---|---|
IT1181661B (it) | 1987-09-30 |
EP0185025A4 (ko) | 1986-09-04 |
EP0185025B1 (en) | 1991-09-04 |
KR920007029B1 (ko) | 1992-08-24 |
IT8548053A1 (it) | 1986-11-07 |
US4575812A (en) | 1986-03-11 |
JPH0555894B2 (ko) | 1993-08-18 |
WO1985005705A1 (en) | 1985-12-19 |
DE3583999D1 (de) | 1991-10-10 |
IT8548053A0 (it) | 1985-05-07 |
EP0185025A1 (ko) | 1986-06-25 |
JPS61502288A (ja) | 1986-10-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR860700165A (ko) | X×y 비트배열 배율기/어큐뮬레이터 회로 | |
DE3566711D1 (en) | Hydraulic circuit with accumulator | |
IT1184389B (it) | Batteria di accumulatori | |
FR2564260B1 (fr) | Circuit de preaccentuation | |
GB8512986D0 (en) | Non-volatile memory circuit | |
DE3585187D1 (de) | Elektronische drucktafel. | |
EP0171720A3 (en) | Data delay/memory circuit | |
GB8505664D0 (en) | Memory access circuit | |
DE3565576D1 (de) | Oleoelastic energy accumulator | |
DK486884A (da) | Celledelt element | |
DE3581596D1 (de) | Festwertspeicherschaltung. | |
EP0186745A3 (en) | Memory array | |
DE3577967D1 (de) | Modul-schaltkreis. | |
FR2568709B1 (fr) | Circuit matriciel | |
DE3587387D1 (de) | Speicherschnittstellenschaltung. | |
GB8422732D0 (en) | Memory cells | |
KR870001108U (ko) | 다중 메모리 회로 | |
KR860004208U (ko) | 이중면의 제조장치 | |
KR850007194U (ko) | 전자 안테나 | |
SG120193G (en) | An XXY bit array multiplier/accumulator circuit. | |
FR2582434B1 (fr) | Guitare-synthetiseur sans cordes | |
AT382728B (de) | Multiplizierschaltung | |
KR860008399U (ko) | 리셋트 회로 | |
BR6400495U (pt) | Adorno eletronico | |
BR8403605A (pt) | Minuteria eletronica |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20041004 Year of fee payment: 13 |
|
EXPY | Expiration of term |