KR20210031438A - Variable low resistance area based memory device and controlling thereof - Google Patents

Abstract

According to an embodiment of the present invention, disclosed is a memory element based on a variable low resistance area which can improve element integration. The memory element based on a variable low resistance area comprises: a base including a spontaneously polarizable material; a gate disposed adjacent to the base; a polarization area formed in the base by applying an electric field to the base through the gate; one or more variable low resistance areas corresponding to a boundary of the polarization area and including an area having a lower electrical resistance than other adjacent areas; a source spaced apart from the gate and connected to the variable low resistance area; and a drain spaced apart from the gate and connected to the variable low resistance area.

Description

Variable low resistance area based memory device and controlling method thereof

The present invention relates to a memory device using a variable low resistance region and a method for controlling the same.

As technology advances and interest in the convenience of people's life increases, attempts to develop various electronic products are becoming more active.

In addition, these electronic products are becoming smaller and more integrated, and the places where they are used are increasing widely.

Such electronic products include various electrical devices, for example, CPU, memory, and various other electrical devices. These elements may include various types of electric circuits.

For example, electrical devices are used in products in various fields, such as home sensor devices for IoT and bioelectronic devices for ergonomics, as well as computers and smartphones.

On the other hand, with the recent speed of technology development and the rapid improvement of the living standards of users, the use and application fields of such electric devices are rapidly increasing, and the demand thereof is also increasing accordingly.

According to this trend, there is a limit to implementing and controlling electronic circuits that are easily and quickly applied to various electric devices that are commonly used.

On the other hand, memory devices, especially nonvolatile memory devices, are widely used as information storage and/or processing devices for various electronic devices such as cameras and communication devices as well as computers.

In particular, many developments have been made in terms of the life and speed of such a memory device. Most of the problems are in securing the life and speed of the memory, but there is a limit to implementing a memory device that improves the memory device.

The present invention can provide a variable low-resistance region-based memory device that can be easily applied to various uses, a memory device having a long data retention period, a high memory speed, and improving device integration, and a control method thereof. .

An embodiment of the present invention corresponds to a base comprising a spontaneous polarization material, a gate disposed adjacent to the base, a polarization region formed on the base by applying an electric field to the base through the gate, and a boundary of the polarization region. Thus, at least one fluctuating low-resistance region including a region having a lower electrical resistance than other adjacent regions, a source spaced apart from the gate and connected to the fluctuating low-resistance region, and a drain spaced apart from the gate and connected to the fluctuating low-resistance region. Disclosed is a variable low-resistance region-based memory device including.

In this embodiment, the low fluctuation resistance region is disposed closer to the gate than the first fluctuation low resistance region and the first fluctuation low resistance region is spaced apart from the gate, and is spaced apart from the first fluctuation low resistance region. It is possible to selectively include one of the 2 fluctuation low resistance regions.

In this embodiment, the low fluctuation resistance region is disposed closer to the gate than the first fluctuation low resistance region and the first fluctuation low resistance region is spaced apart from the gate, and is spaced apart from the first fluctuation low resistance region. It may include 2 fluctuation low resistance regions.

In the present exemplary embodiment, the source may have a shape elongated so as to correspond to a second variable low resistance region spaced apart from the first variable low resistance region.

In the present exemplary embodiment, the drain may have a shape elongated so as to correspond to a second variable low resistance region spaced apart from the first variable low resistance region.

In the present embodiment, it may be formed to store different information according to the formation of the first fluctuating low-resistance region or the second fluctuating low-resistance region.

In the present embodiment, the fluctuation low resistance region may be generated or destroyed according to the control of the polarization region by controlling the electric field through the gate.

In this embodiment, the variable low resistance region may be maintained even when the electric field applied through the gate is removed.

According to another aspect of the present invention, a base comprising a spontaneous polarization material, a gate disposed adjacent to the base, a source spaced apart from the gate and connected to the variable low resistance region; And forming a polarization region of the base by applying an electric field to the base through the gate for a memory device based on a variable low resistance region including a drain spaced apart from the gate and connected to the variable low resistance region, and the Forming a fluctuating low-resistance region including a region having a lower electrical resistance than other adjacent regions corresponding to the boundary of the polarization region so that the flow of current between the source and the drain is formed through the fluctuating low-resistance region. Disclosed is a method for controlling a memory device based on a variable low-resistance region comprising a.

In this embodiment, the low fluctuation resistance region is disposed closer to the gate than the first fluctuation low resistance region and the first fluctuation low resistance region is spaced apart from the gate, and is spaced apart from the first fluctuation low resistance region. It is possible to selectively include one of the 2 fluctuation low resistance regions.

In this embodiment, the low fluctuation resistance region is disposed closer to the gate than the first fluctuation low resistance region and the first fluctuation low resistance region is spaced apart from the gate, and is spaced apart from the first fluctuation low resistance region. It may include 2 fluctuation low resistance regions.

The present embodiment may include measuring a current between the source and the drain as the first variable low resistance region or the second variable low resistance region is formed while controlling the gate.

In the present embodiment, it may include the step of controlling the electric field through the gate and generating or extinguishing the fluctuating low resistance region according to the control of the polarization region.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

The electronic circuit using the variable low resistance region and the control method thereof according to the present invention can be easily applied to various applications.

1 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.
3 is an enlarged view of K in FIG. 2.
4A to 4C are diagrams for explaining a control method related to the electronic circuit of FIG. 1. 5 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.
6 is a cross-sectional view taken along line VI-VI of FIG. 5.
7A to 7D are diagrams for explaining a method of controlling a current path range in relation to the electronic circuit of FIG. 5.
8 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention.
9 is a cross-sectional view taken along line II-II of FIG. 8.
10 to 14 are diagrams for explaining the operation of the electronic circuit of FIG. 8.
15 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.
16 is a cross-sectional view taken along line V-V of FIG. 15.
17 is a schematic plan view illustrating a memory device according to still another embodiment of the present invention.
18 is a cross-sectional view taken along line VI-VI of FIG. 17.
19 is a graph showing a voltage and current relationship between a first region and a low fluctuation resistance region.
20 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.
21 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.
22 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.
23 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.
24 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.
25 to 27 are diagrams for explaining a variable low resistance region memory device according to another embodiment of the present invention.
28 to 34 are diagrams for describing a variable low resistance region memory device according to another embodiment of the present invention.
35 is a diagram for describing an example of an operation of a memory device according to an embodiment of the present invention.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to embodiments of the present invention shown in the accompanying drawings.

Since the present invention can apply various transformations and have various embodiments, specific embodiments are illustrated in the drawings and will be described in detail in the detailed description. Effects and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when describing with reference to the drawings, the same or corresponding constituent elements are assigned the same reference numerals, and redundant descriptions thereof will be omitted. .

In the following embodiments, terms such as first and second are used for the purpose of distinguishing one constituent element from other constituent elements rather than a limiting meaning.

In the following examples, expressions in the singular include plural expressions unless the context clearly indicates otherwise.

In the following embodiments, terms such as include or have means that the features or elements described in the specification are present, and do not preclude the possibility of adding one or more other features or components in advance.

In the drawings, components may be exaggerated or reduced in size for convenience of description. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, and thus the present invention is not necessarily limited to what is shown.

In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes on a Cartesian coordinate system, and may be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

When a certain embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the described order.

1 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and FIG. 3 is an enlarged view of K of FIG. 2.

Referring to FIGS. 1 and 2, the electronic circuit 10 of the present embodiment may include an active layer 11, an application electrode 12, and a variable low resistance region VL.

The active layer 11 may include a spontaneous polarization material. For example, the active layer 11 may include an insulating material and may include a ferroelectric material. That is, the active layer 11 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment the active layer 11 may comprise a perovskite-based material, for example, it may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

In addition, as another example, the active layer 11 has an ABX3 structure, where A may include one or more materials selected from inorganic materials such as Cs, Ru, etc., capable of forming a CnH2n+1 alkyl group, and a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the active layer 11 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _3, CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _{1-y PbCl x} Br _3-x (0≤x, y≤1) can do.

Since the active layer 11 may be formed by using various other ferroelectric materials, descriptions of all examples thereof will be omitted. In addition, when the active layer 11 is formed, the ferroelectric material may be doped with various other materials to include an additional function or to improve electrical characteristics.

The active layer 11 has spontaneous polarization, and the degree and direction of polarization can be controlled according to the application of an electric field. In addition, the active layer 11 can maintain a polarized state even when the applied electric field is removed.

The application electrode 12 may be formed to apply an electric field to the active layer 11, and for example, a voltage may be applied to the active layer 11.

As an alternative embodiment, the application electrode 12 may be formed to be in contact with the upper surface of the active layer 11.

In addition, the application electrode 12 may be formed to apply voltages of various sizes to the active layer 11 and to control the time of application of the voltage.

As an alternative embodiment, the application electrode 12 may be a gate electrode.

For example, the application electrode 12 may be electrically connected to a power source (not shown) or a power control unit.

The application electrode 12 may include various materials, and may include a material having high electrical conductivity. For example, the application electrode 12 may be formed using various metals.

For example, the application electrode 12 may be formed to contain aluminum, chromium, titanium, tantalum, molybdenum, tungsten, neodymium, scandium, or copper. Alternatively, it may be formed using an alloy of these materials, or may be formed using a nitride of these materials.

In addition, as an optional embodiment, the application electrode 12 may include a laminate structure.

Although not shown, as an optional embodiment, one or more insulating layers may be further disposed between the application electrode 12 and the active layer 11.

The variable low resistance region VL is a region formed in the active layer 11 and is a region through which a current can flow, and may be formed as a path of a current having a linear shape around the application electrode 12 as shown in FIG. 1. have.

Specifically, the low-variable resistance region VL is a region in which electrical resistance is lower than that of other regions adjacent to the low-variable resistance region VL among the regions of the active layer 11.

In addition, after forming the variable low resistance region VL through the application electrode 12, even if the electric field through the application electrode 12 is removed, for example, even if the voltage is removed, the polarization state of the active layer 11 is Since it is maintained, the fluctuating low resistance region VL is maintained, and a state in which a path of current is formed can be maintained.

Through this, various electronic circuits can be configured.

The variable low resistance region VL has a height HVL, and this height HVL may correspond to the overall thickness of the active layer 11.

The height HVL of the fluctuating low resistance region VL may be proportional to the strength of the electric field, for example, the magnitude of the voltage when the electric field is applied through the application electrode 12. At least the magnitude of this electric field may be larger than the inherent anti-electric field of the active layer 11.

The variable low-resistance region VL is a region formed when a voltage is applied to the active layer 11 through the application electrode 12, and can be changed, for example, generated, destroyed, or moved through the control of the application electrode 12. .

The active layer 11 may include a first polarization region 11F having a first polarization direction, and the variable low resistance region VL may be formed at the boundary of the first polarization region 11F.

In addition, a second polarization region 11R having a second polarization direction may be included so as to be adjacent to the first polarization region 11F, and the variable low resistance region VL is at the boundary of the second polarization region 11R. Can be formed. The second direction may be at least different from the first direction, for example, may be a direction opposite to the first direction.

For example, the variable low resistance region VL may be formed between the first polarization region 11F and the second polarization region 11R.

The variable low resistance region VL may have a width WVL in one direction, which may be proportional to the moving distance of the variable low resistance region VL.

In addition, the width WVL may be the width of a planar region defined as the variable low resistance region VL, which can be said to correspond to the width of the first polarization region 11F.

In addition, the variable low resistance region VL may be formed to correspond to the entire side surface of the boundary line of the first polarization region 11F, and may have a thickness TVL1 in a direction away from the side surface of the first polarization region 11F. have.

As an optional embodiment, this thickness (TVL1) may be 0.1 to 0.3 nanometers.

4A to 4C are diagrams for explaining a method of controlling a current path range for the electronic circuit of FIG. 1.

Referring to FIG. 4A, the active layer 11 may include a second polarization region 11R having a second polarization direction. As an alternative embodiment, a polarization state of the active layer 11 as shown in FIG. 4A may be formed by applying an initializing electric field through the application electrode 12.

Then, referring to FIG. 4B, a first polarization region 11F is formed in the active layer 11. As a specific example, the first polarization region 11F may be first formed in a region overlapping the application electrode 12 so as to correspond to the width of the application electrode 12.

It is larger than the coercive electric field of the active layer 11 through the application electrode 12, and has a size such that the height HVL of the first polarization region 11F can be formed to at least correspond to the entire thickness of the active layer 11. An electric field may be applied to the active layer 11.

Through the application of the electric field through the application electrode 12, the polarization direction of one region of the second polarization region 11R of the active layer 11 may be changed to change the polarization direction to the first polarization region 11F.

As an alternative embodiment, the growth rate in the height HVL direction of the first polarization region 11F may be very fast, for example, it may grow at a rate of 1 km/sec (second).

Then, if the electric field through the applied electrode 12 is continuously maintained, that is, over time, the first polarization region 11F moves in the horizontal direction (H), that is, in a direction orthogonal to the height (HVL), and its size increases. I can. That is, the area of the second polarization area 11R may be gradually converted into the first polarization area 11F.

As an alternative embodiment, the growth rate of the first polarization region 11F in the horizontal direction H may be very fast, for example, it may grow at a rate of 1 m/sec (second).

Through this, the size of the fluctuating low resistance region VL can be controlled. This size is, for example, the width of the fluctuating low resistance region VL and corresponds to the growth distance of the first polarization region 11F, so the growth speed and electric field It can be proportional to the holding time. For example, the growth distance may be proportional to the product of the growth speed and the duration of the electric field.

In addition, the growth speed of the first polarization region 11F may be proportional to the sum of the growth speed in the height HVL direction and the growth speed in the horizontal direction H.

Therefore, the size of the fluctuating low resistance region VL can be adjusted as desired by controlling the electric field holding time.

Specifically, as shown in FIG. 4C, the first polarization region 11F spreads and increases, and accordingly, the fluctuation low resistance region VL may also move in a direction away from the application electrode 12.

In this embodiment, a first polarization region having a first polarization direction different from the second polarization direction is formed in the active layer by applying an electric field to the active layer through the application electrode, and at the boundary between the first polarization region and the second polarization region. A corresponding fluctuation low resistance region can be formed. Such a low-variable resistance region is a region having a low resistance and a region having a reduced resistance, and can be a path of a current, so that an electronic circuit can be easily formed.

In addition, in this embodiment, by controlling the magnitude of the electric field through the applied electrode, for example, by controlling the magnitude of the voltage, the height of the fluctuating low-resistance region can be determined, and specifically, it is controlled to have a height corresponding to the total thickness of the active layer. can do.

In addition, it is possible to determine the size, for example, the width of the variable low resistance region by controlling the time to maintain the electric field through the applied electrode. Through the control of the size of the fluctuation low resistance region, the size of the path of the current flow can be easily controlled.

In addition, even if the electric field through the applied electrode is removed, the polarization state of the polarized region is maintained, so the path of the current can be easily maintained. When the polarization region is expanded by continuously maintaining the electric field through the applied electrode, the already formed fluctuation is reduced. In the resistance region, resistance may be lowered so that no current flows.

Through this, it is possible to control the dissipation of the current path, and as a result, it is possible to easily control the flow of the current.

The electronic circuit of the present embodiment can be controlled to be used for various purposes, and for example, one or more electrodes can be connected so as to contact a variable low resistance region.

5 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.

6 is a cross-sectional view taken along line VI-VI of FIG. 5.

5 and 6, the electronic circuit 20 of the present embodiment may include an active layer 21, an application electrode 22, and variable low resistance regions VL1, VL2, and VL3.

The active layer 21 may include a spontaneous polarization material. For example, the active layer 21 may include an insulating material and may include a ferroelectric material. That is, the active layer 21 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the active layer 21 may include a perovskite-based material, and a detailed description thereof will be omitted since it is the same as the above-described embodiment.

The application electrode 22 may be formed to apply an electric field to the active layer 21, and for example, a voltage may be applied to the active layer 21. Details are the same as those of the above-described embodiment, and thus will be omitted.

The variable low resistance regions VL1, VL2, and VL3 may include a first variable low resistance region VL1, a second variable low resistance region VL2, and a third variable low resistance region VL3.

The first fluctuating low-resistance region VL1 may have a larger width than the second fluctuating low-resistance region VL2, and the second fluctuating low-resistance region VL2 may have a larger width than the third fluctuating low-resistance region VL3. have. For example, the region surrounded by the first fluctuating low resistance region VL1 has a larger width than the region surrounded by the second fluctuating low resistance region VL2, and the region surrounded by the second fluctuating low resistance region VL2 has a third fluctuation. It may have a larger width than a region surrounded by the low resistance region VL3.

As an optional embodiment, the first fluctuating low-resistance region VL1 is disposed outside the second fluctuating low-resistance region VL2, and the second fluctuating low-resistance region VL2 is the outside of the third fluctuating low-resistance region VL3 Can be placed on

The first fluctuating low-resistance region VL1, the second fluctuating low-resistance region VL2, and the third fluctuating low-resistance region VL3 are regions formed in the active layer 21 and are regions through which current can flow, and have a linear current. Can be formed with

Specifically, the first fluctuating low-resistance region VL1, the second fluctuating low-resistance region VL2, and the third fluctuating low-resistance region VL3 are among the regions of the active layer 21. This is a region in which electrical resistance is lower than that of other regions adjacent to the second low fluctuation resistance region VL2 and the third low fluctuation resistance region VL3.

In addition, after forming the first fluctuating low resistance region VL1, the second fluctuating low-resistance region VL2 and the third fluctuating low-resistance region VL3 through the application electrode 22, Since the polarization state of the active layer 21 is maintained even when the electric field is removed or voltage is removed, the first fluctuating low resistance region VL1, the second fluctuating low resistance region VL2, and the third fluctuating low resistance region (VL3) is maintained, and the state in which the path of the current is formed can be maintained.

Through this, various electronic circuits can be configured. For example, at least a portion of a memory device capable of storing one or more data may be configured.

The variable low resistance regions VL1, VL2, and VL3 have a height HVL, and this height HVL may correspond to the overall thickness of the active layer 21.

The active layer 21 may include first polarization regions 21F1 and 21F3 having a first polarization direction, and the fluctuation low resistance regions VL1, VL2, and VL3 are the boundaries of the first polarization regions 21F1 and 21F3. Can be formed in

In addition, second polarization regions 21R1 and 21R2 having a second polarization direction may be included so as to be adjacent to the first polarization regions 21F1 and 21F3, and the variable low resistance region VL is the second polarization region 21R1. , 21R2). The second direction may be at least different from the first direction, for example, may be a direction opposite to the first direction.

For example, the first variable low resistance region VL1 may be formed between the first polarization region 21F1 and the second polarization region 21R1.

In addition, the second variable low resistance region VL2 may be formed between the first polarization region 21F1 and the second polarization region 21R2.

In addition, the third low-variation resistance region VL3 may be formed between the first polarization region 21F3 and the second polarization region 21R2.

7A to 7D are diagrams for explaining a method of controlling a current path range in relation to the electronic circuit of FIG. 5.

Referring to FIG. 7A, the active layer 21 may include a second polarization region 21R having a second polarization direction. As an alternative embodiment, a polarization state of the active layer 21 as shown in FIG. 7A may be formed by applying an initializing electric field through the application electrode 22.

Then, referring to FIG. 7B, a first polarization region 21F is formed in the active layer 21. As a specific example, the first polarization region 21F is first formed in a region overlapping the application electrode 22 so as to correspond to the width of the application electrode 22 and then grows in a horizontal direction to form a state as shown in FIG. 7B. In addition, the first polarization region 21R of FIG. 7A may be reduced to change to the first polarization region 21R1 of FIG. 7B.

A first variable low resistance region VL1 may be formed between the first polarization region 21F and the second polarization region 21R1.

Then, referring to FIG. 7C, the polarization direction of a portion of the first polarization region 21F is converted into a second polarization region 21R2 having a polarization direction in the second direction by applying an electric field in the opposite direction to that of FIG. 7B. I can. For example, a second polarization region 21R2 having a polarization direction in a second direction opposite to the first polarization direction of the first polarization region 21F may be formed.

In addition, through this, the size of the first polarization region 21F of FIG. 7B is reduced and can be changed to the first polarization region 21F1 of the shape shown in FIG. 7C.

A second variable low resistance region VL2 may be formed between the second polarization region 21R2 and the first polarization region 21F1.

Since the polarization state is maintained, the first fluctuating low resistance region VL1 may be maintained as it is.

Then, referring to FIG. 7D, the polarization direction of a portion of the second polarization region 21R2 is converted into a first polarization region 21F3 having a polarization direction in the first direction by applying an electric field in the opposite direction to that of FIG. 7C. can do. For example, a first polarization region 21F3 having a polarization direction in a first direction opposite to the second polarization direction of the second polarization region 21R2 may be formed.

In addition, through this, the size of the second polarization region 21R2 of FIG. 7C may be reduced to change into the second polarization region 21R2 of the shape shown in FIG. 7D.

A third variable low resistance region VL3 may be formed between the second polarization region 21R2 and the first polarization region 21F3.

Since the polarization state is maintained, the first fluctuating low-resistance region VL1 and the second fluctuating low-resistance region VL2 are maintained as they are, and a third fluctuating low-resistance region VL3 may be added thereto.

In this embodiment, a first polarization region having a first polarization direction different from the second polarization direction is formed in the active layer by applying an electric field to the active layer through the application electrode, and at the boundary between the first polarization region and the second polarization region. A corresponding fluctuation low resistance region can be formed. Such a low-variable resistance region is a region having a low resistance and a region having a reduced resistance, and can be a path of a current, so that an electronic circuit can be easily formed.

In addition, according to the present embodiment, the magnitude of the electric field through the application electrode can be controlled and the direction of the electric field can be controlled, thereby forming a plurality of first polarization regions or a plurality of second polarization regions with respect to the active layer.

A plurality of low-variation resistance regions may be formed at a boundary line between the plurality of first polarization regions or the plurality of second polarization regions. Since each of the plurality of fluctuating low resistance regions can form a path of current, it is possible to easily generate and control electronic circuits of various types and uses.

For example, since the number of variable low-resistance regions can be selectively applied around the applied electrode, various current paths can be formed, and a memory for storing various data according to the current path can be implemented.

8 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line II-II of FIG. 8.

8 and 9, the electronic circuit 100 of the present embodiment may include an active layer 110, an application electrode 120, a variable low resistance region VL, and one or more connection electrode units 131 and 132. have.

The active layer 110 may include a spontaneous polarization material. For example, the active layer 110 may include an insulating material and may include a ferroelectric material. That is, the active layer 110 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment the active layer 110 may comprise a perovskite-based material, for example, it may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

In addition, as another example, the active layer 110 has an ABX3 structure, where A may include one or more materials selected from inorganic materials such as Cs, Ru, etc., capable of forming a CnH2n+1 alkyl group, and a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the active layer 110 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _3, CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _{1-y PbCl x} Br _3-x (0≤x, y≤1) can do.

Since the active layer 110 may be formed by using various other ferroelectric materials, descriptions of all examples thereof will be omitted. In addition, when the active layer 110 is formed, the ferroelectric material may be doped with various other materials to include an additional function or to improve electrical characteristics.

The active layer 110 has spontaneous polarization, and the degree and direction of polarization can be controlled according to the application of an electric field. In addition, the active layer 110 may maintain a polarized state even when the applied electric field is removed.

The application electrode 120 may be formed to apply an electric field to the active layer 110, and for example, a voltage may be applied to the active layer 110.

As an alternative embodiment, the application electrode 120 may be formed to be in contact with the upper surface of the active layer 110.

In addition, the application electrode 120 may apply voltages of various sizes to the active layer 110 and may be formed to control a voltage application time.

As an alternative embodiment, the application electrode 120 may be a gate electrode.

For example, the application electrode 120 may be electrically connected to a power source (not shown) or a power control unit.

The application electrode 120 may include various materials, and may include a material having high electrical conductivity. For example, the application electrode 120 may be formed using various metals.

For example, the application electrode 120 may be formed to contain aluminum, chromium, titanium, tantalum, molybdenum, tungsten, neodymium, scandium, or copper. Alternatively, it may be formed using an alloy of these materials, or may be formed using a nitride of these materials.

In addition, as an optional embodiment, the application electrode 120 may include a laminate structure.

The connection electrode units 131 and 132 may include one or more electrode members, for example, a first connection electrode member 131 and a second connection electrode member 132.

The connection electrode portions 131 and 132 may be formed on the active layer 110, for example, may be formed to be spaced apart from the application electrode 120 on the upper surface of the active layer 110, and as an alternative embodiment, the active layer 110 ) Can be formed to contact.

The first connection electrode member 131 and the second connection electrode member 132 may be formed using various conductive materials. For example, the first connection electrode member 131 and the second connection electrode member 132 may be formed to contain aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten.

As an optional embodiment, the first connection electrode member 131 and the second connection electrode member 132 may include a structure in which a plurality of conductive layers are stacked.

As an optional embodiment, the first connection electrode member 131 and the second connection electrode member 132 may be formed using a conductive metal oxide, for example, indium oxide (eg, In ₂ O ₃ ), tin oxide. (E.g. _{SnO 2} ), zinc oxide (e.g. ZnO), indium tin oxide alloy (e.g. In ₂ O _{3 -SnO 2} ) or indium zinc oxide alloy (e.g. In ₂ O ₃ -ZnO) Can be formed.

As an alternative embodiment, the connection electrode units 131 and 132 may be terminal members including input/output of electrical signals.

In addition, as a specific example, the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode units 131 and 132 may include a source electrode or a drain electrode.

10 to 14 are diagrams for explaining the operation of the electronic circuit of FIG. 8.

10 is a diagram showing a state in which a first electric field is applied through the application electrode 120, FIG. 11 is a cross-sectional view taken along lines VIII-VIII of FIG. 10, and FIG. 12 is an enlarged view of K of FIG. 11 to be.

10 to 14, when a first electric field is applied to the active layer 110 through the application electrode 120, at least one region of the active layer 110 may include a polarization region 110F.

The polarization region 110F may have a shape surrounding the application electrode 120 around the application electrode 120. The polarization region 110F may have a boundary line.

The first low fluctuation resistance region VL1 may be formed in a region corresponding to the side of the boundary line. Referring to FIG. 10, the application electrode 120 may be formed in a linear shape surrounding the application electrode 120.

For example, the first variable low resistance region VL1 may have a first width WVL1 in one direction so as to surround the application electrode 120.

In addition, the first variable low-resistance region VL1 may be formed to correspond to the entire side surface of the boundary line of the polarization region 110F, and may have a thickness TVL1 in a direction away from the side surface of the polarization region 110F.

As an optional embodiment, this thickness (TVL1) may be 0.1 to 0.3 nanometers.

As an alternative embodiment, a process of applying an initialization electric field to the active layer 110 before the first voltage is applied to the active layer 110 through the application electrode 120 may be performed.

The process of applying such an initializing electric field to the active layer 110 may include converting all regions of the active layer 110 to polarization in a direction different from that of the polarization region 110F, for example, a polarization region in the opposite direction. .

Then, the polarization region 110F may be formed in one region by applying an electric field in the opposite direction.

The first variable low resistance region VL1 formed at the boundary of the polarization region 110F of the active layer 110 may be changed to a region having a lower resistance than other regions of the active layer 110. For example, the first low fluctuation resistance region VL1 may have a lower resistance than the polarization region 110F of the active layer 110 and the active layer 110 surrounding the first fluctuation low resistance region VL1.

Through this, the first fluctuating low resistance region VL1 may form a current path.

As an alternative embodiment, the first variable low resistance region VL1 may correspond to a region of a plurality of domain walls provided in the active layer 110.

In addition, the first fluctuating low resistance region VL1 may be maintained as long as the polarization state of the polarization region 110F of the active layer 110 is maintained. That is, even when the first voltage applied to the active layer 110 through the application electrode 120 is removed, the state of the variable low resistance region VL1, that is, the low resistance state may be maintained.

As shown in FIGS. 10 and 11, a current path may be formed through the first fluctuating low resistance region VL1. However, since the connection electrode portions 131 and 132 do not correspond to the first fluctuating low resistance region VL1, current flow through the connection electrode portions 131 and 132 may not occur.

FIG. 13 is a diagram illustrating a state in which the first electric field is further maintained for a predetermined period of time through the application electrode 120, and FIG. 14 is a cross-sectional view taken along line XI-XI of FIG. 13.

13 and 14, the holding time of the first electric field through the application electrode 120 increases, so that the polarization region 110F of FIGS. 10 and 11 moves in the horizontal direction, thereby increasing the polarization region 110F. A second low fluctuation resistance region VL2 larger than the first low fluctuation resistance region VL1 may be formed.

For example, by continuously maintaining the voltage applied in FIGS. 10 and 11 for a predetermined period of time, a structure as shown in FIGS. 13 and 14 may be formed.

The polarization region 110F may have a shape surrounding the application electrode 120 around the application electrode 120. The polarization region 110F may have a boundary line. The second low fluctuation resistance region VL2 may be formed in a region corresponding to a side surface of the boundary line of the polarization region 110F. Referring to FIG. 13, the application electrode 120 may be formed in a linear shape surrounding the application electrode 120.

For example, the second variable low resistance region VL2 may have a second width WVL2 in one direction to surround the applied electrode 120, and the second width WVL2 is greater than the first width WVL1. I can. That is, the second fluctuation low-resistance region VL2 can circumscribe the application electrode 120.

In addition, the second fluctuating low resistance region VL2 may be formed to correspond to the entire side of the boundary line of the polarization region 110F, and may have a thickness in a direction away from the side of the polarization region 110F, and an optional embodiment As such, the thickness may be 0.1 to 0.3 nanometers.

The second variable low-resistance region VL2 formed at the boundary of the polarization region 110F of the active layer 110 may be changed to a region having a lower resistance than other regions of the active layer 110. For example, the second low variable resistance region VL2 may have a lower resistance than the region of the active layer 110 around the polarized region 110F of the active layer 110 and the second low variable resistance region VL2. That is, the resistance of the second low fluctuation resistance region VL2 is lower than the resistance of the inner portion of the second low fluctuation resistance region VL2 of the polarization region 110F. In addition, the resistance of the second low fluctuation resistance region VL2 may be lower than the resistance of the outer portion of the second low fluctuation resistance region VL2 of the active layer 110.

Through this, the second fluctuation low resistance region VL2 may form a current path.

As an alternative embodiment, the second variable low resistance region VL2 may correspond to a region of a plurality of domain walls provided in the active layer 110.

In addition, the second fluctuating low resistance region VL2 may be maintained as long as the polarization state of the active layer 110 is maintained. That is, even when the second voltage applied to the active layer 110 through the application electrode 120 is removed, the state of the second fluctuating low resistance region VL2, that is, the low resistance state may be maintained.

Therefore, a current path may be formed through the second fluctuation low resistance region VL2.

In addition, as a specific example, the connection electrode portions 131 and 132 are formed to correspond to the second variable low resistance region VL2, for example, the first connection electrode member 131 of the connection electrode portions 131 and 132 and The second connection electrode members 132 may be disposed to be in contact with the upper surface of the second variable low resistance region VL2 while being spaced apart from each other.

Through this, current may flow through the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode units 131 and 132.

In addition, various electrical signals may be generated. For example, when the electric field in the states of FIGS. 13 and 14 is more continuously applied, that is, when the application time increases, the second fluctuating low resistance region VL2 further moves and 2 It may escape from the connection electrode member 132. Accordingly, current may not flow through the first connection electrode member 131 and the second connection electrode member 132.

In addition, as an optional embodiment, an initialization process for the entire active layer 110 may be performed.

Then, when an electric field is applied to the active layer 110 through the application electrode 120 again, current flows through the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode units 131 and 132. I can.

In the electronic circuit of the present embodiment, voltages of various sizes can be applied to the active layer through the application electrode, and the applied time can be controlled.

Through this, a polarization region may be formed in the active layer with a region having a desired size, and a variable low resistance region may be formed at the boundary of the polarization region.

When the connection electrode part is formed to correspond to such a fluctuating low resistance region, for example, to make contact, current may flow through the connection electrode part, and even if the voltage is removed, the active layer containing the ferroelectric material may maintain a polarized state. The fluctuating low-resistance region of the boundary can also be maintained, so that current can continue to flow.

In addition, a voltage may be applied to the active layer through the application electrode so that the variable low-resistance region is changed into a polarization region, and the current does not flow through the connection electrode portion through which the current flows.

By controlling the voltage of the applied electrode, the flow of current can be controlled, and the electronic circuit can be used for various purposes through the control of the current flow.

As an alternative embodiment, the electronic circuit can be used as a memory.

For example, it can be used as a memory by defining the flow of current as 1 and not flowing as 0, and as a specific example, since current can flow even when the voltage is removed, it can also be used as a nonvolatile memory.

In addition, the electronic circuit may constitute a circuit unit that generates and transmits various signals, and may be used as a switching element.

In addition, since it can be applied in a simple structure to other parts requiring control of electrical signals, it can be applied to various fields such as variable circuits, CPUs, and biochips.

15 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along line V-V of FIG. 15.

Referring to FIGS. 15 and 16, the electronic circuit 200 of the present embodiment may include an active layer 210, an application electrode 220, a variable low resistance region VL, and connection electrode portions 231 and 232.

For convenience of explanation, the description will focus on differences from the above-described embodiment.

The active layer 210 may include a spontaneous polarization material. For example, the active layer 210 may include an insulating material and may include a ferroelectric material. That is, the active layer 210 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

A description of the material for forming the active layer 210 is the same as described in the above-described embodiment or can be applied by modifying it, and thus a detailed description thereof will be omitted.

The application electrode 220 may be formed to apply an electric field to the active layer 210, and for example, a voltage may be applied to the active layer 210.

As an alternative embodiment, the application electrode 220 may be formed to be in contact with the upper surface of the active layer 210.

The description of the material forming the application electrode 220 is the same as described in the above-described embodiment or can be applied by modifying it, and thus a detailed description thereof will be omitted.

The connection electrode parts 231 and 232 may include one or more electrode members, for example, a first connection electrode member 231 and a second connection electrode member 232.

The connection electrode portions 231 and 232 may be formed on the active layer 210, for example, on a surface of the active layer 210 opposite to the surface on which the application electrode 220 is formed so as to be spaced apart from the application electrode 220. Can be formed.

The application electrode 220 may be formed on the upper surface of the active layer 210, and the connection electrode portions 231 and 232 may be formed on the lower surface of the active layer 210.

As an alternative embodiment, the connection electrode portions 231 and 232 may be formed to contact the active layer 210.

The first connection electrode member 231 and the second connection electrode member 232 may be formed using various conductive materials.

A description of the material for forming the first connection electrode member 231 and the second connection electrode member 232 is the same as described in the above-described embodiment, or may be modified and applied, so a detailed description thereof will be omitted.

Referring to FIG. 16, when a voltage is applied to the active layer 210 through the application electrode 220, at least one region of the active layer 210 may include a polarization region 210F.

The variable low resistance region VL may be formed in a region corresponding to the side of the boundary line of the polarization region 210F, and referring to FIG. 15, a linear region surrounding the application electrode 220 with the application electrode 220 as a center. It can be formed as

For example, the variable low resistance region VL2 may have a width in one direction so as to surround the application electrode 220.

In addition, the fluctuation low resistance region VL may be formed to correspond to the entire side of the boundary line of the polarization region 210F, and may have a thickness in a direction away from the side surface of the polarization region 210F. The thickness may be 0.1 to 0.3 nanometers.

The variable low resistance region VL formed at the boundary of the polarization region 210F of the active layer 210 may be changed to a region having a lower resistance than other regions of the active layer 210. For example, the variable low resistance region VL may have a lower resistance than the polarization region 210F of the active layer 210 and the region of the active layer 210 surrounding the variable low resistance region VL.

Through this, the fluctuation low resistance region VL may form a current path.

As an alternative embodiment, the variable low resistance region VL may correspond to a region of a plurality of domain walls provided in the active layer 210.

In addition, this variable low resistance region VL may be maintained continuously as long as the polarization state of the active layer 210 is maintained. That is, even when the voltage applied to the active layer 210 through the application electrode 220 is removed, the state of the variable low resistance region VL, that is, the low resistance state may be maintained.

A current path may be formed through the fluctuation low resistance region VL.

In addition, as a specific example, the connection electrode portions 231 and 232 are formed to correspond to the variable low resistance region VL, for example, the first connection electrode member 231 and the second connection of the connection electrode portions 231 and 232 The electrode members 232 may be disposed to be in contact with the lower surface of the variable low resistance region VL while being spaced apart from each other.

Through this, current may flow through the first connection electrode member 231 and the second connection electrode member 232 of the connection electrode units 231 and 232.

In the electronic circuit of the present embodiment, voltages of various sizes can be applied to the active layer through the application electrode, and the applied time can be controlled.

Through this, a polarization region may be formed in the active layer with a region having a desired size, and a variable low resistance region may be formed at the boundary of the polarization region.

In addition, by forming an application electrode on one surface of the active layer and a connection electrode on the other surface, precise patterning and miniaturization of the electronic circuit can be easily performed.

The electronic device as described above may be implemented as a variable low-resistance memory device as follows.

17 is a schematic plan view illustrating a memory device according to another embodiment of the present invention, and FIG. 18 is a cross-sectional view taken along line VI-VI of FIG. 17.

17 and 18, the variable low resistance memory device 300 may include a base 310, a gate 320, a source 331 and a drain 332.

The base 310 may include the above-described active layer material, for example, a spontaneous polarization material. For example, the base 310 may include an insulating material and may include a ferroelectric material. That is, the base 310 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment the base unit 310 may comprise a perovskite-based material, for example, it may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

In addition, as another example, the base 310 has an ABX3 structure, where A may include one or more materials selected from inorganic materials such as Cs, Ru, etc., capable of forming a CnH2n+1 alkyl group, and a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the base 310 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _3, CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _{1-y PbCl x} Br _3-x (0≤x, y≤1) can do.

The base 310 may be formed using various other ferroelectric materials, and descriptions of all examples thereof will be omitted. In addition, when the base 310 is formed, the ferroelectric material may be doped with various other materials to include an additional function or to improve electrical characteristics.

The base 310 has spontaneous polarization, and the degree and direction of polarization can be controlled according to the application of an electric field. In addition, the base 310 may maintain a polarized state even when the applied electric field is removed.

The base 310 may include a first region 311 and a second region 312 positioned adjacent to each other in the X-Y plane direction. The first region 311 may have a polarization in a first direction, and the first direction is a thickness direction of the base 310, that is, a direction in which the first region 311 and the second region 312 are disposed It may be a Z-direction perpendicular to.

The second region 312 is positioned adjacent to the first region 311 in a direction perpendicular to the thickness, that is, in the XY plane direction, and the second region 312 is selectively disposed opposite to the first direction. It can have polarizations arranged in two directions.

A gate 320 may be positioned on the second region 312. Although not shown in the drawing, the gate 320 may be connected to a separate device to receive a gate signal.

The polarization of the second region 312 in a direction opposite to that of the first region 311 can be achieved by a voltage applied to the gate 320.

In this way, a variable low resistance region 340 may be formed between the first region 311 and the second region 312 having polarizations in opposite directions. The variable low-resistance region 340 as described above becomes a region having a very small resistance compared to the first region 311 and/or the second region 312, and a current flow may be formed through this region.

The fluctuation low resistance region 340 may be formed according to the following exemplary embodiment.

First, the base 310 including the spontaneous polarization material may have a polarization in the first direction as a whole. The entire base 310 is not limited to having polarization in the first direction, and at least a predetermined area of the base 310 facing the gate 320 may have polarization in the first direction. Optionally, such a first direction polarization may be formed by applying an initializing electric field to the gate 320.

In this state, as a first voltage is applied to the gate 320 for a first time and an electric field is applied to the base 310 through the gate 320, a certain area facing the gate 320 is polarized in the second direction. Changes. The electric field applied to the gate 320 to change the direction of polarization can be adjusted by the first voltage, that is, the first voltage so that an electric field greater than the coercive electric field of the spontaneous polarization material forming the base 310 is applied. Can be added.

The base 310 may have a first thickness t1. In this case, the second region 312 is formed over the entire first thickness t1, and the magnitude of the first voltage applied to the gate 320 may be adjusted according to the first thickness t1. According to an embodiment, the first thickness t1 and the magnitude of the first voltage applied to the gate 320 may be proportional. That is, when the first thickness t1 is thick, the first voltage can be increased.

As can be seen in FIG. 18, the variable low resistance region 340 may also be formed over the entire first thickness t1.

The area of the second region 312 formed in this way may be determined in proportion to the first time when the first voltage is applied to the gate 320.

Therefore, in order to form the second region 312 having a desired area and/or size, an appropriate gate voltage and time for the ferroelectric material, and the first thickness t1 of the second region 312 are tested and/or calculated. Can be determined in advance by

When the polarization direction of the second region 312 changes from the first direction to the second direction, the gap between the first region 311 having polarization in the first direction and the second region 312 having polarization in the second direction A fluctuating low-resistance region 340 having a predetermined width may be formed in FIG. The variable low resistance region 340 may be formed around the gate 320.

19 is a graph showing a voltage and current relationship between a first region and a low fluctuation resistance region.

Specifically, FIG. 19 shows a state in which the current changes as the voltage increases in the first region and the variable low resistance region.

That is, in FIG. 19, (a) shows a state in which the current changes as the voltage increases in the fluctuating low resistance region, and (b) shows the state in which the current changes as the voltage increases in the first region.

Since the variable low resistance region 340 has a very small resistance compared to the first region 311, it can be seen that the flow of current smoothly occurs according to the application of voltage.

The variable low resistance region 340 formed as described above may not be erased even after time passes.

The source 331 and the drain 332 are positioned so as to contact the variable low resistance region 340 formed in this way. In this case, a current may flow from the source 331 to the drain 332 through the variable low resistance region 340. Therefore, data can be written at this time, and can be read as 1, for example.

Optionally, the polarization direction of the second region 312 may be erased by making the polarization direction of the second region 312 again equal to the polarization direction of the first region 311 by the voltage applied to the variable low resistance region 340 and the gate 320.

That is, by applying the second voltage to the gate 320, the polarization direction of the second region 312 may be set to the first direction again. Thereafter, the second voltage is maintained for a second time to grow a region whose polarization changes in the first direction in a planar direction, and the region whose polarization is changed in the first direction passes through the fluctuation low resistance region 340 When extending to the region 311, the fluctuating low resistance region 340 may disappear. In this case, a current cannot flow from the source 331 to the drain 332, and thus data can be erased at this time, and read as zero.

In this case, the second voltage may be a voltage different from the first voltage, and may be a voltage having the same magnitude as the first voltage according to an exemplary embodiment and a polarity opposite to that of the first voltage. The second time may be at least the first time or longer.

The variable low-resistance region memory device formed as described above can be used as a nonvolatile memory device because the above-described variable low-resistance region 340 can maintain its state even when power to the gate 320 is turned off.

Since the variable low-resistance region memory device can ^{write/erase about 10 12} times, it can have a memory life of ^{about 10 7} times that of a conventional semiconductor device-based memory device.

As for the memory speed, the variable low-resistance region memory device may be about 10 ^-9 sec, and thus the memory speed may be increased by ^{about 10 6} times compared to that of a conventional semiconductor device-based memory device.

As described above, the variable low-resistance region memory device can be a memory device having very excellent speed and lifetime.

In addition, since the position at which the variable low resistance region 340 is formed can be adjusted according to the gate voltage and/or application time, it is possible to design various memory devices and to be thinner compared to conventional ferroelectric memory devices using ferroelectrics. Can be achieved. In addition, there is an advantage in that the degree of integration of the device can be increased because the degree of freedom in memory design is increased.

The variable low resistance region 340 formed in this way may be formed in a closed loop shape around the gate 320 as shown in FIG. 17, and the source 331 and the drain 332 are partially formed on the closed loop. By arranging, there may be two lines connecting the source 331 and the drain 332. However, the present invention is not limited thereto, and if a gate is positioned on one side of the base in a plane direction and a source and a drain adjacent to the other two sides are disposed, the variable low resistance region may become a single line connecting the source and the drain.

The source 331 and the drain 332 as described above may be an electrode structure formed by patterning on the base 310, but the present invention is not necessarily limited thereto, and although not shown in the drawing, the base 310 The variable low resistance region 340 may be contacted through a via hole formed in the covering insulating layer.

20 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 2, in the variable low-resistance region memory device 400, a source 431 and a drain 432 are formed on a substrate 430, and a base 410 including a spontaneous polarization material on a substrate 430. ) Can be placed. The substrate 430 may be formed of a semiconductor wafer or, according to an embodiment, a silicon wafer. In addition, the source 431 and the drain 432 may be formed on a wafer by ion doping. Of course, although not shown in the drawing, an external signal line may be connected to the source 431 and the drain 432 through separate vias.

In this structure, the gate voltage and the application time may be determined so that the variable low resistance region 440 may be positioned corresponding to the regions of the source 431 and the drain 432 formed on the substrate 430.

The substrate 430 and the base 410 as described above may be bonded to each other by a separate adhesive layer, but the present invention is not limited thereto, and the base 410 may be formed on the substrate 430. By implementing the base 410 as a thin film on the substrate 430 in this way, the memory device 400 can be further thinned, and an existing memory device process can be used to further increase the efficiency of the manufacturing process.

In the above-described embodiments, the first region and the second region have the same thickness, but the present invention is not limited thereto.

21 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 21, in the variable low-resistance region memory device 500, a source 531 and a drain 532 are formed on a substrate 530, and a base 510 including a spontaneous polarization material on a substrate 530. ) Can be placed. In the memory device 500 of the embodiment shown in FIG. 21, the first region 511 may have a second thickness t2 that is thicker than the first thickness t1 of the second region 512. The second thickness t2 becomes a thickness at which the polarization direction is not switched by the voltage applied to the gate 520, and accordingly, the variable low resistance region 540 has a first thickness t1 and a second thickness ( It can be formed at a location that becomes the boundary of t2).

As described above, since the voltage applied to the gate 520 can be set as a voltage at which polarization switching is performed with respect to the first thickness t1, by creating a region formed with the second thickness t2 on the base 510 , The fluctuating low-resistance region 540 is not formed in the second thickness t2 even according to the intensity and time of the voltage applied to the gate 520, and only the fluctuating low-resistance region 540 is formed in the region of the first thickness t1. ) Can be formed.

That is, as shown in FIG. 21, the variable low resistance region 540 may be formed at a position that becomes a boundary between the first thickness t1 and the second thickness t2.

22 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 22, in the variable low-resistance region memory device 600, a source 631 and a drain 632 are formed on a substrate 630, and a base 610 including a spontaneous polarization material on a substrate 630. ) Can be placed. The memory device 600 of the embodiment illustrated in FIG. 22 also has a second thickness t2 in which the first region 611 is thicker than the first thickness t1 of the second region 612 as in the embodiment shown in FIG. 21. Can have.

At this time, depending on the time when the voltage is applied to the gate 620, as shown in FIG. 22, it is located inside the first thickness t1 from the boundary between the first thickness t1 and the second thickness t2. can do. Accordingly, in the memory device 600 having this structure, the source 631 and the drain 632 may be formed inside the boundary between the first thickness t1 and the second thickness t2. Accordingly, even if the formation position of the fluctuating low-resistance region 640 is changed according to the change of the strength and/or the time of the gate 620 voltage, the fluctuating low-resistance region 640 and the source 631/drain 632 are Can be electrically connected.

In the above-described embodiments, the gate is formed adjacent to the base, but the present invention is not limited thereto.

23 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 23, in the memory device 700, another layer 750 may be further positioned between the base 710 and the gate 720. The layer 750 may be an insulating layer, but may be a material different from the ferroelectric material forming the base 710.

Even in this case, the polarization direction of the second region 712 can be switched under the influence of the electric field caused by the voltage applied to the gate 720, and at this time, the voltage of the gate 720 and/or the polarization direction can be switched. Alternatively, the time can be obtained by experimentation and/or calculation in advance.

24 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 24, in the variable low-resistance region memory device 800, a source 831 and a drain 832 are formed on a substrate 830, and a base 810 including a spontaneous polarization material on a substrate 830. ) Can be placed.

According to the embodiment shown in FIG. 24, a first gate 821 facing the base 810 and a second gate 822 positioned opposite to the first gate 821 around the base 810 are included. can do.

In this case, the variable low resistance region 840 may be formed by switching the polarization direction of the second region 812 by the first gate 821. This makes it possible to write data.

By switching the polarization direction of the second region 812 by the second gate 822 again as in the first region 811, the variable low resistance region 840 may be removed. This makes it possible to erase data.

In this way, data can be read at 0/1 by the first gate 821 and the second gate 822.

It goes without saying that all the embodiments of the present specification described above are not limited to the illustrated embodiments, and may be applied in combination with each other.

In addition, of course, these embodiments can be selectively applied or modified and applied to the embodiments to be described later.

25 to 27 are diagrams for explaining a variable low resistance region memory device according to another embodiment of the present invention.

First, referring to FIG. 25, the variable low resistance memory device 900 may include a base 910, a gate 920, a source 931, and a drain 932.

The base 910 may include the above-described active layer material, for example, a spontaneous polarization material. For example, the base 910 may include an insulating material and may include a ferroelectric material. That is, the base 910 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment the base unit 910 may comprise a perovskite-based material, for example, it may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

In addition, as another example, the base 910 has an ABX3 structure, where A may include one or more materials selected from inorganic materials such as Cs, Ru, etc., capable of forming a CnH2n+1 alkyl group, and a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. A specific example is the same as described in the above-described embodiment, and thus will be omitted.

The base 910 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the base 910 may maintain a polarized state even when the applied electric field is removed.

A gate 920 may be positioned on the base 910.

The base 910 including the active layer material by application of a voltage through the gate 920 may include a first region that is a polarization region in one direction around the gate 920, and is adjacent to the first region and A second region having a polarization direction different from the polarization direction of the first region may be included. Since the contents of the first area and the second area are similar to those described in the above-described embodiments, detailed descriptions are omitted.

In this way, a first low-variation resistance region 941 may be formed between the first region and the second region having polarizations in opposite directions. The properties of the first fluctuating low-resistance region 941 are the same as those of the fluctuating low-resistance region described in the foregoing embodiments. As shown in FIG. 25, when viewed from a direction perpendicular to the base 910, the first fluctuating low-resistance region 941 is spaced apart from the gate 920 to round the gate 920.

In this case, the size of the first region may be controlled by controlling the first voltage, and one end of the first fluctuating low resistance region 941 may be connected to the source 931 and the other end to the drain 932. .

In this case, a current may flow from the source 931 to the drain 932 through the first fluctuating low resistance region 941.

For example, the first fluctuating low-resistance region 941 may have a shape similar to a part of a rectangle, and a source 931 is formed to overlap one side of the rectangle, and a drain 932 is formed on the other side. Can be.

As an alternative embodiment, the first variable low-resistance region 941 may have a shape similar to a quadrangle, and the source 931 and the drain 932 may be formed to overlap the two opposite sides of the quadrangle.

Also, referring to FIG. 26, it is shown that a second low-variable resistance region 942 is formed inside the first low-variable resistance region 941 with respect to the gate 920. The properties of the second variable low resistance region 942 are the same as those of the variable low resistance region described in the above-described embodiments. As shown in FIG. 26, when viewed from a direction perpendicular to the base 910, the second fluctuating low-resistance region 942 is spaced apart from the gate 920 to round the gate 920.

One end of the second variable low resistance region 942 may be connected to the source 931 and the other end to the drain 932.

For example, the second fluctuating low-resistance region 942 may have a shape similar to a part of a rectangle smaller than the first fluctuating low-resistance region 941, and the source 931 is formed so as to overlap one side of the rectangle. , A drain 932 may be formed on one side different from the one.

As an alternative embodiment, the second variable low resistance region 942 may have a shape similar to a quadrangle, and the source 931 and the drain 932 may be formed to overlap the two opposite sides of the quadrangle.

Since the second fluctuating low-resistance region 942 is formed inside the first fluctuating low-resistance region 941, current flows from the source 931 to the drain 932 through the first fluctuating low-resistance region 941 The length of may be greater than the length of the current flow from the source 931 to the drain 932 through the second variable low resistance region 942.

The first fluctuating low-resistance region 941 and the second fluctuating low-resistance region 942 may be formed as a path of a linear current, and specifically, a first fluctuating low-resistance region 941 and a second fluctuating low-resistance region Reference numeral 942 is an area in which electrical resistance is lower than that of other adjacent areas.

The process of forming the first variable low resistance region 941 and the second variable low resistance region 942 may be applied in the same or similar manner as described in FIGS. 7A to 7D of the above-described embodiment.

For example, by applying a voltage to the base 910 through the gate 920, a polarization state may be formed, and through this, a first fluctuating low resistance region 941 may be formed. Then, by applying an electric field in the opposite direction, a second low variable resistance region 942 spaced apart from the first low variable resistance region 941 may be formed.

In addition, since the polarization state is maintained even when the voltage is removed from the gate 920, the first variable low resistance region 941 and the second variable low resistance region 942 may be maintained as they are.

As an alternative embodiment, the source 931 may be formed to be connected to both the first variable low resistance region 941 and the second variable low resistance region 942. For example, the source 931 may have a structure elongated along one direction, and as a specific example, may be elongated along a direction away from the gate 920.

In addition, the drain 932 may be formed to be connected to both the first variable low resistance region 941 and the second variable low resistance region 942. For example, the drain 932 may have a structure elongated along one direction, and as a specific example, may be elongated along a direction away from the gate 920.

The source 931 and the drain 932 may have a structure formed on both sides with the gate 920 interposed therebetween.

The variable low-resistance region memory element formed as described above can be used as a nonvolatile memory element because the variable low-resistance regions 941 and 942 can maintain their state even when the power to the gate 920 is turned off, as described above.

Since the variable low-resistance region memory device can ^{write/erase about 10 12} times, it can have a memory life of ^{about 10 7} times that of a conventional semiconductor device-based memory device.

As for the memory speed, the variable low-resistance region memory device may be about 10 ^-9 sec, and thus the memory speed may be increased by ^{about 10 6} times compared to that of a conventional semiconductor device-based memory device.

As described above, the variable low-resistance region memory device can be a memory device having very excellent speed and lifetime.

In addition, through the control of the electric field through the gate 920, only the first fluctuating low-resistance region 941 is formed, or both the first fluctuating low-resistance region 941 and the second fluctuating low-resistance region 942 are formed. You can control it.

On the other hand, when a current flows between the source 931 and the drain 932, the current value when only the first fluctuation low resistance region 941 is formed is the first fluctuation low resistance region 941 and the second fluctuation low resistance region 941. The resistance region 942 may be different from the current value when both are formed and may be small, for example.

Through this, the memory device 900 can store not only two pieces of information, for example, 1 or 0, but also store more than four pieces of information, and these may be referred to as 0, 1, 2, and 3, respectively, for convenience. .

That is, as shown in FIG. 26, a case where a current flow between the source 931 and the drain 932 is formed through the first variable low resistance region 941 and the second variable low resistance region 942 may be referred to as three.

As shown in FIG. 25, when only the first fluctuating low-resistance region 941 is generated, a case in which a current flow between the source 931 and the drain 932 is formed through the first fluctuating low-resistance region 941 may be referred to as 1. .

In addition, referring to FIG. 27, by controlling the size of the polarization region through voltage control through the gate 920, the size of the first region may be formed to reach the second fluctuation low resistance region 942, and this Throughout, only the second fluctuating low-resistance region 942 is formed, and the first fluctuating low-resistance region 941 is not generated.

If the first low fluctuation resistance region 941 is formed, the second low fluctuation resistance region 942 may be formed after removing the first low fluctuation resistance region 941 through initialization. For example, the first fluctuating low-resistance region 941 may be extinguished through control of voltage application through the gate 920. This can be done by expanding the first area to the edge, and as another example, converting the first area into a second area, that is, by applying an electric field in the opposite direction.

A current flow between the source 931 and the drain 932 may be formed through the second variable low resistance region 942.

Since the second fluctuating low-resistance region 942 is formed inside the first fluctuating low-resistance region 941, current flows from the source 931 to the drain 932 through the second fluctuating low-resistance region 942 The length of may be smaller than the length of the current flow from the source 931 to the drain 932 through the first fluctuating low resistance region 941.

The length of the current flow can be a resistance to the current from the source 931 to the drain 932, and it can be said that the resistance increases as the length of the current flow from the source 931 to the drain 932 increases. have.

Therefore, the measured value of the current from the source 931 to the drain 932 through the second fluctuating low-resistance region 942 is from the source 931 to the drain 932 through the first fluctuating low-resistance region 941. May be greater than the measured value of the current.

Therefore, when only the second fluctuating low-resistance region 942 is generated as shown in FIG. 27, a case in which a current flow between the source 931 and the drain 932 is formed through the second fluctuating low-resistance region 942 can be referred to as 2. have.

In addition, a case where the first and second fluctuating low resistance regions 941 and 942 disappear due to voltage control through the gate 920 and no current flow between the source 931 and the drain 932 is formed is referred to as 0. I can.

That is, since the first variable low resistance region 941 and the second low fluctuation resistance region 942 can be formed by controlling the gate 920, the first low fluctuation resistance region 941 and the second low fluctuation resistance region 942 are formed. A memory can be formed as four different pieces of information by measuring the current according to the control of the resistance region 942.

Therefore, when a single low-resistance region is used in the design of a memory device, two pieces of information of 0 and 1 can be stored, and when the number of low-resistance regions is increased to n, at least n+1 pieces of information can be stored. Through this, it is possible to easily provide a memory device design capable of integrating more information.

Through this, the degree of freedom in memory design is increased, and high information can be accumulated.

28 to 34 are diagrams for describing a variable low resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 28, the variable low resistance memory device 1000 may include a base 1010, a gate 1020, a source 1031, and a drain 1032.

The base 1010 may include the above-described active layer material, for example, a spontaneous polarization material. For example, the base 1010 may include an insulating material and may include a ferroelectric material. That is, the base 1010 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

Base 1010, as an alternative embodiment may comprise a perovskite-based material, for example, may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

In addition, as another example, the base 1010 has an ABX3 structure, where A may include one or more materials selected from inorganic materials such as Cs, Ru, etc., capable of forming a CnH2n+1 alkyl group, and a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. A specific example is the same as described in the above-described embodiment, and thus will be omitted.

The base 1010 has spontaneous polarization, and the degree and direction of polarization can be controlled according to the application of an electric field. In addition, the base 1010 may maintain a polarized state even when the applied electric field is removed.

A gate 1020 may be positioned on the base 1010.

The base 1010 including the active layer material by application of a voltage through the gate 1020 may include a first region that is a polarization region in one direction around the gate 1020, and is adjacent to the first region and A second region having a polarization direction different from the polarization direction of the first region may be included. Details of the first area and the second area may be formed similarly to those described in the above-described embodiments, and a detailed description thereof will be omitted.

In this way, a first low fluctuation resistance region 1041 may be formed between the first region and the second region having polarizations in opposite directions.

In this case, the size of the first region may be controlled by controlling the first voltage, and one end of the first fluctuating low resistance region 1041 may be connected to the source 1031 and the other end to the drain 1032. .

In this case, a current may flow from the source 1031 to the drain 1032 through the first variable low resistance region 1041.

For example, the first fluctuating low-resistance region 1041 may have a shape similar to a part of a square, and a source 1031 is formed to overlap one side of the square, and a drain 1032 is formed on the other side. Can be.

As an alternative embodiment, the first variable low-resistance region 1041 may have a shape similar to a quadrangle, and the source 1031 and the drain 1032 may be formed so as to overlap on two opposite sides of the quadrangle.

In addition, referring to FIG. 29, the size of the polarization region is controlled through voltage control through the gate 1020, and the size of the first region can be formed to reach the second fluctuation low resistance region 1042, and this Throughout, only the second fluctuating low-resistance region 1042 is formed, and the first fluctuating low-resistance region 1041 is not generated.

If the first low fluctuation resistance region 1041 is formed, the second low fluctuation resistance region 1042 may be formed after removing the first low fluctuation resistance region 1041 through initialization. For example, the first fluctuating low-resistance region 1041 may be extinguished through control of voltage application through the gate 1020. This can be done by expanding the first area to the edge, and as another example, converting the first area into a second area, that is, by applying an electric field in the opposite direction.

A current flow between the source 1031 and the drain 1032 may be formed through the second variable low resistance region 1042.

Since the second fluctuating low-resistance region 1042 is formed inside the first fluctuating low-resistance region 1041, the flow of current from the source 1031 to the drain 1032 through the second fluctuating low-resistance region 1042 The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the first fluctuating low resistance region 1041.

The length of the current flow can be a resistance to the current from the source 1031 to the drain 1032, and it can be said that the resistance increases as the length of the current flow from the source 1031 to the drain 1032 increases. have.

Therefore, the measured value of the current from the source 1031 to the drain 1032 through the second fluctuating low-resistance region 1042 is from the source 1031 to the drain 1032 through the first fluctuating low-resistance region 1041. May be greater than the measured value of the current.

Therefore, when only the second fluctuating low-resistance region 1042 is generated as shown in FIG. 29, the current flow between the source 1031 and the drain 1032 through the second fluctuating low-resistance region 1042 is different from that of FIG. Value information can be saved.

In addition, referring to FIG. 30, by controlling the size of the polarization region through voltage control through the gate 1020, the size of the first region can be formed to reach the third variable low resistance region 1043, and this Throughout, only the third low fluctuation resistance region 1043 is formed, and the first fluctuation low resistance region 1041 or the second fluctuation low resistance region 1042 is not generated.

If the first low fluctuation resistance region 1041 is formed, the third low fluctuation resistance region 1043 may be formed after removing the first low fluctuation resistance region 1041 through initialization. For example, the first fluctuating low-resistance region 1041 may be extinguished through control of voltage application through the gate 1020. This can be done by expanding the first area to the edge, and as another example, converting the first area into a second area, that is, by applying an electric field in the opposite direction.

A current flow between the source 1031 and the drain 1032 may be formed through the third variable low resistance region 1043.

Since the third fluctuation low resistance region 1043 is formed inside the second fluctuation low resistance region 1042, the flow of current from the source 1031 to the drain 1032 through the third fluctuation low resistance region 1043 The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the second fluctuating low resistance region 1042.

The length of the current flow can be a resistance to the current from the source 1031 to the drain 1032, and it can be said that the resistance increases as the length of the current flow from the source 1031 to the drain 1032 increases. have.

Therefore, the measured value of the current from the source 1031 to the drain 1032 through the third fluctuating low-resistance region 1043 is from the source 1031 to the drain 1032 through the second fluctuating low-resistance region 1042. May be greater than the measured value of the current.

Therefore, when only the third fluctuating low-resistance region 1043 is generated, as shown in FIG. 30, when a current flow between the source 1031 and the drain 1032 is formed through the third fluctuating low-resistance region 1043, FIGS. 28 and 28 You can store information of a value different from 29.

In addition, referring to FIG. 31, by controlling the size of the polarization region through voltage control through the gate 1020, the size of the first region can be formed to reach the fourth fluctuation low resistance region 1044, and this Throughout, only the fourth low fluctuation resistance region 1044 is formed, and the first fluctuation low resistance region 1041 to the third low fluctuation resistance region 1043 is not generated.

If the first low fluctuation resistance region 1041 is formed, the fourth low fluctuation resistance region 1044 may be formed after removing the first low fluctuation resistance region 1041 through initialization. For example, the first fluctuating low-resistance region 1041 may be extinguished through control of voltage application through the gate 1020. This can be done by expanding the first area to the edge, and as another example, converting the first area into a second area, that is, by applying an electric field in the opposite direction.

A current flow between the source 1031 and the drain 1032 may be formed through the fourth variable low resistance region 1044.

Since the fourth fluctuation low resistance region 1044 is formed inside the third fluctuation low resistance region 1043, current flows from the source 1031 to the drain 1032 through the fourth fluctuation low resistance region 1044. The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the third variable low resistance region 1043.

The length of the current flow can be a resistance to the current from the source 1031 to the drain 1032, and it can be said that the resistance increases as the length of the current flow from the source 1031 to the drain 1032 increases. have.

Therefore, the measured value of the current from the source 1031 to the drain 1032 through the fourth fluctuating low-resistance region 1044 is from the source 1031 to the drain 1032 through the third fluctuating low-resistance region 1043. May be greater than the measured value of the current.

Therefore, when only the fourth fluctuation low resistance region 1044 is generated as shown in FIG. 31, when the current flow between the source 1031 and the drain 1032 is formed through the fourth fluctuation low resistance region 1044, FIG. 28 and FIG. Information of values different from those of 29 and 30 may be stored.

As an alternative embodiment, a plurality of low-variable resistance regions may be formed at the same time. For example, as shown in FIG. 26, a plurality of fluctuating low resistance regions may be formed by applying the structure of FIG. 5 and the contents of FIGS. 7A to 7D, which are similar to those described in FIG. 26 as a specific example. have.

Through this, since it is possible to store more various types of information, it is possible to easily form a memory device with improved directivity.

A specific example will be described.

Further, referring to FIG. 32, it is shown that a second low-variable resistance region 1042 is formed inside the first low-variable resistance region 1041 based on the gate 1020.

One end of the second variable low resistance region 1042 may be connected to the source 1031 and the other end to the drain 1032.

For example, the second fluctuating low-resistance region 1042 may have a shape similar to a part of a rectangle smaller than the first fluctuating low-resistance region 1041, and the source 1031 is formed so as to overlap one side of the rectangle. , A drain 1032 may be formed on one side different from the one.

As an alternative embodiment, the second variable low-resistance region 1042 may have a shape similar to a quadrangle, and the source 1031 and the drain 1032 may be formed to overlap the two opposite sides of the quadrangle.

Since the second fluctuating low-resistance region 1042 is formed inside the first fluctuating low-resistance region 1041, the flow of current from the source 1031 to the drain 1032 through the second fluctuating low-resistance region 1042 The length of may be shorter than the length of the current flow from the source 1031 to the drain 1032 through the first fluctuating low resistance region 1041.

Compared to the current value when only one of the first fluctuating low-resistance region 1041 or the second fluctuating low-resistance region 1042 is formed as shown in FIG. 28 or 29, the first fluctuating low-resistance region 1041 or When all of the second fluctuation low resistance regions 1042 are formed, the current value may be larger.

Through this, the memory device 1000 can store information different from when only one of the first variable low resistance region 1041 or the second variable low resistance region 1042 is formed, thereby improving the degree of integration.

In addition, referring to FIG. 33, it is shown that a third low-variable low-resistance region 1043 is formed inside the second low-variable low-resistance region 1042 based on the gate 1020.

One end of the third variable low resistance region 1043 may be connected to the source 1031 and the other end to the drain 1032.

For example, the third variable low resistance region 1043 may have a shape similar to a part of a rectangle smaller than the second variable low resistance region 1042, and the source 1031 is formed so as to overlap one side of the square. , A drain 1032 may be formed on one side different from the one.

As an alternative embodiment, the source 1031 and the drain 1032 may be formed so that the third variable low resistance region 1043 has a shape similar to a quadrangle, and overlaps two opposite sides of the quadrangle.

Since the third fluctuation low resistance region 1043 is formed inside the second fluctuation low resistance region 1042, the flow of current from the source 1031 to the drain 1032 through the third fluctuation low resistance region 1043 The length of may be shorter than the length of the flow of current from the source 1031 to the drain 1032 through the second fluctuating low resistance region 1042.

The first fluctuation low-resistance region 1041 and the second fluctuation are lower than the current values when the first fluctuating low-resistance region 1041 and the second fluctuating low-resistance region 1042 shown in FIG. 32 are formed. When the resistance region 1042 and the third variable low resistance region 1043 are formed, the current value may be larger.

Through this, the memory device 1000 may store information having a value different from that of FIG. 32, and thus the degree of integration may be improved.

Further, referring to FIG. 34, it is shown that the fourth low-variable resistance region 1044 is formed inside the third low-variable resistance region 1043 based on the gate 1020.

One end of the fourth variable low resistance region 1044 may be connected to the source 1031 and the other end to the drain 1032.

For example, the fourth variable low resistance region 1044 may have a shape similar to a part of a rectangle smaller than the third variable low resistance region 1043, and the source 1031 is formed so as to overlap one side of the square. , A drain 1032 may be formed on one side different from the one.

As an alternative embodiment, the fourth variable low-resistance region 1044 may have a shape similar to a quadrangle, and the source 1031 and the drain 1032 may be formed so as to overlap on two opposite sides of the quadrangle.

Since the fourth fluctuation low resistance region 1044 is formed inside the third fluctuation low resistance region 1043, current flows from the source 1031 to the drain 1032 through the fourth fluctuation low resistance region 1044. The length of may be shorter than the length of the current flow from the source 1031 to the drain 1032 through the third variable low resistance region 1043.

The first fluctuation lower in FIG. 34 than the current values when the first fluctuating low-resistance region 1041, the second fluctuating low-resistance region 1042, and the third fluctuating low-resistance region 1043 shown in FIG. 33 are formed. When the resistance region 1041, the second low fluctuation resistance region 1042, the third low fluctuation resistance region 1043, and the fourth fluctuation low resistance region 1044 are formed, a current value may be larger.

Through this, the memory device 1000 may store information having a value different from that of FIG. 33, thereby improving integration.

The variable low-resistance region memory element formed as described above is the first variable low-resistance region 1041, the second low-variation resistance region 1042, the third low-variation resistance region 1043, or the fourth low-variation resistance as described above. The region 1044 can be used as a nonvolatile memory device because it can maintain its state even when the power to the gate 1020 is turned off.

Since the variable low-resistance region memory device can ^{write/erase about 10 12} times, it can have a memory life of ^{about 10 7} times that of a conventional semiconductor device-based memory device.

As for the memory speed, the variable low-resistance region memory device may be about 10 ^-9 sec, and thus the memory speed may be increased by ^{about 10 6} times compared to that of a conventional semiconductor device-based memory device.

As described above, the variable low-resistance region memory device can be a memory device having very excellent speed and lifetime.

In addition, through the control of the electric field through the gate 1020, only the first fluctuating low-resistance region 1041 is formed, the first and second fluctuating low-resistance regions 1041 and 1042 are formed, or the first, second, and second fluctuating low resistance regions 1041 and 1042 are formed. The three-variable low-resistance regions 1041, 1042, and 1043 may be formed, or the first, second, third, and fourth-variable low-resistance regions 1041, 1042, 1043, and 1044 may be formed.

On the other hand, when a current flows between the source 1031 and the drain 1032, the current value when only the first fluctuating low-resistance region 1041 is formed, and the first and second fluctuating low-resistance regions 1041 and 1042 are The current value when formed, the first, second and third fluctuation low resistance regions 1041, 1042, and 1043 when the current value and the first, second, third, and fourth fluctuation low resistance regions 1041, 1042, 1043 , 1044) may have different current values when formed, and different information may be stored using this.

In addition, as described above, only the first fluctuating low-resistance region 1041 is formed, only the second fluctuating low-resistance region 1042 is formed, or the third fluctuating low-resistance is formed through the control of the electric field through the gate 1020. Only the region 1043 may be formed, or only the fourth fluctuation low resistance region 1044 may be formed.

In addition, a current value when only the first fluctuating low resistance region 1041 is formed, a current value when only the second fluctuating low resistance region 1042 is formed, a current value when only the third fluctuating low resistance region 1043 is formed, When only the fourth fluctuation low resistance region 1044 is formed, the current values are all different, and different information may be stored using the same.

Through this, the degree of freedom in memory design is increased, and high information can be accumulated.

35 is a diagram for describing an example of an operation of a memory device according to an embodiment of the present invention.

Referring to FIG. 35, a constant daily current value is stably maintained after a time t1 has elapsed, a larger current value is stably maintained after a time t2 has passed, and a subsequent time t3 has elapsed. It is shown to stably maintain a larger current value.

For example, a case in which a constant daily current value is stably maintained after a time t1 elapses may be illustrated in FIG. 28, and a case in which a larger current value is stably maintained after a time t2 subsequently elapses is FIG. 29 may be described, and FIG. 30 may be described when a larger current value is stably maintained after a subsequent time t3 elapses.

As another example, a case in which a constant daily current value is stably maintained after a time t1 elapses may be illustrated in FIG. 28, and a case in which a larger current value is stably maintained after a time t2 has passed. FIG. 32 may be used to describe FIG. 32, and a case of stably maintaining a larger current value after time t3 elapses may indicate FIG. 33.

As described above, the current value is different in each case, and various information can be stored accordingly. As described above, the present invention has been described with reference to the embodiment shown in the drawings, but this is only exemplary, and is common in the art. Those of skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Specific implementations described in the embodiments are examples, and do not limit the scope of the embodiments in any way. In addition, if there is no specific mention such as "essential", "important", etc., it may not be an essential component for the application of the present invention.

In the specification of the embodiment (especially in the claims), the use of the term "above" and the similar reference term may correspond to both the singular and the plural. In addition, when a range is described in an embodiment, the invention to which individual values falling within the range are applied (unless otherwise stated), it is the same as describing each individual value constituting the range in the detailed description. . Finally, if there is no clearly stated or contrary to the order of steps constituting the method according to the embodiment, the steps may be performed in an appropriate order. The embodiments are not necessarily limited according to the order of description of the steps. The use of all examples or illustrative terms (for example, etc.) in the embodiments is merely for describing the embodiments in detail, and the scope of the embodiments is limited by the above examples or illustrative terms unless limited by the claims. It is not. In addition, those skilled in the art can recognize that various modifications, combinations, and changes may be configured according to design conditions and factors within the scope of the appended claims or their equivalents.

10, 100, 200: electronic circuit
11, 21, 110, 210: active layer
12, 120, 220: applied electrode
131, 132, 231, 232: connection electrode part
VL: fluctuation low resistance area
300, 400, 500, 600, 700, 800, 900, 1000: memory elements
320, 420, 520, 620, 720, 821, 822, 920, 1020: gate

Claims (10)

A base comprising a spontaneously polarizable material;
A gate disposed adjacent to the base;
A polarization region formed on the base by applying an electric field to the base through the gate and formed to correspond to a total thickness in the thickness direction of the base;
A variable low-resistance region including a region having an electrical resistance lower than that of other adjacent regions corresponding to the boundary of the polarization region;
A source spaced apart from the gate and connected to the variable low resistance region; And
And a drain spaced apart from the gate and connected to the variable low resistance region,
Through the control of the gate, the variable low resistance region is formed to selectively include at least one of a first variable low resistance region and a second variable low resistance region,
A first fluctuation low resistance region is formed to surround the gate and correspond to the total thickness in the thickness direction of the base,
A second variable low-resistance region surrounds the gate and is disposed closer to the gate than the first variance low-resistance region, and is formed to correspond to an entire thickness in a thickness direction of the base,
The source extends to have a length in one direction and has both sides in a direction crossing the length,
The drain extends to have a length in one direction and has both sides in a direction crossing the length,
Two ends of the second fluctuating low-resistance region are connected to both sides of the source, and two ends of the first fluctuating low-resistance region are located in a region further from the gate than the two ends of the second fluctuating low-resistance region. Connected,
The other two ends of the second fluctuating low-resistance region are connected to both sides of the drain, and the other two ends of the first fluctuating low-resistance region are located in a region farther from the gate than the other two ends of the second fluctuating low-resistance region. A variable low-resistance region-based memory device comprising the ends of which are connected. The method of claim 1,
The variable low-resistance region-based memory device comprising: a length of the first variable low-resistance region connecting the source and the drain is greater than a length of the second variable low-resistance region connecting the source and the drain. The method of claim 1,
The variable low resistance region includes the first variable low resistance region and a third variable low resistance region spaced apart from the second variable low resistance region. The method of claim 1,
A memory device based on a variable low resistance region configured to store different information according to the formation of the first variable low resistance region or the second variable low resistance region. The method of claim 1,
The variable low-resistance region is a variable low-resistance region-based memory device that controls an electric field through the gate to generate or disappear according to the control of the polarization region. The method of claim 1,
The variable low resistance region is maintained even when the electric field applied through the gate is removed. A base comprising a spontaneously polarizable material, a gate disposed adjacent to the base, a source spaced apart from the gate and connected to the variable low resistance region; And a drain spaced apart from the gate and connected to the variable low resistance region,
Forming a polarization region of the base by applying an electric field to the base through the gate; And
Forming a step of forming a fluctuating low-resistance region including a region having a lower electrical resistance than other adjacent regions corresponding to the boundary of the polarization region so that a current flow between the source and the drain is formed through the fluctuating low-resistance region. Including steps,
Through the control of the gate, the variable low resistance region is formed to selectively include at least one of a first variable low resistance region and a second variable low resistance region,
The first fluctuation low resistance region is formed to surround the gate and correspond to the total thickness in the thickness direction of the base,
The second fluctuation low resistance region surrounds the gate and is disposed closer to the gate than the first fluctuation low resistance region, and is formed to correspond to the entire thickness in the thickness direction of the base,
The source extends to have a length in one direction and has both sides in a direction crossing the length,
The drain extends to have a length in one direction and has both sides in a direction crossing the length,
Two ends of the second fluctuating low-resistance region are connected to both sides of the source, and two ends of the first fluctuating low-resistance region are located in a region further from the gate than the two ends of the second fluctuating low-resistance region. Connected,
The other two ends of the second fluctuating low-resistance region are connected to both sides of the drain, and the other two ends of the first fluctuating low-resistance region are located in a region further from the gate than the other two ends of the second fluctuating low-resistance region A method for controlling a memory device based on a variable low-resistance region, comprising connecting ends of the two ends. The method of claim 7,
And a length of the first variable low resistance region connecting the source and the drain is greater than a length of the second variable low resistance region connecting the source and the drain. The method of claim 7,
And measuring a current between the source and the drain as the first variable low resistance region or the second variable low resistance region is formed while controlling the gate. The method of claim 7,
And generating or extinguishing the variable low resistance region according to the control of the polarization region by controlling an electric field through the gate.

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