KR20200083842A - Variable low resistance area based memory device and controlling thereof - Google Patents

Abstract

According to one embodiment of the present invention, disclosed is a variable low resistance region-based memory device comprising: a base including a spontaneous polarizable material; a gate disposed adjacent to the base; a polarization region formed in the base by applying an electric field to the base through the gate; one or more fluctuating low resistance regions including regions having lower electrical resistance than that of the other adjacent regions corresponding to the boundary of the polarization region; a source spaced apart from the gate and connected to the variable low resistance region; and a drain spaced apart from the gate and connected to the variable low resistance region. Therefore, the present invention is capable of being applied to various applications.

Description

Variable low resistance area based memory device and control method thereof

The present invention relates to a memory device using a variable low resistance region and a control method therefor.

As the interest in the development of technology and the convenience of people's lives increases, attempts to develop various electronic products are becoming active.

In addition, these electronic products are becoming smaller and more integrated, and the places where they are used are increasing widely.

Such electronic products include various electric elements, for example, CPU, memory, and various other electric elements. These pre-elements may include various types of electrical circuits.

For example, electric devices are used in products in various fields, such as home sensor devices for IoT, bio-electronic devices for ergonomics, as well as computers and smartphones.

On the other hand, according to the recent speed of technological development and the rapid improvement of users' standard of living, the use and application fields of these electric devices have rapidly increased, and the demand has increased accordingly.

According to this trend, there are limitations in implementing and controlling electronic circuits that are easily and quickly applied to various electrical devices commonly used.

On the other hand, memory elements, especially non-volatile memory elements, are widely used as information storage and/or processing devices for various electronic devices, such as cameras and communication devices, as well as computers.

In particular, many developments have been made in these memory devices in terms of lifespan and speed, but most of the problems are in securing memory lifespan and speed, but there are limitations in implementing memory devices that have improved them.

The present invention can provide a memory device based on a variable low-resistance region that can be easily applied to various applications, a long data retention period, a high memory speed, and a memory device capable of improving device integration and a control method thereof. .

An embodiment of the present invention corresponds to a base comprising a spontaneous polarizable material, a gate disposed adjacent to the base, a polarization region formed on the base by applying an electric field to the base through the gate, and a boundary between the polarization regions One or more variable low-resistance regions including regions having lower electrical resistance than other adjacent regions, a source spaced apart from the gate and connected to the variable low-resistance region, and a drain spaced apart from the gate and connected to the variable low-resistance region. Disclosed is a memory device based on a variable low resistance region.

In the present embodiment, the variable low-resistance region is spaced apart from the first variable low-resistance region and the first variable low-resistance region and spaced apart from the first variable low-resistance region than the first variable low-resistance region. 2 One of the variable low-resistance regions may be selectively included.

In the present embodiment, the variable low-resistance region is spaced apart from the first variable low-resistance region and the first variable low-resistance region and spaced apart from the first variable low-resistance region than the first variable low-resistance region. 2 may include a variable low-resistance region.

In this embodiment, the source may have a long elongated shape to correspond to the second variable low-resistance region spaced apart from the first variable low-resistance region.

In this embodiment, the drain may have a long elongated shape to correspond to the second variable low resistance region spaced apart from the first variable low resistance region.

In this embodiment, the first variable low-resistance region or the second variable low-resistance region may be formed to store different information depending on the formation.

In this embodiment, the variable low-resistance region may be generated or destroyed under control of the polarization region by controlling an electric field through the gate.

In this embodiment, the variable low-resistance region can be maintained even when the electric field applied through the gate is removed.

According to another aspect of the present invention, a base comprising a spontaneous polarizable material, a gate disposed adjacent to the base, a source spaced apart from the gate and connected to the variable low resistance region; And forming a polarization region of the base by applying an electric field to the base through the gate for the variable low resistance region based memory device including a drain spaced apart from the gate and connected to the variable low resistance region. Forming a variable low-resistance region including a region having a lower electrical resistance than other adjacent regions corresponding to the boundary of the polarization region so that a flow of current between the source and drain is formed through the variable low-resistance region. Disclosed is a method for controlling a memory device based on a variable low-resistance region.

In the present embodiment, the variable low-resistance region is spaced apart from the first variable low-resistance region and the first variable low-resistance region and spaced apart from the first variable low-resistance region than the first variable low-resistance region. 2 One of the variable low-resistance regions may be selectively included.

In the present embodiment, the variable low-resistance region is spaced apart from the first variable low-resistance region and the first variable low-resistance region and spaced apart from the first variable low-resistance region than the first variable low-resistance region. 2 may include a variable low-resistance region.

In the present embodiment, as the first variable low-resistance region or the second variable low-resistance region is formed while controlling the gate, a step of measuring current between the source and the drain may be included.

In the present embodiment, controlling the electric field through the gate may include generating or destroying the variable low resistance region according to the control of the polarization region.

Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

The electronic circuit using the variable low resistance region according to the present invention and its control method can be easily applied to various uses.

1 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention.
2 is a cross-sectional view taken along line II-II of FIG. 1.
3 is an enlarged view of K in FIG. 2.
4A to 4C are diagrams for describing a control method related to the electronic circuit of FIG. 1. 5 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.
6 is a cross-sectional view taken along line VI-VI of FIG. 5.
7A to 7D are diagrams for describing a method of controlling a current path range in relation to the electronic circuit of FIG. 5.
8 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention.
9 is a cross-sectional view taken along line II-II of FIG. 8.
10 to 14 are diagrams for describing the operation of the electronic circuit of FIG. 8.
15 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.
16 is a cross-sectional view of FIG. 15 taken along line V-V.
17 is a schematic plan view showing a memory device according to still another embodiment of the present invention.
18 is a cross-sectional view taken along line VI-VI of FIG. 17.
19 is a graph showing the voltage and current relationship between the first region and the variable low-resistance region.
20 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.
21 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.
22 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.
23 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.
24 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.
25 to 27 are diagrams for describing a variable low-resistance region memory device according to another embodiment of the present invention.
28 to 34 are diagrams for describing a variable low-resistance region memory device according to another embodiment of the present invention.
35 is a view for explaining an example of the operation of the memory device according to an embodiment of the present invention.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to embodiments of the present invention shown in the accompanying drawings.

The present invention can be applied to various transformations and can have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention and methods for achieving them will be clarified with reference to embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be denoted by the same reference numerals and redundant description thereof will be omitted. .

In the following examples, terms such as first and second are not used in a limiting sense, but for the purpose of distinguishing one component from other components.

In the following embodiments, singular expressions include plural expressions, unless the context clearly indicates otherwise.

In the examples below, terms such as include or have are meant to mean that features or components described in the specification exist, and do not preclude the possibility of adding one or more other features or components.

In the drawings, the size of components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present invention is not necessarily limited to what is shown.

In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes on the Cartesian coordinate system, and can be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

When an embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to that described.

1 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and FIG. 3 is an enlarged view of K of FIG.

Referring to FIGS. 1 and 2, the electronic circuit 10 of the present embodiment may include an active layer 11, an applied electrode 12, and a variable low-resistance region VL.

The active layer 11 may include a spontaneous polarizable material. For example, the active layer 11 may include an insulating material and a ferroelectric material. That is, the active layer 11 may include a material having spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment the active layer 11 may comprise a perovskite-based material, for example, it may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

In another example, the active layer 11 is an ABX3 structure, A may include at least one material selected from inorganic groups such as Cs, Ru, and CnH2n+1 alkyl groups, and Cs, Ru capable of forming a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the active layer 11 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _3, CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

The active layer 11 may be formed by using various other ferroelectric materials, and thus, description of all examples will be omitted. In addition, when forming the active layer 11, the ferroelectric material may be doped with various other materials to include additional functions or to improve electrical properties.

The active layer 11 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the active layer 11 can maintain the polarization state even when the applied electric field is removed.

The applying electrode 12 may be formed to apply an electric field to the active layer 11, for example, a voltage may be applied to the active layer 11.

As an optional embodiment, the application electrode 12 may be formed to contact the top surface of the active layer 11.

In addition, the applying electrode 12 may be formed to apply a voltage of various sizes to the active layer 11 and to control the time of applying the voltage.

As an optional embodiment, the applied electrode 12 may be a gate electrode.

For example, the application electrode 12 may be electrically connected to a power supply (not shown) or a power control unit.

The applied electrode 12 may include various materials, and may include a material having high electrical conductivity. For example, the application electrode 12 may be formed using various metals.

For example, the applied electrode 12 may be formed to contain aluminum, chromium, titanium, tantalum, molybdenum, tungsten, neodymium, scandium or copper. Alternatively, it may be formed using an alloy of these materials or may be formed using a nitride of these materials.

Also, as an optional embodiment, the applied electrode 12 may include a laminate structure.

Although not shown, as an optional embodiment, one or more insulating layers may be further disposed between the applied electrode 12 and the active layer 11.

The variable low-resistance region VL is a region formed in the active layer 11 and is a region through which current can flow, and can also be formed as a path of current having a linearity around the applied electrode 12 as shown in FIG. 1. have.

Specifically, the variable low-resistance region VL is a region in which the electrical resistance is lower than other regions adjacent to the variable low-resistance region VL among the regions of the active layer 11.

In addition, after forming the variable low resistance region VL through the applied electrode 12, even if the electric field through the applied electrode 12 is removed, for example, even when the voltage is removed, the polarization state of the active layer 11 is Since it is maintained, the variable low-resistance region VL is maintained, and a state in which a current path is formed can be maintained.

Through this, various electronic circuits can be configured.

The variable low-resistance region VL has a height HVL, and this height HVL may correspond to the entire thickness of the active layer 11.

The variable low-resistance region VL may have a height HVL proportional to the strength of the electric field, for example, the magnitude of the voltage when an electric field is applied through the applied electrode 12. At least, the size of this electric field may be larger than the inherent anti-electric field of the active layer 11.

The variable low-resistance region VL is a region formed when a voltage is applied to the active layer 11 through the applied electrode 12, and can be changed, for example, generated, destroyed, or moved through control of the applied electrode 12. .

The active layer 11 may include a first polarization region 11F having a first polarization direction, and a variable low resistance region VL may be formed at the boundary of the first polarization region 11F.

In addition, a second polarization region 11R having a second polarization direction may be included to be adjacent to the first polarization region 11F, and the variable low resistance region VL is at the boundary of the second polarization region 11R. Can be formed. The second direction may be at least a different direction from the first direction, for example, a direction opposite to the first direction.

For example, the variable low resistance region VL may be formed between the first polarization region 11F and the second polarization region 11R.

The variable low resistance region VL may have a width WVL in one direction, which may be proportional to the moving distance of the variable low resistance region VL.

In addition, the width WVL may be the width of the planar region defined by the variable low resistance region VL, which can be said to correspond to the width of the first polarization region 11F.

In addition, the variable low-resistance region VL may be formed to correspond to the entire side surface of the boundary line of the first polarization region 11F, and may have a thickness TVL1 in a direction away from the side surface of the first polarization region 11F. have.

As an optional embodiment, this thickness (TVL1) may be 0.1 to 0.3 nanometers.

4A to 4C are diagrams for describing a current path range control method for the electronic circuit of FIG. 1.

Referring to FIG. 4A, the active layer 11 may include a second polarization region 11R having a second polarization direction. As an optional embodiment, the polarization state of the active layer 11 as shown in FIG. 4A may be formed by applying an initializing electric field through the applying electrode 12.

Then, referring to FIG. 4B, the first polarization region 11F is formed in the active layer 11. As a specific example, the first polarization region 11F may be first formed in a region overlapping the application electrode 12 to correspond to the width of the application electrode 12.

It is larger than the anti-electric field of the active layer 11 through the applied electrode 12 and has a size sufficient to form a height HVL of the first polarization region 11F to at least correspond to the entire thickness of the active layer 11. An electric field can be applied to the active layer 11.

The polarization direction of one region of the second polarization region 11R of the active layer 11 may be changed to the first polarization region 11F through the application of the electric field through the application electrode 12.

As an optional embodiment, the growth rate of the first polarization region 11F in the height (HVL) direction may be very fast, for example, at a speed of 1 km/sec (sec).

Then, if the electric field is continuously maintained through the applied electrode 12, that is, over time, the first polarization region 11F moves in a horizontal direction (H), that is, a direction perpendicular to the height (HVL) to increase in size. Can. That is, the region of the second polarization region 11R can be gradually converted into the first polarization region 11F.

As an alternative embodiment, the growth rate of the first polarization region 11F in the horizontal direction H may be very fast, for example, at a rate of 1 m/sec (sec).

Through this, the size of the variable low-resistance region VL can be controlled. For example, the size is the width of the variable low-resistance region VL and corresponds to the growth distance of the first polarization region 11F. It can be proportional to the holding time. For example, the growth distance may be proportional to the product of the growth speed and the electric field holding time.

In addition, the growth speed of the first polarization region 11F may be proportional to the sum of the growth rate in the height HVL direction and the growth rate in the horizontal direction H.

Therefore, the size of the variable low-resistance region VL can be adjusted as desired by controlling the electric field holding time.

Specifically, as illustrated in FIG. 4C, the first polarization region 11F spreads and becomes large, so that the variable low-resistance region VL can also move in a direction away from the applied electrode 12.

In the present embodiment, an electric field is applied to the active layer through an applied electrode to form a first polarization region having a first polarization direction different from a second polarization direction to the active layer, and at the boundary between the first polarization region and the first polarization region. A corresponding low-resistance region can be formed. Such a variable low-resistance region is a region with low resistance and can be a path of current as a region with reduced resistance, so that an electronic circuit can be easily formed.

In addition, the present embodiment can control the size of the electric field through the applied electrode, for example, by controlling the size of the voltage to determine the height of the variable low-resistance region, and specifically, to have a height corresponding to the overall thickness of the active layer. can do.

In addition, the time to maintain the electric field through the applied electrode can be controlled to determine the size of the variable low-resistance region, for example, width. Through the control of the size of the variable low-resistance region, the size of the path of the current flow can be easily controlled.

In addition, since the polarization state of the polarization region is maintained even when the electric field through the applied electrode is removed, the current path can be easily maintained, and when the polarization region is enlarged by continuously maintaining the electric field through the applied electrode, fluctuations that have already been formed are reduced In the resistance region, resistance may be lowered and current may not flow.

Through this, the extinction of the current path can be controlled, and consequently, the current flow can be easily controlled.

By controlling the electronic circuit of this embodiment, it can be used for various purposes, for example, one or more electrodes can be connected to contact the variable low resistance region.

5 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.

6 is a cross-sectional view taken along line VI-VI of FIG. 5.

5 and 6, the electronic circuit 20 of this embodiment may include an active layer 21, an applied electrode 22, and variable low-resistance regions VL1, VL2 and VL3.

The active layer 21 may include a spontaneous polarizable material. For example, the active layer 21 may include an insulating material and a ferroelectric material. That is, the active layer 21 may include a material having spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the active layer 21 may include a perovskite-based material, and a detailed description thereof is the same as the above-described embodiment, and thus is omitted.

The applying electrode 22 may be formed to apply an electric field to the active layer 21, for example, a voltage may be applied to the active layer 21. The detailed contents are the same as in the above-described embodiment, and thus will be omitted.

The variable low resistance areas VL1, VL2, and VL3 may include a first variable low resistance area VL1, a second variable low resistance area VL2, and a third variable low resistance area VL3.

The first variable low-resistance region VL1 may have a greater width than the second variable low-resistance region VL2, and the second variable low-resistance region VL2 may have a greater width than the third variable low-resistance region VL3. have. For example, the region surrounded by the first variable low-resistance region VL1 has a greater width than the region surrounded by the second variable low-resistance region VL2, and the region surrounded by the second variable low-resistance region VL2 is third variable. It may have a larger width than the region surrounded by the low resistance region VL3.

As an optional embodiment, the first variable low resistance region VL1 is disposed outside the second variable low resistance region VL2, and the second variable low resistance region VL2 is outside the third variable low resistance region VL3. Can be placed on.

The first variable low-resistance region VL1, the second variable low-resistance region VL2, and the third variable low-resistance region VL3 are regions formed in the active layer 21 and are regions through which current can flow and have a linear current. It can be formed of a path.

Specifically, the first variable low-resistance region VL1, the second variable low-resistance region VL2 and the third variable low-resistance region VL3 are the first variable low-resistance region VL1, the first of the regions of the active layer 21. It is a region in which electrical resistance is lower than other regions adjacent to the second variable low resistance region VL2 and the third variable low resistance region VL3.

Further, after forming the first variable low-resistance region VL1, the second variable low-resistance region VL2 and the third variable low-resistance region VL3 through the applied electrode 22, the applied variable electrode through the applied electrode 22 is formed. The polarization state of the active layer 21 is maintained even when the electric field is removed, for example, voltage is removed, so that the first variable low resistance region VL1, the second variable low resistance region VL2 and the third variable low resistance region (VL3) is maintained, and a state in which a path of current is formed can be maintained.

Through this, various electronic circuits can be configured. For example, at least a portion of a memory device capable of storing one or more data may be configured.

The variable low-resistance regions VL1, VL2, and VL3 have a height HVL, and this height HVL may correspond to the entire thickness of the active layer 21.

The active layer 21 may include first polarization regions 21F1 and 21F3 having a first polarization direction, and the variable low-resistance regions VL1, VL2, and VL3 border the first polarization regions 21F1 and 21F3. Can be formed on.

Further, it may include second polarization regions 21R1 and 21R2 having a second polarization direction so as to be adjacent to the first polarization regions 21F1 and 21F3, and the variable low-resistance regions VL may include such second polarization regions 21R1. , 21R2). The second direction may be at least a different direction from the first direction, for example, a direction opposite to the first direction.

For example, the first variable low resistance region VL1 may be formed between the first polarization region 21F1 and the second polarization region 21R1.

Also, the second variable low resistance region VL2 may be formed between the first polarization region 21F1 and the second polarization region 21R2.

Also, the third variable low resistance region VL3 may be formed between the first polarization region 21F3 and the second polarization region 21R2.

7A to 7D are diagrams for describing a method of controlling a current path range in relation to the electronic circuit of FIG. 5.

Referring to FIG. 7A, the active layer 21 may include a second polarization region 21R having a second polarization direction. As an optional embodiment, the polarization state of the active layer 21 as shown in FIG. 7A may be formed by applying an initializing electric field through the applying electrode 22.

Then, referring to FIG. 7B, the first polarization region 21F is formed in the active layer 21. As a specific example, a first polarization region 21F is first formed in a region overlapping with the application electrode 22 to correspond to the width of the application electrode 22, and then grown in a horizontal direction to form a state as shown in FIG. 7B. In addition, the first polarization region 21R of FIG. 7A may be reduced to change into the first polarization region 21R1 of the shape shown in FIG. 7B.

A first variable low resistance region VL1 may be formed between the first polarization region 21F and the second polarization region 21R1.

Then, referring to FIG. 7C, an electric field in the opposite direction to FIG. 7B is applied to convert the polarization direction of a portion of the first polarization region 21F to the second polarization region 21R2 having the polarization direction in the second direction. Can. For example, a second polarization region 21R2 having a polarization direction in a second direction that is opposite to the first polarization direction of the first polarization region 21F may be formed.

In addition, through this, the first polarization region 21F of FIG. 7B may be reduced in size and changed into the first polarization region 21F1 of the shape shown in FIG. 7C.

A second variable low-resistance region VL2 may be formed between the second polarization region 21R2 and the first polarization region 21F1.

Since the polarization state is maintained, the first variable low resistance region VL1 may be maintained.

Then, referring to FIG. 7D, an electric field in a direction opposite to that of FIG. 7C is applied to convert a polarization direction of a portion of the second polarization region 21R2 into a first polarization region 21F3 having a polarization direction in the first direction can do. For example, a first polarization region 21F3 having a polarization direction in a first direction that is opposite to a second polarization direction of the second polarization region 21R2 may be formed.

In addition, through this, the size of the second polarization region 21R2 of FIG. 7C may be reduced to change to the second polarization region 21R2 of the shape shown in FIG. 7D.

A third variable low resistance region VL3 may be formed between the second polarization region 21R2 and the first polarization region 21F3.

Since the polarization state is maintained, the first variable low-resistance region VL1 and the second variable low-resistance region VL2 are maintained, and the third variable low-resistance region VL3 may be added thereto.

In the present embodiment, an electric field is applied to the active layer through an applied electrode to form a first polarization region having a first polarization direction different from a second polarization direction to the active layer, and at the boundary between the first polarization region and the first polarization region. A corresponding low-resistance region can be formed. Such a variable low-resistance region is a region with low resistance and can be a path of current as a region with reduced resistance, so that an electronic circuit can be easily formed.

In addition, the present embodiment can control the size of the electric field through the applied electrode, and control the direction of the electric field, thereby forming a plurality of first polarization regions or a plurality of second polarization regions with respect to the active layer.

A plurality of variable low-resistance regions may be formed on a boundary line between the plurality of first polarization regions or the plurality of second polarization regions. Since each of the plurality of variable low-resistance regions can form a path of current, electronic circuits of various shapes and uses can be easily generated and controlled.

For example, a number of variable low-resistance regions can be selectively applied around the applied electrode to form various current paths, and a memory storing various data according to the current paths can be implemented.

8 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line II-II of FIG. 8.

8 and 9, the electronic circuit 100 of the present embodiment may include an active layer 110, an applied electrode 120, a variable low-resistance region VL, and one or more connection electrode parts 131 and 132. have.

The active layer 110 may include a spontaneous polarizable material. For example, the active layer 110 may include an insulating material and a ferroelectric material. That is, the active layer 110 may include a material having spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment the active layer 110 may comprise a perovskite-based material, for example, it may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

As another example, the active layer 110 is an ABX3 structure, and A may include one or more materials selected from CnH2n+1 alkyl groups and inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the active layer 110 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _3, CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

Since the active layer 110 can be formed using various other ferroelectric materials, descriptions of all examples thereof will be omitted. In addition, when the active layer 110 is formed, the ferroelectric material may be doped with various other materials to include additional functions or to improve electrical properties.

The active layer 110 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the active layer 110 may maintain a polarization state even when the applied electric field is removed.

The applying electrode 120 may be formed to apply an electric field to the active layer 110, for example, a voltage may be applied to the active layer 110.

As an optional embodiment, the application electrode 120 may be formed to contact the top surface of the active layer 110.

In addition, the application electrode 120 may be formed to apply a voltage of various sizes to the active layer 110 and to control the time of voltage application.

As an optional embodiment, the applied electrode 120 may be a gate electrode.

For example, the application electrode 120 may be electrically connected to a power supply (not shown) or a power control unit.

The applied electrode 120 may include various materials, and may include a material having high electrical conductivity. For example, the application electrode 120 may be formed using various metals.

For example, the applied electrode 120 may be formed to contain aluminum, chromium, titanium, tantalum, molybdenum, tungsten, neodymium, scandium or copper. Alternatively, it may be formed using an alloy of these materials or may be formed using a nitride of these materials.

Also, as an optional embodiment, the applied electrode 120 may include a laminate structure.

The connecting electrode parts 131 and 132 may include one or more electrode members, for example, the first connecting electrode member 131 and the second connecting electrode member 132.

The connection electrode portions 131 and 132 may be formed on the active layer 110, for example, may be formed to be spaced apart from the applied electrode 120 on the upper surface of the active layer 110, and as an optional embodiment, the active layer 110 ).

The first connecting electrode member 131 and the second connecting electrode member 132 may be formed using various conductive materials. For example, the first connection electrode member 131 and the second connection electrode member 132 may be formed to contain aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten.

As an optional embodiment, the first connection electrode member 131 and the second connection electrode member 132 may include a structure in which a plurality of conductive layers are stacked.

As an optional embodiment, the first connecting electrode member 131 and the second connecting electrode member 132 may be formed using a conductive metal oxide, for example, indium oxide (eg, In ₂ O ₃ ), tin oxide (E.g., SnO ₂ ), zinc oxide (e.g., ZnO), indium tin oxide alloy (e.g., In ₂ O ₃ ―SnO ₂ ) or indium zinc oxide alloy (e.g., In ₂ O ₃ ―ZnO) Can form.

As an optional embodiment, the connection electrode parts 131 and 132 may be a terminal member including input and output of electrical signals.

In addition, as a specific example, the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode parts 131 and 132 may include a source electrode or a drain electrode.

10 to 14 are diagrams for describing the operation of the electronic circuit of FIG. 8.

FIG. 10 is a view showing a state in which a first electric field is applied through the applied electrode 120, FIG. 11 is a cross-sectional view taken along the line X-V of FIG. 10, and FIG. 12 is an enlarged view of K in FIG. to be.

10 to 14, when a first electric field is applied to the active layer 110 through the application electrode 120, at least one region of the active layer 110 may include a polarization region 110F.

The polarization region 110F may have a shape surrounding the application electrode 120 around the application electrode 120. The polarization region 110F may have a boundary line.

The first variable low resistance region VL1 may be formed in a region corresponding to a side surface of the boundary line. Referring to FIG. 10, the application electrode 120 may be linearly formed around the application electrode 120.

For example, the first variable low resistance region VL1 may have a first width WVL1 in one direction to surround the applied electrode 120.

In addition, the first variable low resistance region VL1 may be formed to correspond to the entire side surface of the boundary line of the polarization region 110F, and may have a thickness TVL1 in a direction away from the side surface of the polarization region 110F.

As an optional embodiment, this thickness (TVL1) may be 0.1 to 0.3 nanometers.

As an optional embodiment, a process of applying an initializing electric field to the active layer 110 may be performed before the first voltage is applied to the active layer 110 through the applying electrode 120.

Through the process of applying the initializing electric field to the active layer 110, it may include the step of converting all of the regions of the active layer 110 into polarizations in different directions from the polarization region 110F, for example, polarization regions in opposite directions. .

Then, a polarization region 110F may be formed in one region by applying an electric field in the opposite direction.

The first variable low-resistance region VL1 formed at the boundary of the polarization region 110F of the active layer 110 may be changed to a region having a lower resistance than other regions of the active layer 110. For example, the first variable low resistance region VL1 may have a lower resistance than the polarization region 110F of the active layer 110 and the region of the active layer 110 around the first variable low resistance region VL1.

Through this, the first variable low-resistance region VL1 may form a passage of current.

As an optional embodiment, the first variable low resistance region VL1 may correspond to a region of a plurality of domain walls provided in the active layer 110.

In addition, the first variable low resistance region VL1 may be maintained when the polarization state of the polarization region 110F of the active layer 110 is maintained. That is, even if the first voltage applied to the active layer 110 is removed through the applied electrode 120, the state of the variable low resistance region VL1, that is, the low resistance state, may be maintained.

As illustrated in FIGS. 10 and 11, a passage of current may be formed through the first variable low resistance region VL1. However, since the connection electrode portions 131 and 132 do not correspond to the first variable low-resistance region VL1, the flow of current through the connection electrode portions 131 and 132 may not occur.

13 is a view showing a state in which the first electric field is maintained for a predetermined period of time through the applied electrode 120, and FIG. 14 is a cross-sectional view taken along line XI-XI of FIG. 13.

13 and 14, the holding time of the first electric field through the applied electrode 120 is increased, so that the polarization region 110F of FIGS. 10 and 11 moves in a horizontal direction, thereby increasing the polarization region 110F. A second variable low-resistance region VL2 larger than the first variable low-resistance region VL1 may be formed.

For example, the voltages applied in FIGS. 10 and 11 may be continuously maintained for a predetermined period of time to form structures as shown in FIGS. 13 and 14.

The polarization region 110F may have a shape surrounding the application electrode 120 around the application electrode 120. The polarization region 110F may have a boundary line. The second variable low resistance region VL2 may be formed in a region corresponding to a side surface of the boundary line of the polarization region 110F. Referring to FIG. 13, the application electrode 120 may be linearly formed around the application electrode 120.

For example, the second variable low-resistance region VL2 may have a second width WVL2 in one direction to surround the applied electrode 120, and the second width WVL2 is greater than the first width WVL1. Can.

Further, the second variable low-resistance region VL2 may be formed to correspond to the entire side surface of the boundary line of the polarization region 110F, may have a thickness in a direction away from the side surface of the polarization region 110F, and an optional embodiment As such, the thickness may be 0.1 to 0.3 nanometers.

The second variable low-resistance region VL2 formed at the boundary of the polarization region 110F of the active layer 110 may be changed to a region having a lower resistance than other regions of the active layer 110. For example, the second variable low resistance region VL2 may have a lower resistance than the polarization region 110F of the active layer 110 and the region of the active layer 110 around the second variable low resistance region VL2.

Through this, the second variable low-resistance region VL2 may form a passage of current.

As an optional embodiment, the second variable low resistance region VL2 may correspond to a region of a plurality of domain walls provided in the active layer 110.

In addition, the second variable low-resistance region VL2 may be maintained when the polarization state of the active layer 110 is maintained. That is, even if the second voltage applied to the active layer 110 is removed through the applying electrode 120, the state of the second variable low resistance region VL2, that is, the low resistance state may be maintained.

Therefore, a passage of current may be formed through the second variable low resistance region VL2.

In addition, as a specific example, the connection electrode portions 131 and 132 are formed to correspond to the second variable low-resistance region VL2, for example, the first connection electrode member 131 of the connection electrode portions 131 and 132 and The second connection electrode members 132 may be disposed to be in contact with the upper surface of the second variable low-resistance region VL2 while being spaced apart from each other.

Through this, current may flow through the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode parts 131 and 132.

In addition, various electrical signals can be generated. For example, when the electric field in the states of FIGS. 13 and 14 is continuously applied, that is, when the application time increases, the second variable low resistance region VL2 moves further to move the first connection electrode member 131 and the first 2 It may escape the connecting electrode member 132. Accordingly, current may not flow through the first connection electrode member 131 and the second connection electrode member 132.

Also, as an optional embodiment, an initialization process for the entire active layer 110 may be performed.

Then, when an electric field is applied to the active layer 110 again through the application electrode 120, current flows through the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode parts 131 and 132. Can.

The electronic circuit of this embodiment can apply voltages of various sizes to the active layer through the application electrode and control the time applied.

Through this, a polarization region can be formed in the active layer with an area of a desired size, and a variable low-resistance region can be formed at the boundary of the polarization region.

In order to correspond to such a variable low-resistance region, for example, when forming a connecting electrode portion to be in contact, an electric current can flow through the connecting electrode portion, and an active layer containing a ferroelectric material can maintain a polarization state even when voltage is removed. The fluctuating low-resistance region of the boundary can also be maintained, allowing current to continue flowing.

In addition, a voltage may be applied to the active layer through the application electrode to change the variable low-resistance region to the polarization region, through which no current flows through the connecting electrode portion through which the current flowed.

The current flow can be controlled by controlling the voltage of the applied electrode, and the electronic circuit can be used for various purposes through control of the current flow.

As an optional embodiment, the electronic circuit can be used as a memory.

For example, the current flow is defined as 1 and the non-flow is defined as 0, which can be used as a memory. As a specific example, it can be used as a non-volatile memory because current can flow even when voltage is removed.

In addition, the electronic circuit may constitute a circuit unit for generating and transmitting various signals, and may also be used as a switching element.

In addition, it can be applied to various fields such as a variable circuit, a CPU, a bio chip, etc. since it can be applied to a part requiring a control of an electrical signal with a simple structure.

15 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along line VV of FIG. 15.

15 and 16, the electronic circuit 200 of the present embodiment may include an active layer 210, an applied electrode 220, a variable low-resistance region VL, and connection electrode parts 231 and 232.

For convenience of description, description will be made focusing on differences from the above-described embodiments.

The active layer 210 may include a spontaneous polarizable material. For example, the active layer 210 may include an insulating material and a ferroelectric material. That is, the active layer 210 may include a material having spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

The description of the material forming the active layer 210 is the same as described in the above-described embodiment or can be applied by modifying it.

The applying electrode 220 may be formed to apply an electric field to the active layer 210, for example, a voltage may be applied to the active layer 210.

As an optional embodiment, the application electrode 220 may be formed to contact the top surface of the active layer 210.

The description of the material forming the applied electrode 220 is the same as that described in the above-described embodiment or can be applied by modifying it.

The connection electrode parts 231 and 232 may include one or more electrode members, for example, the first connection electrode member 231 and the second connection electrode member 232.

The connection electrode parts 231 and 232 may be formed on the active layer 210, for example, on the opposite side of the surface of the active layer 210 where the applied electrode 220 is formed to be spaced apart from the applied electrode 220. Can be formed.

The applied electrode 220 may be formed on the upper surface of the active layer 210 and the connection electrode portions 231 and 232 may be formed on the lower surface of the active layer 210.

As an optional embodiment, the connection electrode portions 231 and 232 may be formed to contact the active layer 210.

The first connection electrode member 231 and the second connection electrode member 232 may be formed using various conductive materials.

Descriptions of the materials forming the first connection electrode member 231 and the second connection electrode member 232 are the same as those described in the above-described embodiment or can be applied by modifying them.

Referring to FIG. 16, when a voltage is applied to the active layer 210 through the applying electrode 220, at least one region of the active layer 210 may include a polarization region 210F.

The variable low-resistance region VL may be formed in a region corresponding to a side surface of the boundary line of the polarization region 210F, and referring to FIG. 15, the linear surrounding the applied electrode 220 around the applied electrode 220 It can be formed as.

For example, the variable low-resistance region VL2 may have a width in one direction to surround the applied electrode 220.

In addition, the variable low-resistance region VL may be formed to correspond to the entire side surface of the boundary line of the polarization region 210F, may have a thickness in a direction away from the side surface of the polarization region 210F, and as an optional embodiment The thickness can be from 0.1 to 0.3 nanometers.

The variable low-resistance region VL formed at the boundary of the polarization region 210F of the active layer 210 may be changed to a region having a lower resistance than other regions of the active layer 210. For example, the variable low resistance region VL may have a lower resistance than the polarization region 210F of the active layer 210 and the region of the active layer 210 around the variable low resistance region VL.

Through this, the variable low-resistance region VL may form a passage of current.

As an optional embodiment, the variable low resistance region VL may correspond to a region of a plurality of domain walls provided in the active layer 210.

In addition, the variable low-resistance region VL may be maintained when the polarization state of the active layer 210 is maintained. That is, even if the voltage applied to the active layer 210 is removed through the applied electrode 220, the state of the variable low resistance region VL, that is, the low resistance state may be maintained.

A passage of current may be formed through the variable low resistance region VL.

In addition, as a specific example, the connection electrode portions 231 and 232 are formed to correspond to the variable low resistance region VL, for example, the first connection electrode member 231 and the second connection of the connection electrode portions 231 and 232 The electrode members 232 may be disposed to be in contact with the lower surface of the variable low-resistance region VL while being spaced apart from each other.

Through this, current may flow through the first connection electrode member 231 and the second connection electrode member 232 of the connection electrode parts 231 and 232.

The electronic circuit of this embodiment can apply voltages of various sizes to the active layer through the application electrode and control the time applied.

Through this, a polarization region can be formed in the active layer with an area of a desired size, and a variable low-resistance region can be formed at the boundary of the polarization region.

In addition, by forming an application electrode on one surface of the active layer and a connection electrode part on the other surface, it is possible to easily perform precise patterning and refinement of the electronic circuit.

The electronic device as described above may be implemented as the following variable low resistance region memory device.

17 is a schematic plan view showing a memory device according to still another embodiment of the present invention, and FIG. 18 is a cross-sectional view taken along line VI-VI of FIG. 17.

17 and 18, the variable low resistance region memory device 300 may include a base 310, a gate 320, a source 331, and a drain 332.

The base 310 may include the above-described active layer material, for example, may include a spontaneous polarizable material. For example, the base 310 may include an insulating material and a ferroelectric material. That is, the base 310 may include a material having spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment the base unit 310 may comprise a perovskite-based material, for example, it may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

As another example, the base 310 is an ABX3 structure, A may include one or more materials selected from CnH2n+1 alkyl groups, and inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the base 310 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _3, CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

The base 310 may be formed using various other ferroelectric materials, and descriptions of all examples thereof will be omitted. In addition, when forming the base 310, the ferroelectric material may be doped with various other materials to include additional functions or to improve electrical properties.

The base 310 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the base 310 may maintain a polarization state even when the applied electric field is removed.

The base 310 may include a first region 311 and a second region 312 positioned adjacent to each other in the X-Y plane direction. The first region 311 may have a polarization in a first direction, and the first direction is a thickness direction of the base 310, that is, a direction in which the first region 311 and the second region 312 are disposed. It may be in the Z-direction perpendicular to.

The second region 312 is positioned adjacent to the first region 311 in a direction perpendicular to the thickness, that is, in the XY plane direction, wherein the second region 312 is selectively opposite to the first direction. It may have polarizations aligned in two directions.

A gate 320 may be positioned on the second region 312. Although not shown in the drawing, the gate 320 may be connected to a separate device to receive a gate signal.

It is possible for the second region 312 to achieve polarization in a direction opposite to the first region 311 by a voltage applied to the gate 320.

Thus, a variable low resistance region 340 may be formed between the first region 311 and the second region 312 having polarizations in opposite directions. The variable low-resistance region 340 is a region having a very low resistance compared to the first region 311 and/or the second region 312, and current flow may be formed through the region.

The variable low-resistance region 340 may be formed according to the following embodiment.

First, the base 310 including the spontaneous polarizable material may have a polarization in the first direction as a whole. The entire base 310 is not limited to having a polarization in the first direction, and at least a certain area facing the gate 320 of the base 310 may have the polarization in the first direction. Optionally, the first polarization may be formed by applying an initializing electric field to the gate 320.

In this state, as the first voltage is applied to the gate 320 for a first time to apply an electric field to the base 310 through the gate 320, a certain area facing the gate 320 is polarized in the second direction. Will change. The electric field applied to the gate 320 to change the direction of polarization can be controlled by the first voltage, that is, the first voltage is applied such that an electric field larger than the anti-electric field of the spontaneous polarizable material forming the base 310 is applied. You can apply

The base 310 may have a first thickness t1. At this time, a second region 312 is formed over the entire first thickness t1, and the magnitude of the first voltage applied to the gate 320 may be adjusted according to the first thickness t1. According to an embodiment, the first thickness t1 and the magnitude of the first voltage applied to the gate 320 may be proportional. That is, when the first thickness t1 is thick, the first voltage can be increased.

18, the variable low-resistance region 340 may also be formed over the entire first thickness t1.

The area of the second region 312 formed as described above may be determined proportionally by the first time that the first voltage is applied to the gate 320.

Therefore, in order to form the second area 312 having a desired area and/or size, an appropriate gate voltage, time, and first thickness t1 of the second area 312 for the ferroelectric material are used in experiments and/or calculations. Can be determined in advance.

When the polarization direction of the second region 312 is changed from the first direction to the second direction, between the first region 311 having the polarization in the first direction and the second region 312 having the polarization in the second direction. A variable low-resistance region 340 having a predetermined width may be formed. The variable low-resistance region 340 may be formed around the gate 320.

19 is a graph showing the voltage and current relationship between the first region and the variable low-resistance region.

Specifically, FIG. 19 shows a state in which the current changes as the voltage increases in the first region and the variable low resistance region.

That is, in FIG. 19, (a) shows a state in which the current changes as the voltage increases in the variable low resistance region, and (b) shows a state in which the current changes as the voltage increases in the first region.

Since the variable low resistance region 340 has a very small resistance compared to the first region 311, it can be seen that the current flows smoothly according to voltage application.

The variable low-resistance region 340 formed as described above may not be erased over time.

The source 331 and the drain 332 are positioned to contact the thus formed variable low resistance region 340. In this case, a flow of current may be formed from the source 331 to the drain 332 through the variable low resistance region 340. Therefore, data can be written at this time, and can be read as 1, for example.

Optionally, the polarization direction of the second region 312 may be erased again by the voltage applied to the variable low-resistance region 340 and the gate 320 to be the same as the polarization direction of the first region 311.

That is, the polarization direction of the second region 312 may be changed to the first direction by applying the second voltage to the gate 320. Thereafter, by maintaining the second voltage for a second time, an area in which the polarization is changed in the first direction can be grown in a planar direction, and an area in which the polarization is changed in the first direction passes through the variable low-resistance area 340 to be the first. When extended to the region 311, the variable low-resistance region 340 may be extinguished. In this case, current cannot flow from the source 331 to the drain 332, and thus data erasing is possible at this time, and can be read as zero.

In this case, the second voltage may be a voltage different from the first voltage, and may be a voltage having the same magnitude as the first voltage according to an embodiment and having the opposite polarity. The second time may be at least the first time or more.

The variable low-resistance region memory element formed as described above can be used as a non-volatile memory element because the aforementioned variable low-resistance region 340 can maintain its state even when the gate 320 is powered off.

Since the variable low-resistance region memory device is capable of about 10 ¹² writes/erases, it may have a memory life of about 10 ⁷ times compared to a conventional semiconductor device-based memory device.

In the memory speed, the variable low-resistance region memory device can be about 10 ^-9 sec, which can increase the memory speed by about 10 ⁶ times compared to a conventional semiconductor device-based memory device.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and life.

In addition, since the position where the variable low-resistance region 340 is formed can be adjusted according to the gate voltage and/or the application time, various memory devices can be designed, and thinner than conventional ferroelectric memory devices using ferroelectrics. Can achieve In addition, since the degree of freedom in memory design is increased, there is an advantage of increasing the degree of integration of the device.

As shown in FIG. 17, the variable low-resistance region 340 formed as described above may be formed in a closed loop shape around the gate 320, and a source 331 and a drain 332 may be provided on a portion of the closed loop. By arranging, the line connecting the source 331 and the drain 332 may be two. However, the present invention is not limited thereto, and when the gate is placed on one side of the plane of the base and two adjacent adjacent sources and drains are disposed, the variable low resistance region may be a single line connecting the source and the drain.

The source 331 and the drain 332 as described above may be an electrode structure formed by being patterned on the base 310, but the present invention is not limited thereto, and the base 310 is not shown in the drawing. It may be in contact with the variable low-resistance region 340 through the via hole formed in the covering insulating film.

20 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 2, in the variable low-resistance region memory device 400, a source 431 and a drain 432 are formed on a substrate 430, and a base 410 including a spontaneous polarizable material is formed on the substrate 430. ). The substrate 430 may be formed of a semiconductor wafer, or a silicon wafer according to an embodiment. In addition, the source 431 and the drain 432 may be formed by ion doping on the wafer. Of course, although not shown in the drawing, an external signal line may be connected to the source 431 and the drain 432 through separate vias.

In this structure, the gate voltage and the application time may be determined so that the variable low-resistance region 440 is positioned to correspond to the regions of the source 431 and the drain 432 formed on the substrate 430.

The substrate 430 and the base 410 as described above may be bonded by separate adhesive layers, but are not limited thereto, and the base 410 may be formed on the substrate 430. By implementing the base 410 in a thin film on the substrate 430 in this way, the memory device 400 can be further thinned, and an existing memory device process can be used to further increase the efficiency of the manufacturing process.

The above-described embodiments have shown the case where the first region and the second region have the same thickness, but the present invention is not limited thereto.

21 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 21, in the variable low-resistance region memory device 500, a source 531 and a drain 532 are formed on a substrate 530, and a base 510 including a spontaneous polarizable material is formed on the substrate 530. ) May be disposed. The memory device 500 of the embodiment shown in FIG. 21 may have a second thickness t2 in which the first area 511 is thicker than the first thickness t1 of the second area 512. The second thickness t2 becomes a thickness in which the direction of polarization is not switched by the voltage applied to the gate 520, so that the variable low resistance region 540 has a first thickness t1 and a second thickness ( t2).

As described above, since the voltage applied to the gate 520 can be set to a voltage at which polarization switching is performed with respect to the first thickness t1, by creating an area formed with the second thickness t2 in the base 510. , The variable low-resistance region 540 is not formed in the second thickness t2 even by the intensity and time of the voltage applied to the gate 520, and the variable low-resistance region 540 is formed only in the region made of the first thickness t1. ) Can be formed.

That is, as shown in FIG. 21, the variable low-resistance region 540 may be formed at a position that is a boundary between the first thickness t1 and the second thickness t2.

22 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 22, in the variable low-resistance region memory device 600, a source 631 and a drain 632 are formed on the substrate 630, and a base 610 including a spontaneous polarizable material is formed on the substrate 630. ) May be disposed. The memory element 600 of the embodiment shown in FIG. 22 also has a second thickness t2 in which the first area 611 is thicker than the first thickness t1 of the second area 612 as in the embodiment shown in FIG. 21. Can have

At this time, depending on the time at which the voltage is applied to the gate 620, as shown in FIG. 22, the first thickness t1 is formed inside the boundary between the first thickness t1 and the second thickness t2. can do. Therefore, in the memory device 600 having such a structure, the source 631 and the drain 632 may be formed inside the boundary between the first thickness t1 and the second thickness t2. Accordingly, even if the formation position of the variable low-resistance region 640 is changed according to a change in the strength and/or time of the gate 620 voltage, the variable low-resistance region 640 and the source 631 / drain 632 It can be electrically connected.

In the above-described embodiments, the gate is formed adjacent to the base, but the present invention is not necessarily limited thereto.

23 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 23, in the memory device 700, another layer 750 may be further positioned between the base 710 and the gate 720. The film 750 may be an insulating film, and may be a material different from a ferroelectric material forming the base 710.

In this case, the polarization direction of the second region 712 may be switched due to the electric field due to the voltage applied to the gate 720, and at this time, the voltage and/or the gate 720 at which the polarization direction can be switched. Alternatively, the time can be obtained by experiment and/or calculation in advance.

24 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 24, in the variable low-resistance region memory device 800, a source 831 and a drain 832 are formed on a substrate 830, and a base 810 including a spontaneous polarizable material is formed on the substrate 830. ) May be disposed.

According to the embodiment illustrated in FIG. 24, a first gate 821 opposite to the base 810 and a second gate 822 positioned opposite the first gate 821 around the base 810 are included. can do.

In this case, the variable low-resistance region 840 may be formed by switching the polarization direction of the second region 812 by the first gate 821. This enables data writing.

The variable low-resistance region 840 can be removed by switching the polarization direction of the second region 812 again by the second gate 822 like the first region 811. This enables data erasure.

As described above, data can be read as 0/1 by the first gate 821 and the second gate 822.

All the embodiments of the present specification described above are not limited to the illustrated embodiments, and of course, they can be applied in combination with each other.

In addition, it is needless to say that these embodiments can be selectively applied or modified to the embodiments described later.

25 to 27 are diagrams for describing a variable low-resistance region memory device according to another embodiment of the present invention.

Referring first to FIG. 25, the variable low resistance region memory device 900 may include a base 910, a gate 920, a source 931, and a drain 932.

The base 910 may include the above-described active layer material, for example, may include a spontaneous polarizable material. For example, the base 910 may include an insulating material and a ferroelectric material. That is, the base 910 may include a material having spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment the base unit 910 may comprise a perovskite-based material, for example, it may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

As another example, the base 910 is an ABX3 structure, A may include one or more materials selected from CnH2n+1 alkyl groups, and inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. Specific examples are the same as those described in the above-described embodiment, and thus will be omitted.

The base 910 has spontaneous polarization, and can control the degree and direction of polarization according to the application of an electric field. Further, the base 910 may maintain a polarization state even when the applied electric field is removed.

A gate 920 may be positioned on the base 910.

The base 910 including the active layer material through the application of the voltage through the gate 920 may include a first region, which is a polarization region in one direction, around the gate 920 and is adjacent to the first region. A second region having a polarization direction different from that of the one region may be included. The contents of the first region and the second region may be formed similarly to those described in the above-described embodiments, and detailed description thereof will be omitted.

The first variable low-resistance region 941 may be formed between the first region and the second region having polarizations in opposite directions.

At this time, the size of the first region may be controlled by controlling the first voltage, and one end of the first variable low-resistance region 941 may be connected to the source 931 and the other end to the drain 932. .

In this case, a flow of current may be formed from the source 931 to the drain 932 through the first variable low resistance region 941.

For example, the first variable low-resistance region 941 may include a shape similar to a part of a square, and a source 931 is formed to overlap one side of the square, and a drain 932 is formed on the other side. Can be.

As an optional embodiment, the first variable low-resistance region 941 includes a shape similar to a square, and the source 931 and the drain 932 may be formed to overlap two opposite sides of the square.

Also, referring to FIG. 26, it is illustrated that the second variable low-resistance region 942 is formed inside the first variable low-resistance region 941 based on the gate 920.

One end of the second variable low-resistance region 942 may be connected to the source 931 and the other end to the drain 932.

For example, the second variable low-resistance region 942 may include a shape similar to a part of a square smaller than the first variable low-resistance region 941, and the source 931 is formed to overlap one side of the square. , The drain 932 may be formed on one side of the other.

As an alternative embodiment, the second variable low-resistance region 942 includes a shape similar to a square, and the source 931 and the drain 932 may be formed to overlap two opposite sides of the square.

Since the second variable low-resistance region 942 is formed inside the first variable low-resistance region 941, current flows from the source 931 to the drain 932 through the first variable low-resistance region 941. The length of may be greater than the length of the flow of current from the source 931 to the drain 932 through the second variable low resistance region 942.

The first variable low-resistance region 941 and the second variable low-resistance region 942 may be formed of paths having a linear current, specifically, the first variable low-resistance region 941 and the second variable low-resistance region. 942 is a region in which electrical resistance is lower than other adjacent regions.

The process of forming the first variable low-resistance region 941 and the second variable low-resistance region 942 may apply the same or similarly as described in FIGS. 7A to 7D of the above-described embodiment.

For example, a voltage may be applied to the base 910 through the gate 920 to form a single polarization state, through which a first variable low resistance region 941 may be formed. Then, by applying an electric field in the opposite direction, a second variable low resistance region 942 spaced apart from the first variable low resistance region 941 may be formed.

In addition, since the polarization state is maintained even when the voltage is removed from the gate 920, the first variable low-resistance region 941 and the second variable low-resistance region 942 may be maintained.

As an optional embodiment, the source 931 may be formed to be connected to both the first variable low resistance region 941 and the second variable low resistance region 942. For example, the source 931 may have a structure extending long along one direction, and may be formed long along a direction away from the gate 920 as a specific example.

In addition, the drain 932 may be formed to be connected to both the first variable low-resistance region 941 and the second variable low-resistance region 942. For example, the drain 932 may have a long elongated structure, and as a specific example, the drain 932 may be elongated along a direction away from the gate 920.

The source 931 and the drain 932 may have structures formed on both sides of the gate 920 therebetween.

The variable low-resistance region memory element formed as described above can be used as a non-volatile memory element because the variable low-resistance regions 941 and 942 can maintain the state even when the power is turned off to the gate 920.

Since the variable low-resistance region memory device is capable of about 10 ¹² writes/erases, it may have a memory life of about 10 ⁷ times compared to a conventional semiconductor device-based memory device.

In the memory speed, the variable low-resistance region memory device can be about 10 ^-9 sec, which can increase the memory speed by about 10 ⁶ times compared to a conventional semiconductor device-based memory device.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and life.

In addition, through control of the electric field through the gate 920, only the first variable low resistance region 941 is formed, or both the first variable low resistance region 941 and the second variable low resistance region 942 are formed. Can control things.

On the other hand, when a current flows between the source 931 and the drain 932, the current values when only the first variable low resistance region 941 is formed are the first variable low resistance region 941 and the second low variation. The resistance region 942 may be different from the current value when both are formed, and may be small, for example.

Through this, the memory device 900 can store two pieces of information, for example, 1 or 0, as well as more than 4 pieces of information, and these can be referred to as 0, 1, 2, and 3 for convenience. .

That is, as illustrated in FIG. 26, a case in which a current flows between the source 931 and the drain 932 is formed through the first variable low resistance region 941 and the second variable low resistance region 942 may be referred to as 3.

When only the first variable low-resistance region 941 is generated as illustrated in FIG. 25, a case in which current flows between the source 931 and the drain 932 is formed through the first variable low-resistance region 941 may be referred to as 1. .

In addition, referring to FIG. 27, the size of the polarization region may be controlled through voltage control through the gate 920 to form the size of the first region to reach the second variable low-resistance region 942. Through this, only the second variable low-resistance region 942 is formed, and the first variable low-resistance region 941 is not generated.

If the first variable low resistance region 941 is formed, the second variable low resistance region 942 may be formed after removing the first variable low resistance region 941 through initialization. For example, the first variable low-resistance region 941 may be extinguished through control of voltage application through the gate 920. This can be done by expanding the first region to the edge, or as another example, converting the first region to the second region, that is, applying an electric field in the opposite direction.

A current flow between the source 931 and the drain 932 may be formed through the second variable low resistance region 942.

Since the second variable low-resistance region 942 is formed inside the first variable low-resistance region 941, current flows from the source 931 to the drain 932 through the second variable low-resistance region 942. The length of may be smaller than the length of the flow of current from the source 931 to the drain 932 through the first variable low resistance region 941.

The length of the current flow may be a resistance to the current from the source 931 to the drain 932, and the resistance may be increased as the length of the current flow from the source 931 to the drain 932 increases. have.

Therefore, the measured value of the current from the source 931 through the second variable low resistance region 942 to the drain 932 is from the source 931 through the first variable low resistance region 941 to the drain 932 It can be greater than the measured value of the current.

Therefore, when only the second variable low-resistance region 942 is generated as shown in FIG. 27, the case where the current flow between the source 931 and the drain 932 is formed through the second variable low-resistance region 942 can be referred to as 2. have.

In addition, when the voltage control through the gate 920, the first and second variable low-resistance regions 941 and 942 are extinguished, and the current flow between the source 931 and the drain 932 is not formed, it is assumed to be 0. Can.

That is, since the first variable low-resistance region 941 and the second variable low-resistance region 942 may be formed through the gate 920, the first variable low-resistance region 941 and the second variable low-resistance region 941 and the second variable low-resistance region may be formed. Memory can be formed as four different pieces of information through measurement of current under the control of the resistance region 942.

Therefore, when a single low-resistance region is used in the design of a memory device, two pieces of information, 0 and 1, can be stored. If the number of low-resistance regions is increased to n, at least n+1 or more pieces of information can be stored. Through this, it is possible to easily provide a memory device design that can integrate more information.

Through this, the degree of freedom of memory design is increased and high information can be accumulated.

28 to 34 are diagrams for describing a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 28, the variable low-resistance region memory device 1000 may include a base 1010, a gate 1020, a source 1031, and a drain 1032.

The base 1010 may include the above-described active layer material, for example, may include a spontaneous polarizable material. For example, the base 1010 may include an insulating material and a ferroelectric material. That is, the base 1010 may include a material having spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

Base 1010, as an alternative embodiment may comprise a perovskite-based material, for example, may include _{BaTiO 3, SrTiO 3, BiFe3,} PbTiO3, PbZrO3, SrBi2Ta2O9.

Further, as another example, the base 1010 is an ABX3 structure, A may include one or more materials selected from CnH2n+1 alkyl groups, and inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B May include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. Specific examples are the same as those described in the above-described embodiment, and thus will be omitted.

The base 1010 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the base 1010 can maintain a polarization state even when the applied electric field is removed.

A gate 1020 may be positioned on the base 1010.

The base 1010 including the active layer material through the application of the voltage through the gate 1020 may include a first region, which is a polarization region in one direction, around the gate 1020, and adjacent to the first region. It may include a second region having a polarization direction in a direction different from the polarization direction of one region. The contents of the first region and the second region may be formed similarly to those described in the above-described embodiments, and detailed description thereof will be omitted.

The first variable low-resistance region 1041 may be formed between the first region and the second region having polarizations in opposite directions.

At this time, the size of the first region may be controlled by controlling the first voltage, and one end of the first variable low-resistance region 1041 may be connected to the source 1031 and the other end to the drain 1032. .

In this case, a flow of current may be formed from the source 1031 to the drain 1032 through the first variable low resistance region 1041.

For example, the first variable low-resistance region 1041 may include a shape similar to a part of a square, and a source 1031 is formed to overlap one side of the square, and a drain 1032 is formed on the other side. Can be.

As an optional embodiment, the first variable low-resistance region 1041 includes a shape similar to a square, and the source 1031 and the drain 1032 may be formed to overlap two opposite sides of the square.

In addition, referring to FIG. 29, the size of the polarization region may be controlled through voltage control through the gate 1020 to form the size of the first region to reach the second variable low-resistance region 1042, which Through this, only the second variable low-resistance region 1042 is formed, and the first variable low-resistance region 1041 is not generated.

If the first variable low resistance region 1041 is formed, the second variable low resistance region 1042 may be formed after removing the first variable low resistance region 1041 through initialization. For example, the first variable low-resistance region 1041 may be extinguished through control of voltage application through the gate 1020. This can be done by expanding the first region to the edge, or as another example, converting the first region to the second region, that is, applying an electric field in the opposite direction.

A current flow between the source 1031 and the drain 1032 may be formed through the second variable low-resistance region 1042.

Since the second variable low-resistance region 1042 is formed inside the first variable low-resistance region 1041, the current flows from the source 1031 to the drain 1032 through the second variable low-resistance region 1042. The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the first variable low-resistance region 1041.

It can be said that the length of the flow of the current can be a resistance to the current from the source 1031 to the drain 1032, and the resistance increases as the length of the flow of the current from the source 1031 to the drain 1032 increases. have.

Therefore, the measured value of the current from the source 1031 through the second variable low resistance region 1042 to the drain 1032 is from the source 1031 through the first variable low resistance region 1041 to the drain 1032 It can be greater than the measured value of the current.

Therefore, when only the second variable low-resistance region 1042 is generated as shown in FIG. 29, the flow of current between the source 1031 and the drain 1032 through the second variable low-resistance region 1042 is different from that in FIG. Value information can be stored.

In addition, referring to FIG. 30, the size of the polarization region may be controlled through voltage control through the gate 1020 to form the size of the first region to reach the third variable low-resistance region 1043. Through this, only the third variable low-resistance region 1043 is formed, and the first variable low-resistance region 1041 or the second variable low-resistance region 1042 is not generated.

If the first variable low resistance region 1041 is formed, the third variable low resistance region 1043 may be formed after removing the first variable low resistance region 1041 through initialization. For example, the first variable low-resistance region 1041 may be extinguished through control of voltage application through the gate 1020. This can be done by expanding the first region to the edge, or as another example, converting the first region to the second region, that is, applying an electric field in the opposite direction.

A current flow between the source 1031 and the drain 1032 may be formed through the third variable low resistance region 1043.

Since the third variable low-resistance region 1043 is formed inside the second variable low-resistance region 1042, current flows from the source 1031 to the drain 1032 through the third variable low-resistance region 1043. The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the second variable low resistance region 1042.

It can be said that the length of the flow of the current can be a resistance to the current from the source 1031 to the drain 1032, and the resistance increases as the length of the flow of the current from the source 1031 to the drain 1032 increases. have.

Therefore, the measured value of the current from the source 1031 through the third variable low resistance region 1043 to the drain 1032 is from the source 1031 through the second variable low resistance region 1042 to the drain 1032. It can be greater than the measured value of the current.

Therefore, when only the third variable low-resistance region 1043 is generated as shown in FIG. 30, the flow of current between the source 1031 and the drain 1032 is formed through the third variable low-resistance region 1043. You can store information with a value different from 29.

In addition, referring to FIG. 31, the size of the polarization region may be controlled through voltage control through the gate 1020 to form the size of the first region to reach the fourth variable low-resistance region 1044. Through this, only the fourth variable low resistance region 1044 is formed, and the first variable low resistance region 1041 to the third variable low resistance region 1043 are not generated.

If the first variable low-resistance region 1041 is formed, the fourth variable low-resistance region 1044 may be formed after removing the first variable low-resistance region 1041 through initialization. For example, the first variable low-resistance region 1041 may be extinguished through control of voltage application through the gate 1020. This can be done by expanding the first region to the edge, or as another example, converting the first region to the second region, that is, applying an electric field in the opposite direction.

A current flow between the source 1031 and the drain 1032 may be formed through the fourth variable low resistance region 1044.

Since the fourth variable low-resistance region 1044 is formed inside the third variable low-resistance region 1043, current flows from the source 1031 to the drain 1032 through the fourth variable low-resistance region 1044. The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the third variable low-resistance region 1043.

It can be said that the length of the flow of the current can be a resistance to the current from the source 1031 to the drain 1032, and the resistance increases as the length of the flow of the current from the source 1031 to the drain 1032 increases. have.

Therefore, the measured value of the current from the source 1031 through the fourth variable low resistance region 1044 to the drain 1032 is from the source 1031 through the third variable low resistance region 1043 to the drain 1032. It can be greater than the measured value of the current.

Therefore, when only the fourth variable low-resistance region 1044 is generated as shown in FIG. 31, the flow of current between the source 1031 and the drain 1032 is formed through the fourth variable low-resistance region 1044. It is possible to store information of different values from 29 and FIG. 30.

As an optional embodiment, a plurality of variable low-resistance regions may be simultaneously formed. For example, as shown in FIG. 26, a plurality of variable low-resistance regions may be formed by applying the structure of FIG. 5 and the contents of FIGS. 7A to 7D explaining the same, and as a specific example, it may be similar to that described in FIG. 26. have.

Through this, more various types of information can be stored, so that a memory element with improved directization can be easily formed.

A specific example will be described.

In addition, referring to FIG. 32, it is illustrated that the second variable low-resistance region 1042 is formed inside the first variable low-resistance region 1041 based on the gate 1020.

One end of the second variable low-resistance region 1042 may be connected to the source 1031 and the other end to the drain 1032.

For example, the second variable low-resistance region 1042 may include a shape similar to a part of a square smaller than the first variable low-resistance region 1041, and the source 1031 is formed to overlap one side of the square. , A drain 1032 may be formed on one side of the other.

As an optional embodiment, the second variable low-resistance region 1042 includes a shape similar to a square, and the source 1031 and the drain 1032 may be formed to overlap two opposite sides of the square.

Since the second variable low-resistance region 1042 is formed inside the first variable low-resistance region 1041, the current flows from the source 1031 to the drain 1032 through the second variable low-resistance region 1042. The length of may be shorter than the length of the flow of current from the source 1031 to the drain 1032 through the first variable low resistance region 1041.

As shown in FIG. 28 or 29, compared to the current value when only one of the first variable low-resistance region 1041 or the second variable low-resistance region 1042 is formed, as shown in FIG. 32, the first variable low-resistance region 1041 or The current value when all of the second variable low-resistance region 1042 is formed may be larger.

Through this, the memory device 1000 can store information different from when only one of the one variable low-resistance region 1041 or the second variable low-resistance region 1042 is formed, thereby improving integration.

In addition, referring to FIG. 33, it is illustrated that the third variable low-resistance region 1043 is formed inside the second variable low-resistance region 1042 based on the gate 1020.

One end of the third variable low-resistance region 1043 may be connected to the source 1031 and the other end to the drain 1032.

For example, the third variable low-resistance region 1043 may include a shape similar to a part of a square smaller than the second variable low-resistance region 1042, and a source 1031 is formed to overlap one side of the square. , A drain 1032 may be formed on one side of the other.

As an alternative embodiment, the third variable low-resistance region 1043 includes a shape similar to a square, and the source 1031 and the drain 1032 may be formed to overlap two opposite sides of the square.

Since the third variable low-resistance region 1043 is formed inside the second variable low-resistance region 1042, current flows from the source 1031 to the drain 1032 through the third variable low-resistance region 1043. The length of may be shorter than the length of the flow of current from the source 1031 to the drain 1032 through the second variable low-resistance region 1042.

The first fluctuation low resistance region 1041 and the second fluctuation lower than the current values when the first fluctuation low resistance region 1041 and the second fluctuation low resistance region 1042 shown in FIG. 32 are formed. The current value when the resistance region 1042 and the third variable low resistance region 1043 are formed may be larger.

Through this, the memory device 1000 can store information having a different value from that of FIG. 32, thereby improving integration.

In addition, referring to FIG. 34, it is illustrated that a fourth variable low-resistance region 1044 is formed inside the third variable low-resistance region 1043 based on the gate 1020.

One end of the fourth variable low-resistance region 1044 may be connected to the source 1031 and the other end to the drain 1032.

For example, the fourth variable low-resistance region 1044 may include a shape similar to a part of a square smaller than the third variable low-resistance region 1043, and the source 1031 is formed to overlap one side of the square. , A drain 1032 may be formed on one side.

As an optional embodiment, the fourth variable low-resistance region 1044 includes a shape similar to a rectangle, and the source 1031 and the drain 1032 may be formed to overlap two opposite sides of the rectangle.

Since the fourth variable low-resistance region 1044 is formed inside the third variable low-resistance region 1043, current flows from the source 1031 to the drain 1032 through the fourth variable low-resistance region 1044. The length of may be shorter than the length of the flow of current from the source 1031 to the drain 1032 through the third variable low-resistance region 1043.

The current value when the first variable low resistance region 1041, the second variable low resistance region 1042, and the third variable low resistance region 1043 shown in FIG. The current value when the resistance region 1041, the second variable low resistance region 1042, the third variable low resistance region 1043, and the fourth variable low resistance region 1044 are formed may be larger.

Through this, the memory device 1000 can store information having a different value from that of FIG. 33, thereby improving integration.

The variable low-resistance region memory element formed as described above is the first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043 or the fourth variable low-resistance as described above. The region 1044 can be used as a nonvolatile memory device because it can maintain its state even when the power is turned off to the gate 1020.

Since the variable low-resistance region memory device is capable of about 10 ¹² writes/erases, it may have a memory life of about 10 ⁷ times compared to a conventional semiconductor device-based memory device.

In the memory speed, the variable low-resistance region memory device can be about 10 ^-9 sec, which can increase the memory speed by about 10 ⁶ times compared to a conventional semiconductor device-based memory device.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and life.

In addition, through control of the electric field through the gate 1020, only the first variable low-resistance regions 1041 are formed, or the first and second variable low-resistance regions 1041, 1042 are formed, or the first, second, The three variable low-resistance regions 1041, 1042, and 1043 may be formed, or the first, second, third, and fourth variable low-resistance regions 1041, 1042, 1043, and 1044 may be formed.

On the other hand, when a current flows between the source 1031 and the drain 1032, the current value when only the first variable low-resistance region 1041 is formed, and the first and second variable low-resistance regions 1041 and 1042 are Current value when formed, first, 2, 3 fluctuating low-resistance regions 1041, 1042, 1043, and current value when formed and fluctuating low-resistance regions 1401, 1042, 1043 , 1044) may have different current values, and different information may be stored using the current values.

In addition, through the control of the electric field through the gate 1020 as described above, only the first variable low-resistance region 1041 is formed, or only the second variable low-resistance region 1042 is formed, or the third variable low-resistance region is formed. Only the region 1043 may be formed, or only the fourth variable low-resistance region 1044 may be formed.

And, the current value when only the first variable low-resistance region 1041 is formed, the current value when only the second variable low-resistance region 1042 is formed, and the current value when only the third variable low-resistance region 1043 is formed, When only the fourth variable low-resistance region 1044 is formed, all current values are different, and different information can be stored by using them.

Through this, the degree of freedom of memory design is increased and high information can be accumulated.

35 is a view for explaining an example of the operation of the memory device according to an embodiment of the present invention.

Referring to FIG. 35, after a time t1, a constant constant current value is stably maintained, and after a time t2, the current value is stably maintained, and a time t3 is subsequently passed. It is shown that the current value is stably maintained.

For example, the case where the constant constant current value is stably maintained after the time t1 has passed may be described with reference to FIG. 28, and when the subsequent time t2 is stably maintained, the current value is greater than that. It may be described in FIG. 29, and subsequently, when time t3 is steadily maintained and a larger current value is maintained, it may be described in FIG.

As another example, the case in which a constant constant current value is stably maintained after a time t1 may be described with reference to FIG. 28, and subsequently, when a time t2 is stably maintained, a current value larger than that may be maintained. 32 may be a description of FIG. 32, and a case where a current value that is greater than that after a time t3 is stably maintained may be described with reference to FIG. 33.

As described above, the current value is changed in each case and various information can be stored accordingly. As described above, the present invention has been described with reference to the embodiment illustrated in the drawings, but this is only exemplary, and it is common in the art. Those skilled in the art will appreciate that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

The specific implementations described in the embodiments are examples, and do not limit the scope of the embodiments in any way. In addition, unless specifically mentioned, such as "essential", "important", etc., it may not be a necessary component for the application of the present invention.

In the specification (especially in the claims) of the embodiments, the use of the term “above” and similar indicating terms may correspond to both singular and plural. In addition, in the case where the range is described in the embodiment, as including the invention to which the individual values belonging to the range are applied (if there is no contrary description), it is the same as describing each individual value constituting the range in the detailed description. . Finally, unless there is an explicit or contradictory description of steps constituting the method according to the embodiment, the steps may be performed in a suitable order. The embodiments are not necessarily limited to the order in which the steps are described. The use of all examples or exemplary terms (eg, etc.) in the embodiments is merely for describing the embodiments in detail, and the scope of the embodiments is limited by the examples or exemplary terms, unless it is defined by the claims. It is not. In addition, those skilled in the art can recognize that various modifications, combinations, and changes can be configured according to design conditions and factors within the scope of the appended claims or equivalents thereof.

10, 100, 200: electronic circuit
11, 21, 110, 210: active layer
12, 120, 220: applied electrode
131, 132, 231, 232: connection electrode part
VL: Variable low resistance area
300, 400, 500, 600, 700, 800, 900, 1000: memory element
320, 420, 520, 620, 720, 821, 822, 920, 1020: gate

Claims (13)

A base comprising spontaneous polarizable material;
A gate disposed adjacent to the base;
A polarization region formed on the base by applying an electric field to the base through the gate;
One or more variable low-resistance regions including regions having lower electrical resistance than other adjacent regions corresponding to the boundary of the polarization region;
A source spaced apart from the gate and connected to the variable low resistance region; And
A variable low-resistance region-based memory device including a drain spaced apart from the gate and connected to the variable low-resistance region. According to claim 1,
The variable low-resistance region is a first variable low-resistance region arranged to be spaced apart from the gate and a second variable low-resistance region disposed closer to the gate than the first variable low-resistance region and spaced apart from the first variable low-resistance region. A variable low-resistance region based memory device selectively including one of the following. According to claim 1,
The variable low-resistance region is a first variable low-resistance region arranged to be spaced apart from the gate and a second variable low-resistance region disposed closer to the gate than the first variable low-resistance region and spaced apart from the first variable low-resistance region. Variable-resistance region-based memory device comprising a. According to claim 2,
The source is a variable low-resistance region-based memory device having an elongated shape to correspond to a second variable low-resistance region spaced apart from the first variable low-resistance region. According to claim 2,
The drain has a long elongated shape to correspond to the second variable low-resistance area spaced apart from the first variable low-resistance area. According to claim 1,
A variable low resistance region based memory device configured to store different information according to the formation of the first variable low resistance region or the second variable low resistance region. According to claim 1,
The variable low-resistance region is a variable low-resistance region-based memory device that generates or disappears under control of the polarization region by controlling an electric field through the gate. According to claim 1,
The variable low-resistance region is a memory device based on the variable low-resistance region that is maintained even when an electric field applied through the gate is removed. A base comprising a spontaneous polarizable material, a gate disposed adjacent to the base, a source spaced apart from the gate and connected to the variable low resistance region; And a drain spaced apart from the gate and connected to the variable low-resistance region.
Forming a polarization region of the base by applying an electric field to the base through the gate; And
A step of forming a variable low-resistance region including a region having a lower electrical resistance than other adjacent regions corresponding to the boundary of the polarization region is formed so that a flow of current between the source and drain is formed through the variable low-resistance region. A method of controlling a memory device based on a variable low-resistance region comprising steps. The method of claim 9,
The variable low-resistance region is a first variable low-resistance region arranged to be spaced apart from the gate and a second variable low-resistance region disposed closer to the gate than the first variable low-resistance region and spaced apart from the first variable low-resistance region. A method for controlling a memory device based on a variable low-resistance region, optionally including one of the following. The method of claim 9,
The variable low-resistance region is a first variable low-resistance region arranged to be spaced apart from the gate and a second variable low-resistance region disposed closer to the gate than the first variable low-resistance region and spaced apart from the first variable low-resistance region. A method for controlling a memory device based on a variable low-resistance region, comprising: a. The method of claim 10 or 11,
And controlling the gate to measure the current between the source and the drain as the first variable low-resistance region or the second variable low-resistance region is formed. The method of claim 9,
And controlling the electric field through the gate to generate or destroy the variable low-resistance region according to the control of the polarization region.

Images