KR102484129B1 - Variable low resistance area based memory device and controlling thereof - Google Patents

Abstract

An embodiment of the present invention provides a base including a spontaneously polarizable material, a gate disposed adjacent to the base, a polarization region formed on the base by applying an electric field to the base through the gate, and corresponding to a boundary of the polarization region. One or more variable low-resistance regions including regions having lower electrical resistance than other adjacent regions, a source spaced apart from the gate and connected to the variable low-resistance region, and a drain spaced apart from the gate and connected to the variable low-resistance region Disclosed is a variable low-resistance region-based memory device comprising:

Description

Variable low resistance area based memory device and control method thereof

The present invention relates to a memory device using a variable low resistance region and a control method thereof.

As technology advances and people's interest in the convenience of life increases, attempts to develop various electronic products are becoming more active.

In addition, these electronic products are increasingly being miniaturized and integrated, and the places where they are used are increasing widely.

These electronic products include various electrical devices, such as CPUs, memories, and other various electrical devices. These base elements may include various types of electrical circuits.

For example, electrical devices are used in products in various fields, such as computers, smart phones, household sensor devices for IoT, and bio-electronic devices for ergonomics.

On the other hand, according to the recent speed of technological development and the rapid improvement of users' living standards, the use and application fields of these electric devices are rapidly increasing, and the demand thereof is also increasing accordingly.

In accordance with this trend, there is a limit to implementing and controlling electronic circuits that can be easily and quickly applied to various electrical devices that are commonly used.

Meanwhile, memory devices, particularly non-volatile memory devices, are widely used as information storage and/or processing devices for various electronic devices such as computers, cameras, and communication devices.

These memory devices are being developed a lot, especially in terms of lifespan and speed. Most of the tasks are to secure memory lifespan and speed, but there is a limit to implementing a memory device with improved memory lifespan and speed.

The present invention can provide a variable low-resistance region-based memory device that can be easily applied to various uses, a memory device with a long data retention period, high memory speed, and improved device integration, and a control method thereof. .

An embodiment of the present invention provides a base including a spontaneously polarizable material, a gate disposed adjacent to the base, a polarization region formed on the base by applying an electric field to the base through the gate, and corresponding to a boundary of the polarization region. One or more variable low-resistance regions including regions having lower electrical resistance than other adjacent regions, a source spaced apart from the gate and connected to the variable low-resistance region, and a drain spaced apart from the gate and connected to the variable low-resistance region Disclosed is a variable low-resistance region-based memory device comprising:

In the present embodiment, the variable low-resistance region may include a plurality of regions formed to be spaced apart from each other.

In this embodiment, the source may have a shape elongated along the plurality of variable low resistance regions.

In this embodiment, the drain may have a shape elongated along the plurality of variable low resistance regions.

In this embodiment, the number of variable low-resistance regions formed may be determined through control of the gate.

In this embodiment, the variable low-resistance region may be created or destroyed according to the control of the polarization region by controlling an electric field through the gate.

In this embodiment, the variable low resistance region may be maintained even when an electric field applied through the gate is removed.

In this embodiment, the variable low resistance region may be formed to include a linear shape around the gate.

Another embodiment of the present invention is a base comprising a spontaneously polarizable material, a gate disposed adjacent to the base, a source spaced apart from the gate and connected to the variable low resistance region; and forming a polarization region of the base by applying an electric field to the base through the gate in a variable low resistance region-based memory device including a drain spaced apart from the gate and connected to the variable low resistance region. Forming a variable low-resistance region including a region having a lower electrical resistance than other adjacent regions corresponding to the boundary of the polarization region so that the flow of current between the source and the drain is formed through the variable low-resistance region. Disclosed is a variable low-resistance region-based memory device control method comprising a.

In this embodiment, the variable low-resistance region may include forming a plurality of them to be spaced apart from each other.

In this embodiment, the number of variable low-resistance regions formed may be determined through control of the gate.

In the present embodiment, a step of measuring a current between the source and the drain according to the number of variable low-resistance regions formed while controlling the gate may be included.

In this embodiment, a step of controlling an electric field through the gate to generate or disappear the variable low-resistance region according to the control of the polarization region may be included.

Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

An electronic circuit using a variable low resistance region and a control method thereof according to the present invention can be easily applied to various applications.

1 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention.
2 is a cross-sectional view taken along line II-II of FIG. 1;
FIG. 3 is an enlarged view of K in FIG. 2 .
4A to 4C are views for explaining a control method related to the electronic circuit of FIG. 1 . 5 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.
FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5 .
7A to 7D are views for explaining a method for controlling a current path range in relation to the electronic circuit of FIG. 5 .
8 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention.
9 is a cross-sectional view taken along line II-II of FIG. 8 .
10 to 14 are diagrams for explaining the operation of the electronic circuit of FIG. 8 .
15 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.
FIG. 16 is a cross-sectional view taken along line V-V of FIG. 15 .
17 is a schematic plan view illustrating a memory device according to another exemplary embodiment of the present invention.
18 is a cross-sectional view taken along line VI-VI of FIG. 17;
19 is a graph showing a relationship between voltage and current between a first region and a variable low resistance region.
20 is a cross-sectional view of a variable low resistance region memory device according to another exemplary embodiment of the present invention.
21 is a cross-sectional view of a variable low resistance region memory device according to another exemplary embodiment of the present invention.
22 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.
23 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.
24 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.
25 and 26 are diagrams for explaining a variable low resistance region memory device according to another exemplary embodiment of the present invention.
27 to 30 are diagrams for explaining a variable low resistance region memory device according to another exemplary embodiment of the present invention.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to embodiments of the present invention shown in the accompanying drawings.

Since the present invention can apply various transformations and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and methods for achieving them will become clear with reference to the embodiments described later in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when describing with reference to the drawings, the same or corresponding components are assigned the same reference numerals, and overlapping descriptions thereof will be omitted. .

In the following embodiments, terms such as first and second are used for the purpose of distinguishing one component from another component without limiting meaning.

In the following examples, expressions in the singular number include plural expressions unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have mean that features or components described in the specification exist, and do not preclude the possibility that one or more other features or components may be added.

In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present invention is not necessarily limited to the illustrated bar.

In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of the Cartesian coordinate system, and may be interpreted in a broad sense including these. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

When an embodiment is otherwise implementable, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order reverse to the order described.

1 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and FIG. 3 is an enlarged view of K in FIG.

Referring to FIGS. 1 and 2 , the electronic circuit 10 of this embodiment may include an active layer 11 , an applied electrode 12 , and a variable low resistance region VL.

The active layer 11 may include a spontaneously polarizable material. For example, the active layer 11 may include an insulating material and a ferroelectric material. That is, the active layer 11 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the active layer 11 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 , BiFe 3} , PbTiO 3 , PbZrO 3 , and SrBi 2 Ta 2 O 9 .

In addition, as another example, the active layer 11 has an ABX3 structure, A may include an alkyl group of CnH2n+1, and at least one material selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B may include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the active layer 11 may include CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _{3 ,} CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( including NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

The active layer 11 may be formed using various other ferroelectric materials, and descriptions of all examples thereof will be omitted. In addition, when forming the active layer 11, ferroelectric materials may be doped with various other materials to include additional functions or improve electrical characteristics.

The active layer 11 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the active layer 11 may maintain a polarized state even when the applied electric field is removed.

The application electrode 12 may be formed to apply an electric field to the active layer 11 , and may apply, for example, a voltage to the active layer 11 .

As an optional embodiment, the application electrode 12 may be formed to contact the upper surface of the active layer 11 .

In addition, the application electrode 12 may be formed to apply voltages of various sizes to the active layer 11 and to control the voltage application time.

As an alternative embodiment, the applying electrode 12 may be a gate electrode.

For example, the application electrode 12 may be electrically connected to a power source (not shown) or a power controller.

The applying electrode 12 may include various materials and may include a material having high electrical conductivity. For example, the application electrode 12 may be formed using various metals.

For example, the application electrode 12 can be formed to contain aluminum, chromium, titanium, tantalum, molybdenum, tungsten, neodymium, scandium or copper. Alternatively, it may be formed using an alloy of these materials or a nitride of these materials.

Also, as an optional embodiment, the applied electrode 12 may include a laminate structure.

Although not shown, as an optional embodiment, one or more insulating layers may be further disposed between the applying electrode 12 and the active layer 11 .

The variable low-resistance region VL is a region formed in the active layer 11 and is a region through which current can flow. Also, as shown in FIG. 1 , it can be formed as a current path having a linear shape around the applying electrode 12 . there is.

Specifically, the variable low resistance region VL is a region in which the electrical resistance is lower than other regions adjacent to the variable low resistance region VL among the regions of the active layer 11 .

In addition, after forming the variable low resistance region VL through the applying electrode 12, even if the electric field through the applying electrode 12 is removed, for example, even if the voltage is removed, the polarization state of the active layer 11 remains. Since the variable low resistance region VL is maintained, a state in which a current path is formed can be maintained.

Through this, various electronic circuits can be configured.

The variable low-resistance region VL has a height HVL, and this height HVL may correspond to the entire thickness of the active layer 11 .

The height HVL of the variable low resistance region VL may be proportional to the strength of the electric field when the electric field is applied through the applying electrode 12, for example, the magnitude of the voltage. At least, the magnitude of this electric field may be greater than the intrinsic coercive electric field of the active layer 11 .

The variable low-resistance region VL is a region formed when a voltage is applied to the active layer 11 through the applying electrode 12, and can be varied, for example created, extinguished, or moved through the control of the applied electrode 12. .

The active layer 11 may include a first polarization region 11F having a first polarization direction, and the variable low resistance region VL may be formed at a boundary of the first polarization region 11F.

In addition, a second polarization region 11R having a second polarization direction may be included adjacent to the first polarization region 11F, and the variable low resistance region VL is at the boundary of the second polarization region 11R. can be formed The second direction may be at least a direction different from the first direction, for example, a direction opposite to the first direction.

For example, the variable low resistance region VL may be formed between the first polarization region 11F and the second polarization region 11R.

The variable low-resistance region VL may have a width WVL in one direction, which may be proportional to a moving distance of the variable low-resistance region VL.

Also, this width WVL may be the width of a region on a plane defined as the variable low resistance region VL, which may be said to correspond to the width of the first polarization region 11F.

In addition, the variable low resistance region VL may be formed to correspond to the entire side surface of the boundary line of the first polarization region 11F, and may have a thickness TVL1 in a direction away from the side surface of the first polarization region 11F. there is.

As an alternative embodiment, this thickness TVL1 may be between 0.1 and 0.3 nanometers.

4A to 4C are diagrams for explaining a method for controlling a current path range for the electronic circuit of FIG. 1 .

Referring to FIG. 4A , the active layer 11 may include a second polarization region 11R having a second polarization direction. As an optional embodiment, a polarization state of the active layer 11 as shown in FIG. 4A may be formed by applying an initialization electric field through the applying electrode 12 .

Then, referring to FIG. 4B , a first polarization region 11F is formed in the active layer 11 . As a specific example, the first polarization region 11F may be first formed in an area overlapping the applying electrode 12 to correspond to the width of the applying electrode 12 .

The height HVL of the first polarization region 11F is greater than the coercive electric field of the active layer 11 through the applied electrode 12 and corresponds to at least the entire thickness of the active layer 11. An electric field may be applied to the active layer 11 .

By applying an electric field through the applying electrode 12, the polarization direction of one region of the second polarization region 11R of the active layer 11 may be changed to the first polarization region 11F.

As an alternative embodiment, the growth rate of the first polarization region 11F in the height (HVL) direction may be very fast, for example, it may grow with a speed of 1 km/sec (sec).

Then, when the electric field is continuously maintained through the applying electrode 12, that is, as time elapses, the first polarization region 11F moves in the horizontal direction H, that is, in the direction orthogonal to the height HVL, and increases in size. can That is, the region of the second polarization region 11R can be gradually converted into the first polarization region 11F.

As an optional embodiment, the growth rate of the first polarization region 11F in the horizontal direction H may be very fast, for example, it may grow with a speed of 1 m/sec (sec).

Through this, it is possible to control the size of the variable low-resistance region VL. Since this size is, for example, the width of the variable low-resistance region VL and corresponds to the growth distance of the first polarization region 11F, the growth speed and the electric field It can be proportional to the holding time. For example, the growth distance may be proportional to the product of the growth rate and the holding time of the electric field.

In addition, the growth rate of the first polarization region 11F may be proportional to the sum of the growth rate in the height (HVL) direction and the growth rate in the horizontal direction (H).

Therefore, the size of the variable low-resistance region VL can be adjusted as desired by controlling the holding time of the electric field.

Specifically, as shown in FIG. 4C , the first polarization region 11F spreads out and becomes large, and accordingly, the variable low-resistance region VL may also move in a direction away from the applied electrode 12 .

In this embodiment, an electric field is applied to the active layer through an applied electrode to form a first polarization region having a first polarization direction different from the second polarization direction in the active layer, and at the boundary between the first polarization region and the second polarization region A corresponding variable low resistance region may be formed. Such a variable low-resistance region is a region of low resistance and is a region of reduced resistance, and can be a path of current, so that an electronic circuit can be easily formed.

In addition, in this embodiment, the height of the variable low resistance region can be determined by controlling the magnitude of the electric field through the applied electrode, for example, by controlling the magnitude of the voltage, and specifically controlled to have a height corresponding to the entire thickness of the active layer. can do.

In addition, the size, eg, width, of the variable low resistance region can be determined by controlling the time for maintaining the electric field through the applied electrode. Through the control of the size of the variable low-resistance region, the size of the current flow path can be easily controlled.

In addition, since the polarization state of the polarization region is maintained even when the electric field through the applied electrode is removed, the current path can be easily maintained. In the resistance region, resistance may be lowered so that current may not flow.

Through this, it is possible to control the extinction of the path of the current, and as a result, it is possible to easily control the flow of the current.

The electronic circuit of this embodiment can be controlled and used for various purposes. For example, one or more electrodes can be connected to contact a variable low resistance region.

5 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5 .

Referring to FIGS. 5 and 6 , the electronic circuit 20 of this embodiment may include an active layer 21 , an applied electrode 22 , and variable low resistance regions VL1 , VL2 , and VL3 .

The active layer 21 may include a spontaneously polarizable material. For example, the active layer 21 may include an insulating material and a ferroelectric material. That is, the active layer 21 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the active layer 21 may include a perovskite-based material, and since detailed descriptions are the same as those of the above-described embodiment, they will be omitted.

The applying electrode 22 may be formed to apply an electric field to the active layer 21 , and for example, a voltage may be applied to the active layer 21 . Since specific details are the same as those of the above-described embodiment, they are omitted.

The variable low-resistance regions VL1 , VL2 , and VL3 may include a first variable low-resistance region VL1 , a second variable low-resistance region VL2 , and a third variable low-resistance region VL3 .

The first variable low-resistance region VL1 may have a larger width than the second variable low-resistance region VL2, and the second variable low-resistance region VL2 may have a larger width than the third variable low-resistance region VL3. there is. For example, the region surrounded by the first variable low resistance region VL1 has a larger width than the region surrounded by the second variable low resistance region VL2, and the region surrounded by the second variable low resistance region VL2 has a third variable resistance region. It may have a larger width than the area surrounded by the low resistance area VL3.

As an optional embodiment, the first variable low-resistance region VL1 is disposed outside the second variable low-resistance region VL2, and the second variable low-resistance region VL2 is located outside the third variable low-resistance region VL3. can be placed in

The first variable low-resistance region VL1, the second variable low-resistance region VL2, and the third variable low-resistance region VL3 are regions formed in the active layer 21 and are regions through which current can flow, and the current having a linear shape It can be formed with the path of

Specifically, the first variable low-resistance region VL1, the second variable low-resistance region VL2, and the third variable low-resistance region VL3 are the first variable low-resistance region VL1 of the active layer 21, This region has lower electrical resistance than other regions adjacent to the second variable low resistance region VL2 and the third variable low resistance region VL3.

In addition, after forming the first variable low-resistance region VL1, the second variable low-resistance region VL2, and the third variable low-resistance region VL3 through the applying electrode 22, the Since the polarization state of the active layer 21 is maintained even if the electric field is removed, for example, the voltage is removed, the first variable low-resistance region VL1, the second variable low-resistance region VL2, and the third variable low-resistance region (VL3) is maintained, and a state of forming a current path can be maintained.

Through this, various electronic circuits can be configured. For example, it may constitute at least a part of a memory element capable of storing one or more data.

The variable low-resistance regions VL1 , VL2 , and VL3 have a height HVL, and this height HVL may correspond to the entire thickness of the active layer 21 .

The active layer 21 may include first polarization regions 21F1 and 21F3 having a first polarization direction, and the variable low resistance regions VL1 , VL2 and VL3 are boundaries of the first polarization regions 21F1 and 21F3 . can be formed in

In addition, second polarization regions 21R1 and 21R2 having a second polarization direction may be included adjacent to the first polarization regions 21F1 and 21F3, and the variable low-resistance region VL may include such a second polarization region 21R1 , 21R2) may be formed at the boundary. The second direction may be at least a direction different from the first direction, for example, a direction opposite to the first direction.

For example, the first variable low-resistance region VL1 may be formed between the first polarization region 21F1 and the second polarization region 21R1.

Also, the second variable low resistance region VL2 may be formed between the first polarization region 21F1 and the second polarization region 21R2.

Also, the third variable low-resistance region VL3 may be formed between the first polarization region 21F3 and the second polarization region 21R2.

7A to 7D are views for explaining a method for controlling a current path range in relation to the electronic circuit of FIG. 5 .

Referring to FIG. 7A , the active layer 21 may include a second polarization region 21R having a second polarization direction. As an optional embodiment, a polarization state of the active layer 21 as shown in FIG. 7A may be formed by applying an initialization electric field through the applying electrode 22 .

Then, referring to FIG. 7B , a first polarization region 21F is formed in the active layer 21 . As a specific example, a first polarization region 21F may be first formed in an area overlapping the applying electrode 22 to correspond to the width of the applying electrode 22, and then grow in a horizontal direction to form a state as shown in FIG. 7B. In addition, the first polarization region 21R of FIG. 7A may be reduced to change to the first polarization region 21R1 as shown in FIG. 7B.

A first variable low resistance region VL1 may be formed between the first polarization region 21F and the second polarization region 21R1.

Then, referring to FIG. 7C , an electric field opposite to that of FIG. 7B is applied to convert the polarization direction of a portion of the first polarization region 21F to the second polarization region 21R2 having a polarization direction in the second direction. can For example, a second polarization region 21R2 having a polarization direction in a second direction opposite to the first polarization direction of the first polarization region 21F may be formed.

In addition, through this, the first polarization region 21F of FIG. 7B may be reduced in size and changed to the first polarization region 21F1 shown in FIG. 7C.

A second variable low resistance region VL2 may be formed between the second polarization region 21R2 and the first polarization region 21F1.

Since this polarization state is maintained, the first variable low-resistance region VL1 may be maintained as it is.

Then, referring to FIG. 7D , by applying an electric field in a direction opposite to that of FIG. 7C , the polarization direction of a portion of the second polarization region 21R2 is converted into a first polarization region 21F3 having a polarization direction in the first direction. can do. For example, a first polarization region 21F3 having a polarization direction of a first direction opposite to the second polarization direction of the second polarization region 21R2 may be formed.

Also, through this, the size of the second polarization region 21R2 of FIG. 7C may be reduced to change into the second polarization region 21R2 shown in FIG. 7D.

A third variable low resistance region VL3 may be formed between the second polarization region 21R2 and the first polarization region 21F3.

Since this polarization state is maintained, the first variable low-resistance region VL1 and the second variable low-resistance region VL2 are maintained, and a third variable low-resistance region VL3 may be added.

In this embodiment, an electric field is applied to the active layer through an applied electrode to form a first polarization region having a first polarization direction different from the second polarization direction in the active layer, and at the boundary between the first polarization region and the second polarization region A corresponding variable low resistance region may be formed. Such a variable low-resistance region is a region of low resistance and is a region of reduced resistance, and can be a path of current, so that an electronic circuit can be easily formed.

In addition, in this embodiment, the magnitude of the electric field through the applied electrode can be controlled and the direction of the electric field can be controlled, and through this, a plurality of first polarization regions or a plurality of second polarization regions can be formed with respect to the active layer.

A plurality of variable low-resistance regions may be formed on the boundary line between the plurality of first polarization regions or the plurality of second polarization regions. Since each of the plurality of variable low-resistance regions can form a current path, electronic circuits of various types and purposes can be easily created and controlled.

For example, various current paths can be formed by selectively applying the number of variable low-resistance regions centered on the applied electrode, and a memory that stores various data according to these current paths can be implemented.

8 is a schematic plan view illustrating an electronic circuit according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line II-II of FIG. 8 .

Referring to FIGS. 8 and 9 , the electronic circuit 100 of this embodiment may include an active layer 110, an applied electrode 120, a variable low resistance region VL, and one or more connection electrode parts 131 and 132. there is.

The active layer 110 may include a spontaneously polarizable material. For example, the active layer 110 may include an insulating material and a ferroelectric material. That is, the active layer 110 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the active layer 110 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 , BiFe 3} , PbTiO 3 , PbZrO 3 , and SrBi 2 Ta 2 O 9 .

In addition, as another example, the active layer 110 has an ABX3 structure, A may include an alkyl group of CnH2n+1, and at least one material selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B may include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the active layer 110 may include CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _{3 ,} CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( including NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

Since the active layer 110 can be formed using various other ferroelectric materials, descriptions of all examples thereof will be omitted. In addition, when forming the active layer 110, the ferroelectric material may be doped with various other materials to include additional functions or improve electrical characteristics.

The active layer 110 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the active layer 110 may maintain a polarized state even when the applied electric field is removed.

The applying electrode 120 may be formed to apply an electric field to the active layer 110 , and may apply, for example, a voltage to the active layer 110 .

As an optional embodiment, the application electrode 120 may be formed to contact the upper surface of the active layer 110 .

In addition, the application electrode 120 may be formed to apply voltages of various sizes to the active layer 110 and to control the voltage application time.

As an optional embodiment, the applying electrode 120 may be a gate electrode.

For example, the application electrode 120 may be electrically connected to a power source (not shown) or a power controller.

The applying electrode 120 may include various materials and may include a material having high electrical conductivity. For example, the application electrode 120 may be formed using various metals.

For example, the application electrode 120 may be formed to contain aluminum, chromium, titanium, tantalum, molybdenum, tungsten, neodymium, scandium, or copper. Alternatively, it may be formed using an alloy of these materials or a nitride of these materials.

Also, as an optional embodiment, the applied electrode 120 may include a laminate structure.

The connection electrode parts 131 and 132 may include one or more electrode members, and may include, for example, a first connection electrode member 131 and a second connection electrode member 132 .

The connecting electrode units 131 and 132 may be formed on the active layer 110, for example, formed on the upper surface of the active layer 110 to be spaced apart from the application electrode 120, and as an optional embodiment, the active layer 110 ) can be formed to come into contact with.

The first connection electrode member 131 and the second connection electrode member 132 may be formed using various conductive materials. For example, the first connection electrode member 131 and the second connection electrode member 132 may be formed to contain aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten.

As an optional embodiment, the first connection electrode member 131 and the second connection electrode member 132 may include a structure in which a plurality of conductive layers are stacked.

As an optional embodiment, the first connection electrode member 131 and the second connection electrode member 132 may be formed using a conductive metal oxide, for example, indium oxide (eg, In ₂ O ₃ ) or tin oxide. (eg SnO ₂ ), zinc oxide (eg ZnO), indium oxide tin oxide alloy (eg In ₂ O ₃ —SnO ₂ ) or indium oxide zinc oxide alloy (eg In ₂ O ₃ —ZnO) can form

As an optional embodiment, the connection electrode units 131 and 132 may be terminal members including input and output of electrical signals.

Also, as a specific example, the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode units 131 and 132 may include a source electrode or a drain electrode.

10 to 14 are diagrams for explaining the operation of the electronic circuit of FIG. 8 .

10 is a view showing a state in which a first electric field is applied through the applying electrode 120, FIG. 11 is a cross-sectional view taken along line VIII-VIII of FIG. 10, and FIG. 12 is an enlarged view of K in FIG. to be.

Referring to FIGS. 10 to 14 , when a first electric field is applied to the active layer 110 through the applying electrode 120 , at least one region of the active layer 110 may include a polarization region 110F.

The polarization region 110F may have a shape surrounding the applying electrode 120 with the applying electrode 120 as a center. The polarization region 110F may have a boundary line.

The first variable low-resistance region VL1 may be formed in an area corresponding to the side of the boundary line. Referring to FIG. 10 , the applied electrode 120 may be formed in a linear shape surrounding the applying electrode 120 .

For example, the first variable low-resistance region VL1 may have a first width WVL1 in one direction to surround the applying electrode 120 .

In addition, the first variable low-resistance region VL1 may be formed to correspond to the entire side surface of the boundary line of the polarization region 110F, and may have a thickness TVL1 in a direction away from the side surface of the polarization region 110F.

As an alternative embodiment, this thickness TVL1 may be between 0.1 and 0.3 nanometers.

As an optional embodiment, a process of applying an initialization electric field to the active layer 110 may proceed before the first voltage is applied to the active layer 110 through the applying electrode 120 .

Through the process of applying such an initialization electric field to the active layer 110, a step of converting all regions of the active layer 110 to polarization in a direction different from that of the polarization region 110F, for example, a polarization region in the opposite direction. .

Then, a polarization region 110F may be formed in one region by applying an electric field in the opposite direction thereto.

The first variable low-resistance region VL1 formed at the boundary of the polarization region 110F of the active layer 110 may change to a region having lower resistance than other regions of the active layer 110 . For example, the first variable low-resistance region VL1 may have a lower resistance than the polarization region 110F of the active layer 110 and a region of the active layer 110 surrounding the first variable low-resistance region VL1.

Through this, the first variable low-resistance region VL1 may form a passage of current.

As an optional embodiment, the first variable low-resistance region VL1 may correspond to one region of a plurality of domain walls provided in the active layer 110 .

In addition, the first variable low-resistance region VL1 may be continuously maintained when the polarization state of the polarization region 110F of the active layer 110 is maintained. That is, even if the first voltage applied to the active layer 110 through the applying electrode 120 is removed, the state of the variable low resistance region VL1 , that is, the low resistance state may be maintained.

As shown in FIGS. 10 and 11 , a current passage may be formed through the first variable low resistance region VL1 . However, since the connection electrode parts 131 and 132 do not correspond to the first variable low resistance region VL1, current may not flow through the connection electrode parts 131 and 132.

FIG. 13 is a view showing a state in which the first electric field is maintained for a predetermined period of time through the applying electrode 120, and FIG. 14 is a cross-sectional view taken along line XI-XI of FIG. 13 .

Referring to FIGS. 13 and 14 , the holding time of the first electric field through the applying electrode 120 increases, and the polarization region 110F of FIGS. 10 and 11 moves in the horizontal direction, so that the polarization region 110F increases accordingly. A second variable low-resistance region VL2 larger than the first variable low-resistance region VL1 may be formed.

For example, the structure shown in FIGS. 13 and 14 may be formed by continuously maintaining the voltage applied in FIGS. 10 and 11 for a predetermined time.

The polarization region 110F may have a shape surrounding the applying electrode 120 with the applying electrode 120 as a center. The polarization region 110F may have a boundary line. The second variable low-resistance region VL2 may be formed in a region corresponding to a side surface of a boundary line of the polarization region 110F. Referring to FIG. 13 , the applied electrode 120 may be formed in a linear shape surrounding the applying electrode 120 .

For example, the second variable low resistance region VL2 may have a second width WVL2 in one direction to surround the applying electrode 120 , and the second width WVL2 is greater than the first width WVL1 . can That is, the second variable low-resistance region VL2 may go around the applying electrode 120 .

In addition, the second variable low-resistance region VL2 may be formed to correspond to the entire side surface of the boundary line of the polarization region 110F, and may have a thickness in a direction away from the side surface of the polarization region 110F. As such, the thickness may be between 0.1 and 0.3 nanometers.

The second variable low-resistance region VL2 formed at the boundary of the polarization region 110F of the active layer 110 may change to a region having lower resistance than other regions of the active layer 110 . For example, the second variable low resistance region VL2 may have a lower resistance than the polarization region 110F of the active layer 110 and the region of the active layer 110 around the second variable low resistance region VL2. That is, the resistance of the second variable low resistance region VL2 is lower than the resistance of the inner portion of the second variable low resistance region VL2 in the polarization region 110F. Also, the resistance of the second variable low resistance region VL2 may be lower than that of a portion outside the second variable low resistance region VL2 of the active layer 110 .

Through this, the second variable low-resistance region VL2 may form a passage of current.

As an optional embodiment, the second variable low-resistance region VL2 may correspond to one region of a plurality of domain walls provided in the active layer 110 .

In addition, the second variable low-resistance region VL2 may be continuously maintained when the polarization state of the active layer 110 is maintained. That is, even if the second voltage applied to the active layer 110 through the applying electrode 120 is removed, the state of the second variable low resistance region VL2 , that is, the low resistance state may be maintained.

Therefore, a passage of current can be formed through the second variable low resistance region VL2.

In addition, as a specific example, the connection electrode parts 131 and 132 are formed to correspond to the second variable low resistance region VL2, for example, the first connection electrode member 131 of the connection electrode parts 131 and 132 and The second connection electrode member 132 may be disposed to contact the upper surface of the second variable low resistance region VL2 while being spaced apart from each other.

Through this, current may flow through the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode parts 131 and 132 .

In addition, various electrical signals may be generated. For example, when the electric field in the state of FIGS. 13 and 14 is applied more continuously, that is, when the application time increases, the second variable low resistance region VL2 moves further, and the first connection electrode member 131 and the second variable low resistance region VL2 move further. 2 can escape the connecting electrode member 132. Accordingly, current may not flow through the first connection electrode member 131 and the second connection electrode member 132 .

In addition, as an optional embodiment, an initialization process for the entire active layer 110 may be performed.

Then, when an electric field is applied to the active layer 110 through the applying electrode 120 again, current flows through the first connecting electrode member 131 and the second connecting electrode member 132 of the connecting electrode parts 131 and 132. can

The electronic circuit of this embodiment can apply voltages of various sizes to the active layer through the application electrode, and can control the application time.

Through this, it is possible to form a polarization region in the active layer with a region of a desired size, and a variable low-resistance region can be formed at the boundary of the polarization region.

In order to correspond to such a variable low-resistance region, for example, when forming the connection electrode portion to be in contact, current can flow through the connection electrode portion, and even when the voltage is removed, the active layer containing the ferroelectric material can maintain a polarized state, and accordingly A fluctuating low-resistance region at the boundary can also be maintained so that current can continue to flow.

In addition, a voltage may be applied to the active layer through the applying electrode so that the variable low-resistance region is changed into a polarization region, and through this, current does not flow in the connection electrode portion through which the current flows.

The flow of current can be controlled by controlling the voltage of the applied electrode, and through the control of the flow of this current, the electronic circuit can be used for various purposes.

As an alternative embodiment, the electronic circuitry can be used as a memory.

For example, it can be used as a memory by defining the flow of current as 1 and non-flow as 0, and as a specific example, since current can flow even when the voltage is removed, it can also be used as a non-volatile memory.

In addition, the electronic circuit may constitute a circuit unit that generates and transmits various signals, and may also be used as a switching element.

In addition, since it can be applied to other parts requiring control of electrical signals with a simple structure, it can be applied to various fields such as variable circuits, CPUs, and bio chips.

15 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along line V-V of FIG. 15 .

Referring to FIGS. 15 and 16 , the electronic circuit 200 of this embodiment may include an active layer 210, an applied electrode 220, a variable low resistance region VL, and connection electrode parts 231 and 232.

For convenience of explanation, it will be described focusing on different points from the above-described embodiment.

The active layer 210 may include a spontaneously polarizable material. For example, the active layer 210 may include an insulating material and a ferroelectric material. That is, the active layer 210 may include a material having spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

A description of the material forming the active layer 210 may be the same as or modified from that described in the foregoing embodiment, and a detailed description thereof will be omitted.

The applying electrode 220 may be formed to apply an electric field to the active layer 210 , and for example, a voltage may be applied to the active layer 210 .

As an optional embodiment, the application electrode 220 may be formed to contact the upper surface of the active layer 210 .

A description of the material forming the applying electrode 220 may be the same as or modified from that described in the foregoing embodiment, and thus a detailed description thereof will be omitted.

The connection electrode parts 231 and 232 may include one or more electrode members, and may include, for example, a first connection electrode member 231 and a second connection electrode member 232 .

The connection electrode parts 231 and 232 may be formed on the active layer 210, and for example, on the surface opposite to the surface of the active layer 210 on which the applied electrode 220 is formed so as to be spaced apart from the applied electrode 220. can be formed

The application electrode 220 may be formed on an upper surface of the active layer 210 , and the connection electrode units 231 and 232 may be formed on a lower surface of the active layer 210 .

As an optional embodiment, the connection electrode parts 231 and 232 may be formed to contact the active layer 210 .

The first connection electrode member 231 and the second connection electrode member 232 may be formed using various conductive materials.

A description of materials forming the first connection electrode member 231 and the second connection electrode member 232 may be the same as or modified from those described in the foregoing embodiment, and thus a detailed description thereof will be omitted.

Referring to FIG. 16 , when a voltage is applied to the active layer 210 through the applying electrode 220 , at least one region of the active layer 210 may include a polarization region 210F.

The variable low-resistance region VL may be formed in an area corresponding to the side of the boundary of the polarization region 210F, and referring to FIG. can be formed as

For example, the variable low-resistance region VL2 may have a width in one direction to surround the applying electrode 220 .

In addition, the variable low-resistance region VL may be formed to correspond to the entire side surface of the boundary line of the polarization region 210F, and may have a thickness in a direction away from the side surface of the polarization region 210F. The thickness may be between 0.1 and 0.3 nanometers.

The variable low-resistance region VL formed at the boundary of the polarization region 210F of the active layer 210 may change to a region having lower resistance than other regions of the active layer 210 . For example, the variable low resistance region VL may have a lower resistance than the polarization region 210F of the active layer 210 and a region of the active layer 210 around the variable low resistance region VL.

Through this, the variable low resistance region VL may form a passage of current.

As an optional embodiment, the variable low-resistance region VL may correspond to one region of a plurality of domain walls provided in the active layer 210 .

In addition, the variable low-resistance region VL may be maintained as long as the polarization state of the active layer 210 is maintained. That is, even if the voltage applied to the active layer 210 through the applying electrode 220 is removed, the state of the variable low resistance region VL, that is, the low resistance state may be maintained.

A current path may be formed through the variable low resistance region VL.

In addition, as a specific example, the connection electrode parts 231 and 232 are formed to correspond to the variable low resistance region VL, for example, the first connection electrode member 231 and the second connection of the connection electrode parts 231 and 232 The electrode members 232 may be disposed to contact the lower surface of the variable low resistance region VL while being spaced apart from each other.

Through this, current may flow through the first connection electrode member 231 and the second connection electrode member 232 of the connection electrode parts 231 and 232 .

The electronic circuit of this embodiment can apply voltages of various sizes to the active layer through the application electrode, and can control the application time.

Through this, it is possible to form a polarization region in the active layer with a region of a desired size, and a variable low-resistance region can be formed at the boundary of the polarization region.

In addition, by forming an application electrode on one surface of the active layer and forming a connection electrode on the other surface, precise patterning and miniaturization of the electronic circuit can be easily performed.

The electronic device as described above may be implemented as a variable low-resistance region memory device as follows.

17 is a schematic plan view illustrating a memory device according to another exemplary embodiment of the present invention, and FIG. 18 is a cross-sectional view taken along line VI-VI of FIG. 17 .

17 and 18 , the variable low resistance region memory device 300 may include a base 310, a gate 320, a source 331 and a drain 332.

The base 310 may include the above-described active layer material, for example, a spontaneous polarization material. For example, the base 310 may include an insulating material and may include a ferroelectric material. That is, the base 310 may include a material having a spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the base 310 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 , BiFe 3} , PbTiO 3 , PbZrO 3 , and SrBi 2 Ta 2 O 9 .

In addition, as another example, the base 310 has an ABX3 structure, A may include an alkyl group of CnH2n+1, and at least one material selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B may include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the base 310 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _{3 ,} CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( including NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

Since the base 310 may be formed using various other ferroelectric materials, a description of all examples thereof will be omitted. In addition, when forming the base 310, the ferroelectric material may be doped with various other materials to include additional functions or improve electrical characteristics.

The base 310 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the base 310 may maintain a polarized state even when the applied electric field is removed.

The base 310 may include a first area 311 and a second area 312 positioned adjacent to each other in the X-Y plane direction. The first region 311 may have polarization in a first direction, and the first direction is the thickness direction of the base 310, that is, the direction in which the first region 311 and the second region 312 are disposed. may be in the Z-direction perpendicular to

The second region 312 is positioned adjacent to the first region 311 in a direction perpendicular to the thickness, that is, in an X-Y plane direction. It can have polarization aligned in two directions.

A gate 320 may be positioned on the second region 312 . Although not shown in the drawing, the gate 320 may be connected to a separate device to receive a gate signal.

The polarization of the second region 312 in the opposite direction to that of the first region 311 is made possible by the voltage applied to the gate 320 .

A variable low-resistance region 340 may be formed between the first region 311 and the second region 312 having polarizations in opposite directions. The variable low-resistance region 340 as described above becomes a region having very low resistance compared to the first region 311 and/or the second region 312, and current may flow through this region.

The variable low-resistance region 340 may be formed according to the following embodiment.

First, the base 310 including the spontaneously polarizable material may have polarization in the first direction as a whole. The entire base 310 is not necessarily limited to having polarization in the first direction, and at least a certain area of the base 310 facing the gate 320 may have polarization in the first direction. Optionally, polarization in the first direction may be formed by applying an initialization electric field to the gate 320 .

In this state, as an electric field is applied to the base 310 through the gate 320 by applying a first voltage to the gate 320 for a first time, a certain area opposite to the gate 320 is polarized in the second direction. It will change. The electric field applied to the gate 320 to change the direction of polarization may be controlled by the first voltage, that is, the first voltage is applied such that a coercive electric field greater than the coercive electric field of the spontaneously polarizable material forming the base 310 is applied. can be added.

The base 310 may have a first thickness t1. At this time, the second region 312 is formed over the entire first thickness t1, and the magnitude of the first voltage applied to the gate 320 can be adjusted according to the first thickness t1. According to an embodiment, the first thickness t1 and the magnitude of the first voltage applied to the gate 320 may be proportional to each other. That is, when the first thickness t1 is large, the first voltage may be increased.

As shown in FIG. 18 , the variable low-resistance region 340 may also be formed over the entire first thickness t1.

The area of the second region 312 formed in this way may be determined in proportion to the first time when the first voltage is applied to the gate 320 .

Therefore, in order to form the second region 312 of a desired area and/or size, an appropriate gate voltage, time, and first thickness t1 of the second region 312 for the corresponding ferroelectric material are required through experiments and/or calculations. can be determined in advance by

When the polarization direction of the second region 312 changes from the first direction to the second direction, a gap exists between the first region 311 having polarization in the first direction and the second region 312 having polarization in the second direction. A variable low-resistance region 340 having a predetermined width may be formed. The variable low-resistance region 340 may be formed around the gate 320 .

19 is a graph showing a relationship between voltage and current between a first region and a variable low resistance region.

Specifically, FIG. 19 shows a state in which current changes as the voltage increases in the first region and the variable low resistance region.

That is, in FIG. 19, (a) shows a state in which the current changes as the voltage increases in the variable low resistance region, and (b) shows a state in which the current changes as the voltage increases in the first region.

Since the resistance of the variable low-resistance region 340 is very small compared to that of the first region 311 , it can be seen that current flows smoothly according to voltage application.

The variable low-resistance region 340 formed as described above may not be erased over time.

The source 331 and the drain 332 are placed in contact with the variable low-resistance region 340 thus formed. In this case, current may flow from the source 331 to the drain 332 through the variable low resistance region 340 . Therefore, data can be written at this time, and can be read as 1, for example.

Optionally, the voltage applied to the variable low-resistance region 340 and the gate 320 may cause the polarization direction of the second region 312 to become the same as that of the first region 311, thereby erasing it.

That is, the polarization direction of the second region 312 may return to the first direction by applying the second voltage to the gate 320 . Thereafter, a second voltage may be maintained for a second time to grow a region in which the polarization is changed in the first direction in a planar direction, and the region in which the polarization is changed in the first direction passes through the variable low resistance region 340 to form the first When extending to the region 311 , the variable low resistance region 340 may disappear. In this case, current cannot flow from the source 331 to the drain 332, so data can be erased at this time and can be read as 0.

In this case, the second voltage may be a voltage different from the first voltage, and may have the same magnitude as the first voltage and a voltage of opposite polarity according to an embodiment. The second time period may be at least equal to or longer than the first time period.

The variable low-resistance region memory device formed as described above can be used as a non-volatile memory device because the above-described variable low-resistance region 340 can maintain its state even when power to the gate 320 is turned off.

Since the variable low-resistance region memory device can write/erase about 10 ¹² times, it can have a memory lifespan that is about 10 ⁷ times that of a memory device based on a conventional semiconductor device.

As for the memory speed, the variable low-resistance region memory device can be about 10 ⁻⁹ sec, so the memory speed can be increased by about 10 ⁶ times compared to memory devices based on conventional semiconductor devices.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and lifespan.

In addition, since the position where the variable low-resistance region 340 is formed can be adjusted according to the gate voltage and/or application time, it is possible to design various memory devices, and it is thinner than conventional ferroelectric memory devices using ferroelectrics. can achieve In addition, since the degree of freedom in memory design is increased, there is an advantage in that the degree of integration of devices can be increased.

As shown in FIG. 17, the variable low-resistance region 340 formed in this way may be formed in a closed loop shape centered on the gate 320. By arranging, the number of lines connecting the source 331 and the drain 332 may be two. However, it is not necessarily limited thereto, and if a gate is placed on one side of the base in a planar direction and a source and a drain are placed on the other two adjacent sides, the variable low-resistance region can be a single line connecting the source and drain.

The source 331 and the drain 332 as described above may be an electrode structure formed by being patterned on the base 310, but the present invention is not necessarily limited thereto, and although not shown in the drawings, the base 310 It may be in contact with the variable low resistance region 340 through a via hole formed in the covering insulating film.

20 is a cross-sectional view of a variable low resistance region memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 20 , the variable low resistance region memory device 400 includes a base 410 having a source 431 and a drain 432 formed on a substrate 430 and including a spontaneously polarizable material on the substrate 430 . ) can be placed. The substrate 430 may be formed of a semiconductor wafer, or a silicon wafer according to one embodiment. Also, the source 431 and the drain 432 may be formed by ion doping on a wafer. Of course, although not shown in the drawings, external signal lines may be connected to the source 431 and the drain 432 through separate vias.

In this structure, the gate voltage and the application time can be determined so that the variable low resistance region 440 can be positioned to correspond to the regions of the source 431 and the drain 432 formed on the substrate 430 .

The substrate 430 and the base 410 as described above may be bonded by a separate adhesive layer, but it is not necessarily limited thereto, and the base 410 may be formed on the substrate 430 . By implementing the base 410 as a thin film on the substrate 430 in this way, the memory device 400 can be further thinned, and the efficiency of the manufacturing process can be further increased because an existing memory device process can be used.

The above-described embodiments show the case where the first region and the second region have the same thickness, but the present invention is not necessarily limited thereto.

21 is a cross-sectional view of a variable low resistance region memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 21 , the variable low resistance region memory device 500 includes a base 510 having a source 531 and a drain 532 formed on a substrate 530 and including a spontaneously polarizable material on the substrate 530. ) can be placed. In the memory device 500 of the embodiment shown in FIG. 21 , the first region 511 may have a second thickness t2 greater than the first thickness t1 of the second region 512 . The second thickness t2 is a thickness at which the polarization direction is not switched by the voltage applied to the gate 520, and thus the variable low-resistance region 540 has the first thickness t1 and the second thickness ( t2) may be formed at a boundary.

As described above, since the voltage applied to the gate 520 can be set to a voltage at which polarization switching is performed with respect to the first thickness t1, a region formed with the second thickness t2 is formed in the base 510, thereby , the intensity of the voltage applied to the gate 520, and the time, the variable low-resistance region 540 is not formed in the second thickness t2, and the variable low-resistance region 540 is formed only in the region made of the first thickness t1. ) can be formed.

That is, as shown in FIG. 21 , the variable low resistance region 540 may be formed at a boundary between the first thickness t1 and the second thickness t2.

22 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 22 , the variable low resistance region memory device 600 includes a base 610 having a source 631 and a drain 632 formed on a substrate 630 and including a spontaneously polarizable material on the substrate 630 . ) can be placed. In the memory device 600 of the embodiment shown in FIG. 22, as in the embodiment shown in FIG. 21, the first region 611 has a second thickness t2 thicker than the first thickness t1 of the second region 612. can have

At this time, according to the time for which the voltage is applied to the gate 620, as can be seen in FIG. 22, the position is located on the inside where the first thickness t1 is formed from the boundary between the first thickness t1 and the second thickness t2. can do. Accordingly, in the memory device 600 having this structure, the source 631 and the drain 632 may be formed inside the boundary between the first thickness t1 and the second thickness t2. Accordingly, even if the formation position of the variable low-resistance region 640 is changed according to the change in the voltage of the gate 620 and/or the time, the variable low-resistance region 640 and the source 631/drain 632 are formed. can be electrically connected.

In the embodiments described above, the gate is formed adjacent to the base, but the present invention is not necessarily limited thereto.

23 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 23 , in the memory device 700 , another layer 750 may be further positioned between the base 710 and the gate 720 . The layer 750 may be an insulating layer, and may be a material different from a ferroelectric material forming the base 710 .

Even in this case, the polarization direction of the second region 712 can be switched under the influence of the electric field caused by the voltage applied to the gate 720. At this time, the gate 720 voltage and/or Alternatively, the time may be obtained in advance by experimentation and/or calculation.

24 is a cross-sectional view of a variable low resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 24 , the variable low-resistance region memory device 800 includes a base 810 having a source 831 and a drain 832 formed on a substrate 830 and including a spontaneously polarizable material on the substrate 830. ) can be placed.

According to the embodiment shown in FIG. 24, a first gate 821 facing the base 810 and a second gate 822 located on the opposite side of the first gate 821 with respect to the base 810 are included. can do.

In this case, the variable low resistance region 840 may be formed by switching the polarization direction of the second region 812 by the first gate 821 . Accordingly, data writing becomes possible.

The variable low-resistance region 840 may be removed by switching the polarization direction of the second region 812 by the second gate 822 again like the first region 811 . This makes it possible to erase data.

As such, data can be read as 0/1 by the first gate 821 and the second gate 822 .

All embodiments of the present specification described above are not limited to each illustrated embodiment, and can be applied in combination with each other, of course.

In addition, it goes without saying that these embodiments can be selectively applied or modified and applied to embodiments to be described later.

25 and 26 are diagrams for explaining a variable low resistance region memory device according to another exemplary embodiment of the present invention.

Referring first to FIG. 25 , the variable low resistance region memory device 900 may include a base 910 , a gate 920 , a source 931 and a drain 932 .

The base 910 may include the above-described active layer material, for example, a spontaneous polarization material. For example, the base 910 may include an insulating material and may include a ferroelectric material. That is, the base 910 may include a material having a spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the base 910 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 , BiFe 3} , PbTiO 3 , PbZrO 3 , and SrBi 2 Ta 2 O 9 .

In addition, as another example, the base 910 has an ABX3 structure, A may include an alkyl group of CnH2n+1, and at least one material selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B may include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. Specific examples are the same as those described in the foregoing embodiment, and thus are omitted.

The base 910 has spontaneous polarization, and the degree and direction of polarization can be controlled according to the application of an electric field. In addition, the base 910 may maintain a polarized state even when the applied electric field is removed.

A gate 920 may be positioned on the base 910 .

When a voltage is applied through the gate 920, the base 910 including the active layer material may include a first region, which is a polarization region in one direction, around the gate 920, and is adjacent to the first region. A second region having a polarization direction different from that of the first region may be included. Since the contents of the first area and the second area are similar to those described in the foregoing embodiments, a detailed description thereof will be omitted.

The first variable low-resistance region 941 may be formed between the first region and the second region having polarizations in opposite directions. The properties of the first variable low-resistance region 941 are the same as those of the variable low-resistance region described in the foregoing embodiments. As shown in FIG. 25 , when viewed from a direction perpendicular to the base 910 , the first variable low resistance region 941 is spaced apart from the gate 920 and is located on both sides of the gate 920 .

In this case, the size of the first region may be controlled by controlling the first voltage, and one end of the first variable low resistance region 941 may be connected to the source 931 and the other end to the drain 932. .

In this case, current may flow from the source 931 to the drain 932 through the first variable low resistance region 941 .

Also, referring to FIG. 26 , it is illustrated that a second variable low-resistance region 942 is formed inside the first variable low-resistance region 941 based on the gate 920 . Properties of the second variable low resistance region 942 are the same as those of the variable low resistance region described in the foregoing embodiments. As shown in FIG. 26 , when viewed from a direction perpendicular to the base 910 , the second variable low resistance region 942 is spaced apart from the gate 920 and is located on both sides of the gate 920 . The second variable low resistance region 942 is positioned between the gate 920 and the first variable low resistance region 941 .

One end of the second variable low resistance region 942 may be connected to the source 931 and the other end to the drain 932 .

The first variable low-resistance region 941 and the second variable low-resistance region 942 may be formed as a current path having a linear shape, and specifically, the first variable low-resistance region 941 and the second variable low-resistance region Reference numeral 942 is a region having lower electrical resistance than other adjacent regions.

The process of forming the first variable low-resistance region 941 and the second variable low-resistance region 942 may be applied in the same or similar manner as described in FIGS. 7A to 7D of the above-described embodiment.

For example, a voltage to the base 910 may be applied through the gate 920 to form a polarized state, and through this, the first variable low-resistance region 941 may be formed. Then, a second variable low-resistance region 942 spaced apart from the first variable low-resistance region 941 may be formed by applying an electric field in the opposite direction.

In addition, since this polarization state is maintained even when the voltage is removed from the gate 920, the first variable low-resistance region 941 and the second variable low-resistance region 942 may be maintained as they are.

As an optional embodiment, the thickness of the first variable low-resistance region 941 or the second variable low-resistance region 942 may be 0.1 to 0.3 nanometers. This thickness may be the thickness in the vertical axis direction based on FIG. 25 or 26 .

As an optional embodiment, the source 931 may be formed to be connected to both the first variable low resistance region 941 and the second variable low resistance region 942 . For example, the source 931 may have a structure elongated along one direction, and as a specific example, may be formed to be longer than the width of the gate 920 .

Also, the drain 932 may be formed to be connected to both the first variable low resistance region 941 and the second variable low resistance region 942 . For example, the drain 932 may have a structure extending in one direction, and as a specific example, may be formed to be longer than the width of the gate 920 .

The source 931 and the drain 932 may have a long structure so as to face each other on both sides with the gate 920 interposed therebetween.

The variable low-resistance region memory device formed as described above can be used as a non-volatile memory device because the variable low-resistance regions 941 and 942 can maintain their state even when power to the gate 920 is turned off, as described above.

Since the variable low-resistance region memory device can write/erase about 10 ¹² times, it can have a memory lifespan that is about 10 ⁷ times that of a memory device based on a conventional semiconductor device.

As for the memory speed, the variable low-resistance region memory device can be about 10 ⁻⁹ sec, so the memory speed can be increased by about 10 ⁶ times compared to memory devices based on conventional semiconductor devices.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and lifespan.

In addition, through control of the electric field through the gate 920, only the first variable low resistance region 941 is formed or both the first variable low resistance region 941 and the second variable low resistance region 942 are formed. you can control things

Meanwhile, when current flows between the source 931 and the drain 932, the current value when only the first variable low resistance region 941 is formed is the first variable low resistance region 941 and the second variable low resistance region 941. It may be different from the current value when all of the resistance regions 942 are formed, and may be small, for example.

Through this, the memory device 900 may store information of two pieces of information, for example, 1 or 0, as well as more three pieces of information, which may be referred to as 0, 1, and 2, respectively, for convenience.

That is, as shown in FIG. 26 , the case where current flows between the source 931 and the drain 932 through the first variable low-resistance region 941 and the second variable low-resistance region 942 can be referred to as 2.

As shown in FIG. 25 , when only the first variable low resistance region 941 is generated, a case in which current flows between the source 931 and the drain 932 through the first variable low resistance region 941 can be referred to as 1. .

In addition, the case where the first and second variable low-resistance regions 941 and 942 disappear by voltage control through the gate 920 and no current flows between the source 931 and the drain 932 is referred to as 0. can

That is, since the first variable low-resistance region 941 and the second variable low-resistance region 942 can be controlled and formed through the gate 920, the first variable low-resistance region 941 and the second variable low-resistance region 941 and the second variable low-resistance region 941 can be formed. A memory can be formed as three different types of information through current measurement according to the control of the resistance region 942 .

Through this, the degree of freedom in memory design is increased and high information can be integrated.

27 to 30 are diagrams for explaining a variable low resistance region memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 27 , the variable low resistance region memory device 1000 may include a base 1010, a gate 1020, a source 1031, and a drain 1032.

The base 1010 may include the above-described active layer material, for example, a spontaneous polarization material. For example, the base 1010 may include an insulating material and may include a ferroelectric material. That is, the base 1010 may include a material having a spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the base 1010 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 , BiFe 3} , PbTiO 3 , PbZrO 3 , and SrBi 2 Ta 2 O 9 .

In addition, as another example, the base 1010 has an ABX3 structure, A may include an alkyl group of CnH2n+1, and one or more materials selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, and B may include one or more materials selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. Specific examples are the same as those described in the foregoing embodiment, and thus are omitted.

The base 1010 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the base 1010 may maintain a polarized state even when the applied electric field is removed.

A gate 1020 may be positioned on the base 1010 .

When a voltage is applied through the gate 1020, the base 1010 including the active layer material may include a first region, which is a polarization region in one direction, around the gate 1020, and is adjacent to the first region. A second region having a polarization direction different from that of the first region may be included. Details of the first area and the second area may be formed similarly to those described in the foregoing embodiments, and detailed descriptions thereof are omitted.

The first variable low-resistance region 1041 may be formed between the first region and the second region having polarizations in opposite directions.

In this case, the size of the first region may be controlled by controlling the first voltage, and one end of the first variable low resistance region 1041 may be connected to the source 1031 and the other end to the drain 1032. .

In this case, current may flow from the source 1031 to the drain 1032 through the first variable low-resistance region 1041 .

Also, referring to FIG. 28 , it is illustrated that a second variable low-resistance region 1042 is formed inside the first variable low-resistance region 1041 based on the gate 1020 .

One end of the second variable low resistance region 1042 may be connected to the source 1031 and the other end to the drain 1032 .

The first variable low-resistance region 1041 and the second variable low-resistance region 1042 may be formed as a current path having a linear shape, and specifically, the first variable low-resistance region 1041 and the second variable low-resistance region Reference numeral 1042 is a region having lower electrical resistance than other adjacent regions.

Also, referring to FIG. 29 , it is illustrated that a third variable low-resistance region 1043 is formed inside the second variable low-resistance region 1042 based on the gate 1020 .

One end of the third variable low resistance region 1043 may be connected to the source 1031 and the other end to the drain 1032 .

The first variable low-resistance region 1041, the second variable low-resistance region 1042, and the third variable low-resistance region 1043 may be formed as a current path having a linear shape, and specifically, the first variable low-resistance region. 1041, the second variable low-resistance region 1042, and are regions having lower electrical resistance than other adjacent regions.

Also, referring to FIG. 30 , it is illustrated that a fourth variable low-resistance region 1044 is formed inside the third variable low-resistance region 1043 based on the gate 1020 .

One end of the fourth variable low resistance region 1044 may be connected to the source 1031 and the other end to the drain 1032 .

The first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043, and the fourth variable low-resistance region 1044 may be formed as a current path having a linear shape. Specifically, the first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043, and the fourth variable low-resistance region 1044 have higher electrical resistance than other adjacent regions. This is the lowered area.

The formation process of the first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043, and the fourth variable low-resistance region 1044 is shown in FIG. 7A of the above-described embodiment. The same or similar can be applied to the bar described in FIG. 7D.

For example, a voltage to the base 1010 may be applied through the gate 1020 to form a polarized state, and through this, the first variable low resistance region 1041 may be formed. Then, a second variable low-resistance region 1042 spaced apart from the first variable low-resistance region 1041 may be formed by applying an electric field in the opposite direction. Also, a third variable low-resistance region 1043 spaced apart from the second variable low-resistance region 1042 may be formed by applying an electric field in the opposite direction. In addition, a fourth variable low-resistance region 1044 spaced apart from the third variable low-resistance region 1043 may be formed by applying an electric field in the opposite direction.

In addition, since this polarization state is maintained even when the voltage is removed from the gate 1020, the first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043 and the fourth variable low-resistance region 1041 are formed. The variable low resistance region 1044 may be maintained as it is.

As an optional embodiment, the thickness of the first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043, or the fourth variable low-resistance region 1044 is 0.1 to 0.3 may be nanometers. This thickness may be the thickness in the vertical axis direction based on FIGS. 27 to 30 .

As an alternative embodiment, the source 1031 may include the first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043, or the fourth variable low-resistance region 1044. It can be formed to be connected. For example, the source 1031 may have a structure elongated along one direction, and as a specific example, may be formed to be longer than the width of the gate 1020 .

In addition, the drain 1032 is formed to be connected to all of the first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043, or the fourth variable low-resistance region 1044. It can be. For example, the drain 1032 may have a structure extending in one direction, and as a specific example, may be formed to be longer than the width of the gate 1020 .

The source 1031 and the drain 1032 may have a long structure so as to face each other on both sides with the gate 1020 interposed therebetween.

The variable low-resistance region memory element formed as described above comprises the first variable low-resistance region 1041, the second variable low-resistance region 1042, the third variable low-resistance region 1043, or the fourth variable low-resistance region 1041 as described above. Since the region 1044 can maintain its state even when power to the gate 1020 is turned off, it can be used as a non-volatile memory device.

Since the variable low-resistance region memory device can write/erase about 10 ¹² times, it can have a memory lifespan that is about 10 ⁷ times that of a memory device based on a conventional semiconductor device.

As for the memory speed, the variable low-resistance region memory device can be about 10 ⁻⁹ sec, so the memory speed can be increased by about 10 ⁶ times compared to memory devices based on conventional semiconductor devices.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and lifespan.

In addition, only the first variable low-resistance region 1041 is formed through the control of the electric field through the gate 1020, the first and second variable low-resistance regions 1041 and 1042 are formed, or the first, second, Three variable low resistance regions 1041, 1042, and 1043 may be formed, or first, second, third, and fourth variable low resistance regions 1041, 1042, 1043, and 1044 may be formed.

Meanwhile, when current flows between the source 1031 and the drain 1032, the current value when only the first variable low resistance region 1041 is formed and the first and second variable low resistance regions 1041 and 1042 are Current values when formed, current values when first, second, and third variable low resistance regions 1041, 1042, and 1043 are formed, and first, second, third, and fourth variable low resistance regions 1041, 1042, and 1043 , 1044) may all be different from each other.

As a specific example, the current value when only the first variable low resistance region 1041 is formed is smaller than the current value when the first and second variable low resistance regions 1041 and 1042 are formed. The current value when the regions 1041 and 1042 are formed is smaller than the current value when the first, second and third variable low resistance regions 1041, 1042 and 1043 are formed, and the first, second and third variable low resistance regions are formed. A current value when the regions 1041 , 1042 , and 1043 are formed may be smaller than a current value when the first, second, third, and fourth variable low resistance regions 1041 , 1042 , 1043 , and 1044 are formed.

Through this, the present memory device 1000 not only stores information as two pieces of information, for example, 1 or 0, but also stores more than five pieces of information, which will be referred to as 0, 1, 2, 3, and 4, respectively, for convenience. can

That is, as shown in FIG. 30, the case where current flows between the source 1031 and the drain 1032 through the first, second, third, and fourth variable low-resistance regions 1041, 1042, 1043, and 1044 can be referred to as 4. there is.

As shown in FIG. 29 , a case in which current flows between the source 1031 and the drain 1032 through the first, second, and third variable low-resistance regions 1041, 1042, and 1043 may be referred to as 3.

As shown in FIG. 28 , a case in which current flows between the source 1031 and the drain 1032 through the first and second variable low-resistance regions 1041 and 1042 may be referred to as 2.

As shown in FIG. 27 , a case in which current flows between the source 1031 and the drain 1032 through the first variable low-resistance region 1041 may be referred to as 1.

In addition, the first, second, third, and fourth variable low-resistance regions 1041, 1042, 1043, and 1044 are extinguished by voltage control through the gate 1020, and the flow of current between the source 1031 and the drain 1032 is reduced. The case where it is not formed is called 0.

That is, since the first, second, third, and fourth variable low-resistance regions 1041, 1042, 1043, and 1044 can be controlled and formed through the gate 1020, these first, second, third, and fourth variable low-resistance regions Through the measurement of the current according to the control of (1041, 1042, 1043, 1044), it is possible to form a memory as five different pieces of information.

Through this, the degree of freedom in memory design is increased and high information can be integrated.

In this way, the present invention has been described with reference to the embodiments shown in the drawings, but this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

Specific executions described in the embodiments are examples, and do not limit the scope of the embodiments in any way. In addition, if there is no specific reference such as "essential" or "important", it may not necessarily be a component necessary for the application of the present invention.

In the specification of the embodiments (particularly in the claims), the use of the term "above" and similar indicating terms may correspond to both singular and plural. In addition, when a range is described in the examples, it includes the invention to which individual values belonging to the range are applied (unless there is no description to the contrary), and it is as if each individual value constituting the range is described in the detailed description. . Finally, if there is no explicit description or description of the order of steps constituting the method according to the embodiment, the steps may be performed in an appropriate order. Examples are not necessarily limited according to the order of description of the steps. The use of all examples or exemplary terms (eg, etc.) in the embodiments is simply to describe the embodiments in detail, and the scope of the embodiments is limited due to the examples or exemplary terms unless limited by the claims. It is not. In addition, those skilled in the art can appreciate that various modifications, combinations and changes can be made according to design conditions and factors within the scope of the appended claims or equivalents thereof.

10, 100, 200: electronic circuit
11, 21, 110, 210: active layer
12, 120, 220: application electrode
131, 132, 231, 232: connection electrode part
VL: variable low resistance region
300, 400, 500, 600, 700, 800, 900, 1000: memory element
320, 420, 520, 620, 720, 821, 822, 920, 1020: gate

Claims (4)

a base comprising a spontaneously polarizable material;
a gate disposed adjacent to the base;
a polarization region formed in the base by applying an electric field to the base through the gate;
one or more variable low-resistance regions corresponding to the boundary of the polarization region and spaced apart from the gate and including a region having a lower electrical resistance than other adjacent regions;
a source spaced apart from the gate and connected to the variable low resistance region; and
A drain spaced apart from the gate and connected to the variable low resistance region;
the variable low-resistance region includes at least a first variable low-resistance region and a second variable low-resistance region;
The first variable low-resistance region is disposed to be connected to the source and the drain at both sides of the gate with respect to the plane of the base so as to be spaced apart from the gate;
The second variable low-resistance region is spaced apart from the gate and is disposed to be connected to the source and the drain between the gate and the first variable low-resistance region on both sides of the gate with respect to the plane of the base,
An edge of at least one side connected to the source and the drain of the first variable low resistance region is formed parallel to an edge of at least one side connected to the source and the drain of the second variable low resistance region. , a memory device based on a variable low-resistance region. a base comprising a spontaneously polarizable material, a gate disposed adjacent to the base, and a source spaced apart from the gate; And for a variable low resistance region-based memory device including a drain spaced apart from the gate,
forming a polarization region of the base by applying an electric field to the base through the gate; and
A variable low-resistance line corresponding to the boundary of the polarization region and spaced apart from the gate and including a region having lower electrical resistance than other adjacent regions is formed, so that current flows between the source and the drain through the variable low-resistance line. Including; step to form;
the variable low-resistance region includes at least a first variable low-resistance region and a second variable low-resistance region;
The first variable low-resistance region is disposed to be connected to the source and the drain at both sides of the gate with respect to the plane of the base so as to be spaced apart from the gate;
The second variable low-resistance region is spaced apart from the gate and is disposed to be connected to the source and the drain between the gate and the first variable low-resistance region on both sides of the gate with respect to the plane of the base,
An edge of at least one side connected to the source and the drain of the first variable low resistance region is formed parallel to an edge of at least one side connected to the source and the drain of the second variable low resistance region. A variable low-resistance area-based memory device control method. According to claim 1,
One or more variable low-resistance regions spaced apart from the gate and connected to the source and the drain on both sides of the gate with respect to the plane of the base and formed closer to the gate than the second variable low-resistance region, Variable low-resistance region-based memory device. According to claim 1,
The variable low resistance region-based memory device, wherein the source and the drain are formed long to pass the first variable low resistance region.

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