KR102370745B1 - Variable low resistance area based memory device and controlling thereof - Google Patents

Abstract

An embodiment of the present invention corresponds to a base including a spontaneously polarizable material, a gate disposed adjacent to the base, a polarization region formed in the base by applying an electric field to the base through the gate, and a boundary between the polarization region one or more variable low-resistance regions including a region having a lower electrical resistance than other adjacent regions, a source spaced apart from the gate and connected to the fluctuating low-resistance region, and a drain spaced apart from the gate and connected to the fluctuating low-resistance region Disclosed is a variable low-resistance region-based memory device comprising:

Description

Variable low resistance area based memory device and controlling thereof

The present invention relates to a memory device using a variable low resistance region and a method for controlling the same.

With the development of technology and increased interest in people's convenience in life, attempts to develop various electronic products are being actively pursued.

In addition, these electronic products are becoming smaller and more integrated, and the places where they are used are increasing widely.

These electronic products include various electrical components, for example, CPU, memory, and other various electrical components. These base elements may include various types of electrical circuits.

For example, electrical devices are used in products in various fields, such as computers and smart phones, as well as home sensor devices for IoT and bio-electronic devices for ergonomics.

On the other hand, the use and application fields of these electric devices are rapidly increasing according to the recent speed of technological development and the rapid improvement of the living standards of users, and the demand thereof is also increasing accordingly.

According to this trend, there is a limit to realizing and controlling an electronic circuit that is easily and quickly applied to various electrical devices that are commonly used.

Meanwhile, memory devices, particularly nonvolatile memory devices, are widely used as information storage and/or processing devices of various electronic devices, such as cameras and communication devices, as well as computers.

These memory devices, particularly in terms of lifespan and speed, are being developed a lot. Most of the problems are in securing the memory lifespan and speed, but there is a limit to realizing an improved memory device.

The present invention can provide a memory device based on a variable low resistance region that can be easily applied to various uses, a memory device having a long data retention period, high memory speed, and improved device integration, and a control method thereof .

An embodiment of the present invention corresponds to a base including a spontaneously polarizable material, a gate disposed adjacent to the base, a polarization region formed in the base by applying an electric field to the base through the gate, and a boundary between the polarization region one or more variable low-resistance regions including a region having a lower electrical resistance than other adjacent regions, a source spaced apart from the gate and connected to the fluctuating low-resistance region, and a drain spaced apart from the gate and connected to the fluctuating low-resistance region Disclosed is a variable low-resistance region-based memory device comprising:

In the present embodiment, the variable low resistance region includes a first variable low resistance region spaced apart from the gate and a first variable low resistance region disposed closer to the gate than the first variable low resistance region and spaced apart from the first variable low resistance region It may optionally include one of the two variable low-resistance regions.

In the present embodiment, the variable low resistance region includes a first variable low resistance region spaced apart from the gate and a first variable low resistance region disposed closer to the gate than the first variable low resistance region and spaced apart from the first variable low resistance region 2 may include a fluctuating low-resistance region.

In the present embodiment, the source may have an elongated shape to correspond to a second variable low resistance region spaced apart from the first variable low resistance region.

In the present embodiment, the drain may have an elongated shape to correspond to a second variable low resistance region spaced apart from the first variable low resistance region.

In the present embodiment, different information may be stored according to the formation of the first variation low resistance region or the second variation low resistance region.

In the present embodiment, the variable low resistance region may be generated or destroyed according to the control of the polarization region by controlling the electric field through the gate.

In the present embodiment, the variable low resistance region may be maintained even when the electric field applied through the gate is removed.

According to another aspect of the present invention, there is provided a device comprising: a base comprising a spontaneously polarizable material, a gate disposed adjacent to the base, a source spaced apart from the gate and connected to the variable low resistance region; and forming a polarization region of the base by applying an electric field to the base through the gate with respect to a memory device based on a variable low resistance region including a drain spaced apart from the gate and connected to the variable low resistance region; Forming a variable low-resistance region including a region having lower electrical resistance than other adjacent regions corresponding to the boundary of the polarization region so that a current flow between the source and the drain is formed through the variable low-resistance region Disclosed is a method for controlling a memory device based on a variable low-resistance region comprising a.

In the present embodiment, the variable low resistance region includes a first variable low resistance region spaced apart from the gate and a first variable low resistance region disposed closer to the gate than the first variable low resistance region and spaced apart from the first variable low resistance region It may optionally include one of the two variable low-resistance regions.

In the present embodiment, the variable low resistance region includes a first variable low resistance region spaced apart from the gate and a first variable low resistance region disposed closer to the gate than the first variable low resistance region and spaced apart from the first variable low resistance region 2 may include a fluctuating low-resistance region.

In the present embodiment, the method may include measuring a current between the source and the drain according to the formation of the first variation low resistance region or the second variation low resistance region while controlling the gate.

According to the control of the polarization region by controlling the electric field through the gate in the present embodiment, it may include the step of generating or disappearing the variable low resistance region.

Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

The electronic circuit using the fluctuating low resistance region and the control method thereof according to the present invention can be easily applied to various uses.

1 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1 .
3 is an enlarged view of K of FIG. 2 .
4A to 4C are diagrams for explaining a control method related to the electronic circuit of FIG. 1 . 5 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.
6 is a cross-sectional view taken along the line VI-VI of FIG.
7A to 7D are diagrams for explaining a current path range control method related to the electronic circuit of FIG. 5 .
8 is a schematic plan view illustrating an electronic circuit according to an embodiment of the present invention.
9 is a cross-sectional view taken along line II-II of FIG.
10 to 14 are diagrams for explaining the operation of the electronic circuit of FIG. 8 .
15 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.
16 is a cross-sectional view taken along line V-V of FIG. 15 .
17 is a schematic plan view illustrating a memory device according to another embodiment of the present invention.
18 is a cross-sectional view taken along line VI-VI of FIG. 17 .
19 is a graph illustrating a voltage and current relationship between the first region and the variable low resistance region.
20 is a cross-sectional view of a variable low-resistance region memory device according to still another exemplary embodiment of the present invention.
21 is a cross-sectional view of a variable low resistance region memory device according to still another exemplary embodiment of the present invention.
22 is a cross-sectional view of a variable low-resistance region memory device according to still another exemplary embodiment of the present invention.
23 is a cross-sectional view of a variable low resistance region memory device according to still another exemplary embodiment of the present invention.
24 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.
25 to 27 are diagrams for explaining a variable low resistance region memory device according to another embodiment of the present invention.
28 to 34 are diagrams for explaining a variable low-resistance region memory device according to still another embodiment of the present invention.
35 is a diagram for explaining an example of an operation of a memory device according to an embodiment of the present invention.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the embodiments of the present invention shown in the accompanying drawings.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. .

In the following embodiments, terms such as first, second, etc. are used for the purpose of distinguishing one component from another, not in a limiting sense.

In the following examples, the singular expression includes the plural expression unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have means that the features or components described in the specification are present, and the possibility that one or more other features or components will be added is not excluded in advance.

In the drawings, the size of the components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

In the following embodiments, the x-axis, the y-axis, and the z-axis are not limited to three axes on a Cartesian coordinate system, and may be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

In cases where certain embodiments may be implemented otherwise, a specific process sequence may be performed different from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the order described.

1 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, and FIG. 3 is an enlarged view K of FIG. 2 .

1 and 2 , the electronic circuit 10 of the present embodiment may include an active layer 11 , an application electrode 12 , and a variable low resistance region VL.

The active layer 11 may include a spontaneously polarizable material. For example, the active layer 11 may include an insulating material and a ferroelectric material. That is, the active layer 11 may comprise a material having a spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

In an optional embodiment, the active layer 11 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 ,} BiFe3, PbTiO3, PbZrO3, SrBi2Ta2O9.

Also, as another example, the active layer 11 has an ABX3 structure, where A is an alkyl group of CnH2n+1, and at least one material selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, B may include at least one material selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the active layer 11 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _{3 ,} CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ ) NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

The active layer 11 may be formed using various other ferroelectric materials, and descriptions of all examples thereof will be omitted. In addition, when the active layer 11 is formed, the ferroelectric material may be doped with various other materials to include additional functions or to improve electrical properties.

The active layer 11 has spontaneous polarization and can control the degree and direction of polarization according to the application of an electric field. In addition, the active layer 11 may maintain a polarized state even when the applied electric field is removed.

The application electrode 12 may be formed to apply an electric field to the active layer 11 , for example, to apply a voltage to the active layer 11 .

As an optional embodiment, the application electrode 12 may be formed to be in contact with the upper surface of the active layer 11 .

In addition, the application electrode 12 may be formed to apply voltages of various magnitudes to the active layer 11 and to control the voltage application time.

In an alternative embodiment, the application electrode 12 may be a gate electrode.

For example, the application electrode 12 may be electrically connected to a power source (not shown) or a power control unit.

The application electrode 12 may include various materials, and may include a material having high electrical conductivity. For example, the application electrode 12 may be formed using various metals.

For example, the application electrode 12 may be formed to contain aluminum, chromium, titanium, tantalum, molybdenum, tungsten, neodymium, scandium, or copper. Alternatively, it may be formed using an alloy of these materials or may be formed using a nitride of these materials.

Also, as an optional embodiment, the applying electrode 12 may include a laminate structure.

Although not shown, as an optional embodiment, one or more insulating layers may be further disposed between the application electrode 12 and the active layer 11 .

The fluctuating low resistance region VL is a region formed in the active layer 11 and is a region through which current can flow, and can be formed as a path of a current having a linearity around the applying electrode 12 as shown in FIG. 1 . there is.

In more detail, the low-variation-resistance region VL is a region in which the electrical resistance of the active layer 11 is lower than that of other regions adjacent to the low-variation resistance region VL.

In addition, after forming the fluctuating low-resistance region VL through the application electrode 12 , even if the electric field through the application electrode 12 is removed, for example, even if the voltage is removed, the polarization state of the active layer 11 is Since it is maintained, the variable low resistance region VL is maintained, and a state in which a current path is formed can be maintained.

Through this, various electronic circuits can be configured.

The variable low resistance region VL has a height HVL, and this height HVL may correspond to the entire thickness of the active layer 11 .

The height HVL of the variable low resistance region VL may be proportional to the strength of the electric field, for example, the magnitude of the voltage when the electric field is applied through the application electrode 12 . At least the magnitude of this electric field may be greater than the intrinsic coercive field of the active layer 11 .

The variable low-resistance region VL is a region formed when a voltage is applied to the active layer 11 through the application electrode 12 , and can be changed, for example, generated, destroyed, or moved through the control of the application electrode 12 . .

The active layer 11 may include a first polarization region 11F having a first polarization direction, and the variable low resistance region VL may be formed at a boundary of the first polarization region 11F.

In addition, it may include a second polarization region 11R having a second polarization direction adjacent to the first polarization region 11F, and the variable low resistance region VL is at the boundary of the second polarization region 11R. can be formed. The second direction may be at least a direction different from the first direction, for example a direction opposite to the first direction.

For example, the variable low resistance region VL may be formed between the first polarization region 11F and the second polarization region 11R.

The variable low resistance region VL may have a width WVL in one direction, which may be proportional to a movement distance of the variable low resistance region VL.

Also, the width WVL may be the width of a region on a plane defined as the variable low resistance region VL, which may correspond to the width of the first polarization region 11F.

In addition, the variable low resistance region VL may be formed to correspond to the entire side surface of the boundary line of the first polarization region 11F, and may have a thickness TVL1 in a direction away from the side surface of the first polarization region 11F. there is.

As an alternative embodiment, this thickness TVL1 may be 0.1 to 0.3 nanometers.

4A to 4C are diagrams for explaining a current path range control method with respect to the electronic circuit of FIG. 1 .

Referring to FIG. 4A , the active layer 11 may include a second polarization region 11R having a second polarization direction. As an alternative embodiment, the polarization state of the active layer 11 as shown in FIG. 4A may be formed by applying the initialization electric field through the application electrode 12 .

Then, referring to FIG. 4B , a first polarization region 11F is formed in the active layer 11 . As a specific example, the first polarization region 11F may be formed in a region overlapping the application electrode 12 to correspond to the width of the application electrode 12 .

It is larger than the coercive field of the active layer 11 through the application electrode 12 and has a size large enough that the height HVL of the first polarization region 11F can be formed to correspond to at least the entire thickness of the active layer 11 . An electric field may be applied to the active layer 11 .

Through the application of the electric field through the application electrode 12 , the polarization direction of one region of the second polarization region 11R of the active layer 11 may be changed to change to the first polarization region 11F.

As an optional embodiment, the growth rate in the height (HVL) direction of the first polarization region 11F may be very fast, for example, it may grow at a rate of 1 km/sec (second).

Then, if the electric field through the application electrode 12 is continuously maintained, that is, as time elapses, the first polarization region 11F moves in the horizontal direction H, that is, in a direction perpendicular to the height HVL, and increases in size. can That is, the region of the second polarization region 11R may be gradually converted into the first polarization region 11F.

As an optional embodiment, the growth rate in the horizontal direction H of the first polarization region 11F may be very fast, for example, it may grow at a rate of 1 m/sec (sec).

Through this, the size of the variable low resistance region VL can be controlled. This size is, for example, the width of the variable low resistance region VL and corresponds to the growth distance of the first polarization region 11F, so the growth rate and electric field It can be proportional to the holding time. For example, the growth distance can be proportional to the product of the growth rate and the duration of the electric field.

Also, the growth rate of the first polarization region 11F may be proportional to the sum of the growth rate in the height (HVL) direction and the growth rate in the horizontal direction (H).

Therefore, the size of the variable low resistance region VL can be adjusted as desired by controlling the electric field holding time.

Specifically, as shown in FIG. 4C , the first polarization region 11F spreads and becomes large, and accordingly, the variable low resistance region VL may also move away from the applying electrode 12 in a direction away from it.

In this embodiment, an electric field is applied to the active layer through the applying electrode to form a first polarization region having a first polarization direction different from the second polarization direction in the active layer, and at the boundary between the first polarization region and the second polarization region A corresponding variation low resistance region can be formed. The variable low-resistance region is a region with low resistance, and as a region with reduced resistance, it can serve as a path for current, so that an electronic circuit can be easily formed.

In addition, in this embodiment, by controlling the magnitude of the electric field through the applied electrode, for example, by controlling the magnitude of the voltage, the height of the variable low-resistance region can be determined, and specifically, it is controlled to have a height corresponding to the entire thickness of the active layer. can do.

In addition, the size, eg, width, of the variable low resistance region can be determined by controlling the duration of the electric field through the applied electrode. By controlling the size of the variable low resistance region, it is possible to easily control the size of the path of the current flow.

In addition, even if the electric field through the applied electrode is removed, the polarization state of the polarization region is maintained, so the path of the current can be easily maintained. The resistance region may have a low resistance so that no current flows.

Through this, it is possible to control the extinction of the path of the current, and as a result, it is possible to easily control the flow of the current.

By controlling the electronic circuit of the present embodiment, it can be used for various purposes, for example, one or more electrodes can be connected so as to be in contact with the variable low resistance region.

5 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention.

6 is a cross-sectional view taken along the line VI-VI of FIG.

5 and 6 , the electronic circuit 20 of this embodiment may include an active layer 21 , an application electrode 22 , and variable low resistance regions VL1 , VL2 , and VL3 .

The active layer 21 may include a spontaneously polarizable material. For example, the active layer 21 may include an insulating material and a ferroelectric material. That is, the active layer 21 may comprise a material having a spontaneous electric polarization (electric dipole) that can be reversed in the presence of an electric field.

As an optional embodiment, the active layer 21 may include a perovskite-based material, and a detailed description thereof will be omitted since it is the same as the above-described embodiment.

The application electrode 22 may be formed to apply an electric field to the active layer 21 , for example, to apply a voltage to the active layer 21 . Specific details are the same as in the above-described embodiment, and thus will be omitted.

The variation low resistance regions VL1 , VL2 , and VL3 may include a first variation low resistance region VL1 , a second variation low resistance region VL2 , and a third low variation resistance region VL3 .

The first variation low resistance region VL1 may have a width greater than that of the second variation low resistance region VL2 , and the second variation low resistance region VL2 may have a width greater than that of the third variation low resistance region VL3 . there is. For example, the region surrounded by the first variation low resistance region VL1 has a greater width than the region surrounded by the second variation low resistance region VL2 , and the region surrounded by the second variation low resistance region VL2 has the third variation It may have a greater width than a region surrounded by the low resistance region VL3 .

As a selective embodiment, the first variation low resistance region VL1 is disposed outside the second variation low resistance region VL2 , and the second variation low resistance region VL2 is outside the third variation low resistance region VL3 . can be placed in

The first variation low resistance region VL1 , the second variation low resistance region VL2 , and the third variation low resistance region VL3 are regions formed in the active layer 21 , and are regions through which current can flow, and have a linear current It can be formed by the path of

Specifically, the first variation low resistance region VL1 , the second variation low resistance region VL2 , and the third variation low resistance region VL3 are the first variation low resistance region VL1 , the second variation low resistance region VL3 of the active layer 21 . The second variation low resistance region VL2 and the third variation low resistance region VL3 are regions in which electrical resistance is lower than that of other regions adjacent to the region.

In addition, after forming the first variation low resistance region VL1 , the second variation low resistance region VL2 , and the third variation low resistance region VL3 through the application electrode 22 , the Even if the electric field is removed, for example, even if the voltage is removed, the polarization state of the active layer 21 is maintained, so that the first variation low resistance region VL1, the second variation low resistance region VL2, and the third variation low resistance region (VL3) is maintained and can maintain a state forming a path of current.

Through this, various electronic circuits can be configured. For example, it may constitute at least a portion of a memory device capable of storing one or more data.

The variable low resistance regions VL1 , VL2 , and VL3 have a height HVL, and this height HVL may correspond to the entire thickness of the active layer 21 .

The active layer 21 may include first polarization regions 21F1 and 21F3 having a first polarization direction, and the variable low resistance regions VL1 , VL2 , and VL3 are boundaries of the first polarization regions 21F1 and 21F3 . can be formed in

In addition, the second polarization regions 21R1 and 21R2 having a second polarization direction may be included adjacent to the first polarization regions 21F1 and 21F3, and the variable low resistance region VL is such a second polarization region 21R1 , 21R2). The second direction may be at least a direction different from the first direction, for example a direction opposite to the first direction.

For example, the first variation low resistance region VL1 may be formed between the first polarization region 21F1 and the second polarization region 21R1 .

In addition, the second variation low resistance region VL2 may be formed between the first polarization region 21F1 and the second polarization region 21R2 .

Also, the third variable low resistance region VL3 may be formed between the first polarization region 21F3 and the second polarization region 21R2 .

7A to 7D are diagrams for explaining a current path range control method related to the electronic circuit of FIG. 5 .

Referring to FIG. 7A , the active layer 21 may include a second polarization region 21R having a second polarization direction. As an optional embodiment, the polarization state of the active layer 21 as shown in FIG. 7A may be formed by applying the initialization electric field through the application electrode 22 .

Then, referring to FIG. 7B , a first polarization region 21F is formed in the active layer 21 . As a specific example, the first polarization region 21F may be first formed in a region overlapping the application electrode 22 to correspond to the width of the application electrode 22 , and then grow in a horizontal direction to form a state as shown in FIG. 7B . Also, the first polarization region 21R of FIG. 7A may be reduced and changed to the first polarization region 21R1 having the same shape as that of FIG. 7B .

A first variation low resistance region VL1 may be formed between the first polarization region 21F and the second polarization region 21R1 .

Then, referring to FIG. 7C , the polarization direction of a portion of the first polarization region 21F is converted into a second polarization region 21R2 having a polarization direction in the second direction by applying an electric field opposite to that of FIG. 7B . can For example, the second polarization region 21R2 having a polarization direction in a second direction opposite to the first polarization direction of the first polarization region 21F may be formed.

In addition, through this, the size of the first polarization region 21F of FIG. 7B may be reduced to change into the first polarization region 21F1 of the shape illustrated in FIG. 7C .

A second variation low resistance region VL2 may be formed between the second polarization region 21R2 and the first polarization region 21F1 .

Since the polarization state is maintained, the first variation low resistance region VL1 may be maintained as it is.

Then, referring to FIG. 7D , the polarization direction of a portion of the second polarization region 21R2 is converted into the first polarization region 21F3 having the polarization direction in the first direction by applying an electric field opposite to that of FIG. 7C . can do. For example, the first polarization region 21F3 having a polarization direction in a first direction opposite to the second polarization direction of the second polarization region 21R2 may be formed.

Also, through this, the size of the second polarization region 21R2 of FIG. 7C may be reduced to change into the second polarization region 21R2 of the shape illustrated in FIG. 7D .

A third low-variation resistance region VL3 may be formed between the second polarization region 21R2 and the first polarization region 21F3 .

Since the polarization state is maintained, the first variation low resistance region VL1 and the second variation low resistance region VL2 are maintained as they are, and a third variation low resistance region VL3 may be added thereto.

In this embodiment, an electric field is applied to the active layer through the applying electrode to form a first polarization region having a first polarization direction different from the second polarization direction in the active layer, and at the boundary between the first polarization region and the second polarization region A corresponding variation low resistance region can be formed. The variable low-resistance region is a region with low resistance, and as a region with reduced resistance, it can serve as a path for current, so that an electronic circuit can be easily formed.

In addition, according to the present embodiment, it is possible to control the magnitude of the electric field through the applying electrode and control the direction of the electric field, thereby forming a plurality of first polarization regions or a plurality of second polarization regions with respect to the active layer.

A plurality of variable low resistance regions may be formed on a boundary line between the plurality of first polarization regions or the plurality of second polarization regions. Each of these plurality of fluctuating low-resistance regions can form a path of current, so that electronic circuits of various shapes and uses can be easily created and controlled.

For example, since the number of a plurality of variable low-resistance regions can be selectively applied with respect to the applied electrode, various current paths can be formed, and a memory for storing various data according to the current paths can be implemented.

8 is a schematic plan view showing an electronic circuit according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line II-II of FIG. 8 .

8 and 9 , the electronic circuit 100 of the present embodiment may include an active layer 110 , an application electrode 120 , a variable low resistance region VL, and one or more connection electrode units 131 and 132 . there is.

The active layer 110 may include a spontaneously polarizable material. For example, the active layer 110 may include an insulating material and a ferroelectric material. That is, the active layer 110 may include a material having a spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

In an alternative embodiment, the active layer 110 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 ,} BiFe3, PbTiO3, PbZrO3, SrBi2Ta2O9.

Also, as another example, the active layer 110 has an ABX3 structure, where A is an alkyl group of CnH2n+1, and at least one material selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, B may include at least one material selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the active layer 110 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _{3 ,} CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ ) NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

Since the active layer 110 can be formed using various other ferroelectric materials, descriptions of all examples thereof will be omitted. In addition, when the active layer 110 is formed, the ferroelectric material may be doped with various other materials to include additional functions or to improve electrical properties.

The active layer 110 has spontaneous polarization and can control the degree and direction of polarization according to application of an electric field. Also, the active layer 110 may maintain a polarized state even when the applied electric field is removed.

The application electrode 120 may be formed to apply an electric field to the active layer 110 , for example, to apply a voltage to the active layer 110 .

As an optional embodiment, the application electrode 120 may be formed to be in contact with the upper surface of the active layer 110 .

In addition, the application electrode 120 may be formed to apply voltages of various magnitudes to the active layer 110 and to control the voltage application time.

In an alternative embodiment, the application electrode 120 may be a gate electrode.

For example, the application electrode 120 may be electrically connected to a power source (not shown) or a power control unit.

The application electrode 120 may include various materials, and may include a material having high electrical conductivity. For example, the application electrode 120 may be formed using various metals.

For example, the application electrode 120 may be formed to contain aluminum, chromium, titanium, tantalum, molybdenum, tungsten, neodymium, scandium, or copper. Alternatively, it may be formed using an alloy of these materials or may be formed using a nitride of these materials.

Also, as an optional embodiment, the applying electrode 120 may include a laminate structure.

The connection electrode parts 131 and 132 may include one or more electrode members, for example, a first connection electrode member 131 and a second connection electrode member 132 .

The connection electrode parts 131 and 132 may be formed on the active layer 110 , for example, may be formed on the upper surface of the active layer 110 to be spaced apart from the applying electrode 120 , and as an optional embodiment, the active layer 110 . ) may be formed to be in contact with.

The first connection electrode member 131 and the second connection electrode member 132 may be formed using various conductive materials. For example, the first connection electrode member 131 and the second connection electrode member 132 may be formed to contain aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten.

As an optional embodiment, the first connection electrode member 131 and the second connection electrode member 132 may include a structure in which a plurality of conductive layers are stacked.

As an optional embodiment, the first connection electrode member 131 and the second connection electrode member 132 may be formed using a conductive metal oxide, for example, indium oxide (eg, In ₂ O ₃ ), tin oxide. (eg SnO ₂ ), zinc oxide (eg ZnO), indium tin oxide alloy (eg In ₂ O ₃ —SnO ₂ ) or indium zinc oxide alloy (eg In ₂ O ₃ —ZnO) can be formed

As an optional embodiment, the connection electrode parts 131 and 132 may be terminal members including input/output of electrical signals.

Also, as a specific example, the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode parts 131 and 132 may include a source electrode or a drain electrode.

10 to 14 are diagrams for explaining the operation of the electronic circuit of FIG. 8 .

10 is a view showing a state in which the first electric field is applied through the application electrode 120, FIG. 11 is a cross-sectional view taken along line VIII-VIII of FIG. 10, and FIG. 12 is an enlarged view K of FIG. am.

10 to 14 , when the first electric field is applied to the active layer 110 through the application electrode 120 , at least one region of the active layer 110 may include a polarization region 110F.

The polarization region 110F may have a shape that surrounds the application electrode 120 with the application electrode 120 as a center. The polarization region 110F may have a boundary line.

The first variation low resistance region VL1 may be formed in a region corresponding to the side of the boundary line. Referring to FIG. 10 , the application electrode 120 may be formed in a linear shape surrounding the application electrode 120 .

For example, the first variable low resistance region VL1 may have a first width WVL1 in one direction to surround the application electrode 120 .

Also, the first variation low resistance region VL1 may be formed to correspond to the entire side surface of the boundary line of the polarization region 110F, and may have a thickness TVL1 in a direction away from the side surface of the polarization region 110F.

As an alternative embodiment, this thickness TVL1 may be 0.1 to 0.3 nanometers.

As an optional embodiment, a process of applying the initialization electric field to the active layer 110 before the first voltage is applied to the active layer 110 through the application electrode 120 may be performed.

Through the process of applying this initialization electric field to the active layer 110, the step of converting the region of the active layer 110 to a polarization in a direction different from that of the polarization region 110F, for example, a polarization region in the opposite direction. .

Then, the polarization region 110F may be formed in one region by applying an electric field in the opposite direction.

The first variation low resistance region VL1 formed at the boundary of the polarization region 110F of the active layer 110 may change to a region having a lower resistance than other regions of the active layer 110 . For example, the first variation low resistance region VL1 may have a lower resistance than the polarization region 110F of the active layer 110 and a region of the active layer 110 surrounding the first variation low resistance region VL1 .

Through this, the first variation low resistance region VL1 may form a current passage.

As an optional embodiment, the first variation low resistance region VL1 may correspond to one region of a plurality of domain walls provided in the active layer 110 .

Also, the first variation low resistance region VL1 may be continuously maintained when the polarization state of the polarization region 110F of the active layer 110 is maintained. That is, even if the first voltage applied to the active layer 110 through the application electrode 120 is removed, the state of the variable low resistance region VL1 , that is, the low resistance state may be maintained.

As shown in FIGS. 10 and 11 , a current passage may be formed through the first variable low resistance region VL1 . However, since the connection electrode parts 131 and 132 do not correspond to the first variable low resistance region VL1 , the flow of current through the connection electrode parts 131 and 132 may not occur.

13 is a view illustrating a state in which the first electric field is further maintained for a predetermined period of time through the applying electrode 120, and FIG. 14 is a cross-sectional view taken along line XII-XI of FIG. 13 .

Referring to FIGS. 13 and 14 , the duration of the first electric field through the application electrode 120 is increased, so that the polarization region 110F of FIGS. 10 and 11 moves in the horizontal direction to increase the polarization region 110F. A second variation low resistance region VL2 larger than the first variation low resistance region VL1 may be formed.

For example, the structure shown in FIGS. 13 and 14 may be formed by continuously maintaining the voltage applied in FIGS. 10 and 11 for a predetermined time.

The polarization region 110F may have a shape that surrounds the application electrode 120 with the application electrode 120 as a center. The polarization region 110F may have a boundary line. The second variation low resistance region VL2 may be formed in a region corresponding to a side surface of the boundary line of the polarization region 110F. Referring to FIG. 13 , the application electrode 120 may be formed in a linear shape surrounding the application electrode 120 .

For example, the second variable low resistance region VL2 may have a second width WVL2 in one direction to surround the application electrode 120 , and the second width WVL2 may be greater than the first width WVL1 . can That is, the second variation low resistance region VL2 may make one circumference of the application electrode 120 .

In addition, the second variation low resistance region VL2 may be formed to correspond to the entire side surface of the boundary line of the polarization region 110F, and may have a thickness in a direction away from the side surface of the polarization region 110F, in an optional embodiment As such, this thickness may be 0.1 to 0.3 nanometers.

The second variation low resistance region VL2 formed at the boundary of the polarization region 110F of the active layer 110 may change to a region having a lower resistance than other regions of the active layer 110 . For example, the second variation low resistance region VL2 may have a lower resistance than the polarization region 110F of the active layer 110 and regions of the active layer 110 surrounding the second variation low resistance region VL2 . That is, the resistance of the second variation low resistance region VL2 is lower than the resistance of the inner portion of the second variation low resistance region VL2 of the polarization region 110F. In addition, the resistance of the second variation low resistance region VL2 may be lower than the resistance of the portion outside the second variation low resistance region VL2 of the active layer 110 .

Through this, the second variation low resistance region VL2 may form a current passage.

As an optional embodiment, the second variable low resistance region VL2 may correspond to one region of a plurality of domain walls provided in the active layer 110 .

Also, the second variation low resistance region VL2 may be continuously maintained when the polarization state of the active layer 110 is maintained. That is, even if the second voltage applied to the active layer 110 through the application electrode 120 is removed, the state of the second variable low resistance region VL2 , that is, the low resistance state may be maintained.

Therefore, a current passage may be formed through the second variation low resistance region VL2 .

In addition, as a specific example, the connection electrode parts 131 and 132 are formed to correspond to the second variable low resistance region VL2, for example, the first connection electrode member 131 of the connection electrode parts 131 and 132 and The second connection electrode members 132 may be disposed to be in contact with the upper surface of the second low variation low resistance region VL2 while being spaced apart from each other.

Through this, current may flow through the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode parts 131 and 132 .

In addition, various electrical signals may be generated. For example, when the electric field in the state of FIGS. 13 and 14 is more continuously applied, that is, when the application time increases, the second variable low resistance region VL2 moves further, and the first connection electrode member 131 and the second 2 It is possible to escape the connection electrode member 132 . Accordingly, current may not flow through the first connection electrode member 131 and the second connection electrode member 132 .

In addition, as an optional embodiment, an initialization process for the entire active layer 110 may be performed.

Then, when an electric field is applied to the active layer 110 through the application electrode 120 again, current flows through the first connection electrode member 131 and the second connection electrode member 132 of the connection electrode parts 131 and 132 . can

The electronic circuit of the present embodiment can apply voltages of various magnitudes to the active layer through the application electrode, and can control the time of application.

Through this, a polarization region can be formed in the active layer with a region of a desired size, and a low variation resistance region can be formed at the boundary of the polarization region.

When the connecting electrode unit is formed to correspond to, for example, contact with, such a fluctuating low-resistance region, a current may flow through the connecting electrode unit, and even if the voltage is removed, the active layer containing the ferroelectric material can maintain a polarized state. The fluctuating low-resistance region of its boundary can also be maintained so that current can continue to flow.

In addition, a voltage may be applied to the active layer through the application electrode to change the variable low resistance region into a polarization region, and through this, the current does not flow through the connection electrode portion through which the current flows.

The current flow can be controlled by controlling the voltage of the applied electrode, and the electronic circuit can be used for various purposes through the control of the current flow.

In an alternative embodiment, the electronic circuit may be used as a memory.

For example, it can be used as a memory by defining the flow of current as 1 and no flow as 0.

In addition, the electronic circuit may constitute a circuit unit that generates and transmits various signals, and may also be used as a switching device.

In addition, since it can be applied with a simple structure to other parts requiring control of electrical signals, it can be applied to various fields such as variable circuits, CPUs, and biochips.

15 is a schematic plan view showing an electronic circuit according to another embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along line V-V of FIG. 15 .

15 and 16 , the electronic circuit 200 of the present embodiment may include an active layer 210 , an applying electrode 220 , a variable low resistance region VL, and connection electrode units 231 and 232 .

For convenience of description, different points from the above-described embodiment will be mainly described.

The active layer 210 may include a spontaneously polarizable material. For example, the active layer 210 may include an insulating material and a ferroelectric material. That is, the active layer 210 may include a material having a spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

The description of the material for forming the active layer 210 is the same as that described in the above-described embodiment, or a specific description thereof will be omitted since it can be applied by modifying the same.

The application electrode 220 may be formed to apply an electric field to the active layer 210 , for example, to apply a voltage to the active layer 210 .

As an optional embodiment, the application electrode 220 may be formed to be in contact with the upper surface of the active layer 210 .

The description of the material forming the application electrode 220 is the same as that described in the above-described embodiment, or a specific description thereof will be omitted since it can be applied by modifying the same.

The connection electrode parts 231 and 232 may include one or more electrode members, for example, a first connection electrode member 231 and a second connection electrode member 232 .

The connection electrode parts 231 and 232 may be formed on the active layer 210 , for example, on the surface opposite to the surface on which the applying electrode 220 is formed among the surfaces of the active layer 210 so as to be spaced apart from the applying electrode 220 . can be formed.

The application electrode 220 may be formed on the upper surface of the active layer 210 , and the connection electrode parts 231 and 232 may be formed on the lower surface of the active layer 210 .

As an optional embodiment, the connection electrode parts 231 and 232 may be formed to contact the active layer 210 .

The first connection electrode member 231 and the second connection electrode member 232 may be formed using various conductive materials.

The description of the material forming the first connection electrode member 231 and the second connection electrode member 232 is the same as that described in the above-described embodiment, or a specific description thereof will be omitted.

Referring to FIG. 16 , when a voltage is applied to the active layer 210 through the application electrode 220 , at least one region of the active layer 210 may include a polarization region 210F.

The variable low resistance region VL may be formed in a region corresponding to the side of the boundary line of the polarization region 210F. Referring to FIG. 15 , a linear region surrounding the application electrode 220 with the application electrode 220 as the center. can be formed with

For example, the variable low resistance region VL2 may have a width in one direction to surround the application electrode 220 .

In addition, the variable low resistance region VL may be formed to correspond to the entire side surface of the boundary line of the polarization region 210F, and may have a thickness in a direction away from the side surface of the polarization region 210F. The thickness may be between 0.1 and 0.3 nanometers.

The variable low resistance region VL formed at the boundary of the polarization region 210F of the active layer 210 may be changed to a region having a lower resistance than other regions of the active layer 210 . For example, the variable low resistance region VL may have a lower resistance than the polarization region 210F of the active layer 210 and a region of the active layer 210 surrounding the variable low resistance region VL.

Through this, the variable low resistance region VL may form a current passage.

As an optional embodiment, the variable low resistance region VL may correspond to one region of a plurality of domain walls provided in the active layer 210 .

Also, the variable low resistance region VL may be continuously maintained when the polarization state of the active layer 210 is maintained. That is, even if the voltage applied to the active layer 210 through the application electrode 220 is removed, the state of the variable low resistance region VL, that is, the low resistance state may be maintained.

A current passage may be formed through the variable low resistance region VL.

In addition, as a specific example, the connection electrode parts 231 and 232 are formed to correspond to the variable low resistance region VL, for example, the first connection electrode member 231 and the second connection of the connection electrode parts 231 and 232 . The electrode members 232 may be disposed to be in contact with the lower surface of the variable low resistance region VL while being spaced apart from each other.

Through this, current may flow through the first connection electrode member 231 and the second connection electrode member 232 of the connection electrode parts 231 and 232 .

The electronic circuit of the present embodiment can apply voltages of various magnitudes to the active layer through the application electrode, and can control the time of application.

Through this, a polarization region can be formed in the active layer with a region of a desired size, and a low variation resistance region can be formed at the boundary of the polarization region.

In addition, by forming an application electrode on one surface of the active layer and a connection electrode part on the other surface, precise patterning and miniaturization of the electronic circuit can be easily performed.

The electronic device as described above may be implemented as a variable low-resistance region memory device as follows.

17 is a schematic plan view illustrating a memory device according to another embodiment of the present invention, and FIG. 18 is a cross-sectional view taken along line VI-VI of FIG. 17 .

17 and 18 , the variable low resistance region memory device 300 may include a base 310 , a gate 320 , a source 331 , and a drain 332 .

The base 310 may include the active layer material described above, for example, a spontaneously polarizable material. For example, the base 310 may include an insulating material and a ferroelectric material. That is, the base 310 may comprise a material with spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

In an alternative embodiment, the base 310 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 ,} BiFe3, PbTiO3, PbZrO3, SrBi2Ta2O9.

As another example, the base 310 has an ABX3 structure, where A is an alkyl group of CnH2n+1, and at least one material selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, B may include at least one material selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. As a specific example, the base 310 is CH ₃ NH ₃ PbI ₃ , CH ₃ NH ₃ PbI _x Cl _3-x , MAPbI _{3 ,} CH ₃ NH ₃ PbI _x Br _3-x , CH ₃ NH ₃ PbClxBr _3-x , HC (NH ₂ ) ₂ PbI ₃ , HC(NH ₂ ) ₂ PbI _x Cl _3-x , HC(NH ₂ ) ₂ PbI _x Br _3-x , HC(NH ₂ ) ₂ PbCl _x Br _3-x , (CH ₃ ) NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI ₃ , (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbI _x Cl _3-x , (CH ₃ NH ₃ )(HC( NH ₂ ) ₂ ) _1-y PbI _x Br _3-x , or (CH ₃ NH ₃ )(HC(NH ₂ ) ₂ ) _1-y PbCl _x Br _3-x (0≤x, y≤1) can do.

Since the base 310 may be formed using various other ferroelectric materials, a description of all examples thereof will be omitted. In addition, when the base 310 is formed, the ferroelectric material may be doped with various other materials to include additional functions or to improve electrical properties.

The base 310 has spontaneous polarization and can control the degree and direction of polarization according to application of an electric field. Also, the base 310 may maintain a polarized state even when the applied electric field is removed.

The base 310 may include a first region 311 and a second region 312 positioned adjacent to each other in the X-Y plane direction. The first region 311 may have polarization in a first direction, and the first direction is a thickness direction of the base 310 , that is, a direction in which the first region 311 and the second region 312 are disposed. may be in the Z-direction perpendicular to .

The second region 312 is positioned adjacent to the first region 311 in a direction perpendicular to the thickness, that is, in an XY plane direction, and the second region 312 is selectively disposed in a second region opposite to the first direction. It can have polarization aligned in two directions.

A gate 320 may be positioned on the second region 312 . Although not shown in the drawing, the gate 320 may be connected to a separate device to receive a gate signal.

The polarization of the second region 312 in the opposite direction to that of the first region 311 is enabled by the voltage applied to the gate 320 .

As described above, a low-variation resistance region 340 may be formed between the first region 311 and the second region 312 having polarizations in opposite directions. The variable low-resistance region 340 has a very small resistance compared to the first region 311 and/or the second region 312 , and a current may flow through this region.

The variable low resistance region 340 may be formed according to the following exemplary embodiment.

First, the base 310 including the spontaneously polarizable material may have polarization in the first direction as a whole. The entire base 310 is not necessarily limited to having the polarization in the first direction, and at least a predetermined area of the base 310 facing the gate 320 may have the polarization in the first direction. Optionally, the polarization in the first direction may be formed by applying an initialization electric field to the gate 320 .

In this state, as a first voltage is applied to the gate 320 for a first time and an electric field is applied to the base 310 through the gate 320, a certain area opposite to the gate 320 is polarized in the second direction. will change The electric field applied to the gate 320 to change the direction of polarization may be regulated by a first voltage, that is, a first voltage such that an electric field greater than the coercive field of the spontaneously polarizable material forming the base 310 is applied. can be added

The base 310 may have a first thickness t1. In this case, the second region 312 is formed over the entire first thickness t1 , and the magnitude of the first voltage applied to the gate 320 may be adjusted according to the first thickness t1 . According to an embodiment, the first thickness t1 and the magnitude of the first voltage applied to the gate 320 may be proportional to each other. That is, when the first thickness t1 is thick, the first voltage may be increased.

As shown in FIG. 18 , the variable low resistance region 340 may also be formed over the entire first thickness t1 .

The area of the second region 312 formed in this way may be proportionally determined according to the first time that the first voltage is applied to the gate 320 .

Therefore, in order to form the second region 312 of a desired area and/or size, an appropriate gate voltage, time, and first thickness t1 of the second region 312 for the corresponding ferroelectric material must be tested and/or calculated. can be determined in advance by

In this way, when the polarization direction of the second region 312 is changed from the first direction to the second direction, between the first region 311 having the polarization in the first direction and the second region 312 having the polarization in the second direction A variable low-resistance region 340 having a predetermined width may be formed in the . The variable low resistance region 340 may be formed around the gate 320 .

19 is a graph illustrating a voltage and current relationship between the first region and the variable low resistance region.

Specifically, FIG. 19 shows a state in which the current changes as the voltage increases in the first region and the variable low resistance region.

That is, in FIG. 19, (a) shows a state in which the current changes as the voltage increases in the low-variable resistance region, and (b) shows a state in which the current changes as the voltage increases in the first region.

Since the variable low resistance region 340 has a very small resistance compared to the first region 311 , it can be seen that the current flows smoothly according to the voltage application.

The variable low resistance region 340 formed as described above may not be erased over time.

The source 331 and the drain 332 are positioned so as to be in contact with the variation low resistance region 340 formed in this way. In this case, a current may flow from the source 331 to the drain 332 through the variable low resistance region 340 . Therefore, data writing is possible at this time, and it can be read, for example, as 1.

Optionally, the polarization direction of the second region 312 may be erased by making the polarization direction of the second region 312 the same as the polarization direction of the first region 311 again by the voltage applied to the variable low resistance region 340 and the gate 320 .

That is, by applying the second voltage to the gate 320 , the polarization direction of the second region 312 may be changed to the first direction again. Thereafter, by maintaining the second voltage for a second time, a region in which the polarization is changed in the first direction can be grown in a planar direction, and the region in which the polarization is changed in the first direction passes through the variable low resistance region 340 to generate a first When extended to the region 311 , the variable low resistance region 340 may disappear. In this case, no current can flow from the source 331 to the drain 332 , and thus, data erase is possible at this time, and it can be read as 0.

In this case, the second voltage may be a voltage different from the first voltage, and may have the same magnitude and opposite polarity as the first voltage according to an exemplary embodiment. The second time period may be at least equal to or longer than the first time period.

The variable low resistance region memory device formed as described above can be used as a nonvolatile memory device because the aforementioned variable low resistance region 340 can maintain its state even when power to the gate 320 is turned off.

Since the variable low-resistance region memory device is capable of writing/erasing about 10 ¹² times, it may have a memory lifespan of about 10 ⁷ times that of a conventional semiconductor device-based memory device.

In terms of memory speed, the variable low-resistance region memory device can be about 10 ^-9 sec, so that the memory speed can be increased by about 10 ⁶ times compared to the conventional semiconductor device-based memory device.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and lifespan.

In addition, since the position at which the variable low-resistance region 340 is formed can be adjusted according to the gate voltage and/or the application time, various memory devices can be designed, and the thickness can be reduced compared to the existing ferroelectric memory devices using ferroelectric materials. can achieve In addition, there is an advantage in that the degree of integration of the device can be increased because the degree of freedom in designing the memory is increased.

As shown in FIG. 17, the variable low resistance region 340 formed in this way may be formed in a closed loop shape with the gate 320 as the center, and a source 331 and a drain 332 are formed in a part of the closed loop. By disposing it, there may be two lines connecting the source 331 and the drain 332 . However, the present invention is not necessarily limited thereto, and if the gate is positioned on one side of the base in the planar direction and the source and drain are disposed on the other two adjacent sides, the variable low resistance region may become a single line connecting the source and the drain.

The source 331 and the drain 332 as described above may be an electrode structure formed by patterning on the base 310, but the present invention is not necessarily limited thereto, and although not shown in the drawings, the base 310 is It may be in contact with the variable low resistance region 340 through a via hole formed in the insulating layer covering it.

20 is a cross-sectional view of a variable low-resistance region memory device according to still another exemplary embodiment of the present invention.

Referring to FIG. 2 , in the variable low resistance region memory device 400 , a source 431 and a drain 432 are formed on a substrate 430 , and a base 410 including a spontaneous polarization material on the substrate 430 . ) can be placed. The substrate 430 may be formed of a semiconductor wafer, or a silicon wafer according to an embodiment. In addition, the source 431 and the drain 432 may be formed by ion doping on the wafer. Of course, although not shown in the drawings, an external signal line may be connected to the source 431 and the drain 432 through separate vias.

In this structure, the gate voltage and the application time may be determined so that the variable low resistance region 440 may be positioned to correspond to the regions of the source 431 and the drain 432 formed on the substrate 430 .

The substrate 430 and the base 410 as described above may be bonded by a separate adhesive layer, but the present invention is not limited thereto, and the base 410 may be formed on the substrate 430 . By implementing the base 410 as a thin film on the substrate 430 in this way, the memory device 400 can be made thinner, and the existing memory device process can be used, thereby further increasing the efficiency of the manufacturing process.

Although the above-described embodiments have shown a case where the first region and the second region have the same thickness, the present invention is not necessarily limited thereto.

21 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 21 , in the variable low resistance region memory device 500 , a source 531 and a drain 532 are formed on a substrate 530 , and a base 510 including a spontaneous polarization material on the substrate 530 . ) can be placed. In the memory device 500 of the embodiment shown in FIG. 21 , the first region 511 may have a second thickness t2 that is thicker than the first thickness t1 of the second region 512 . The second thickness t2 becomes a thickness at which the direction of polarization is not switched by the voltage applied to the gate 520, and accordingly, the variable low resistance region 540 has the first thickness t1 and the second thickness ( t2) may be formed at a boundary position.

As described above, since the voltage applied to the gate 520 can be set to a voltage at which polarization switching is performed with respect to the first thickness t1, by making a region formed with the second thickness t2 in the base 510 , the variable low resistance region 540 is not formed in the second thickness t2 even by the intensity of the voltage applied to the gate 520 and time, and only the variable low resistance region 540 is formed in the first thickness t1. ) can be formed.

That is, as shown in FIG. 21 , the variable low resistance region 540 may be formed at a position that becomes a boundary between the first thickness t1 and the second thickness t2 .

22 is a cross-sectional view of a variable low-resistance region memory device according to still another exemplary embodiment of the present invention.

Referring to FIG. 22 , in the variable low resistance region memory device 600 , a source 631 and a drain 632 are formed on a substrate 630 , and a base 610 including a spontaneous polarization material on the substrate 630 . ) can be placed. In the memory device 600 of the embodiment shown in FIG. 22 , as in the embodiment shown in FIG. 21 , the first region 611 has a second thickness t2 that is thicker than the first thickness t1 of the second region 612 . can have

At this time, depending on the time when the voltage is applied to the gate 620 , as shown in FIG. 22 , the first thickness t1 is formed from the boundary between the first thickness t1 and the second thickness t2 . can do. Accordingly, in the memory device 600 having such a structure, the source 631 and the drain 632 may be formed inside the boundary between the first thickness t1 and the second thickness t2 . Accordingly, even if the formation position of the variable low resistance region 640 is changed according to the change in the intensity of the voltage of the gate 620 and/or the time thereof, the variable low resistance region 640 and the source 631/drain 632 are may be electrically connected.

In the above-described embodiments, the gate is formed adjacent to the base, but the present invention is not limited thereto.

23 is a cross-sectional view of a variable low resistance region memory device according to still another exemplary embodiment of the present invention.

Referring to FIG. 23 , in the memory device 700 , another layer 750 may be further positioned between the base 710 and the gate 720 . The film 750 may be an insulating film, and may be a different material from the ferroelectric material forming the base 710 .

Even in this case, the polarization direction of the second region 712 may be switched under the influence of the electric field by the voltage applied to the gate 720 , and in this case, the gate 720 voltage and/ Alternatively, the time may be obtained by experimentation and/or calculation in advance.

24 is a cross-sectional view of a variable low-resistance region memory device according to another embodiment of the present invention.

Referring to FIG. 24 , in the variable low resistance region memory device 800 , a source 831 and a drain 832 are formed on a substrate 830 , and a base 810 including a spontaneous polarization material on the substrate 830 . ) can be placed.

According to the embodiment shown in FIG. 24 , a first gate 821 facing the base 810 and a second gate 822 positioned on the opposite side to the first gate 821 with respect to the base 810 are included. can do.

In this case, the variable low resistance region 840 may be formed by switching the polarization direction of the second region 812 by the first gate 821 . Accordingly, data writing becomes possible.

By switching the polarization direction of the second region 812 back to that of the first region 811 by the second gate 822 , the variable low resistance region 840 may be removed. This makes it possible to erase data.

As such, data may be read as 0/1 by the first gate 821 and the second gate 822 .

Of course, all the embodiments of the present specification described above are not limited to the illustrated embodiments, and may be applied in combination with each other.

In addition, it goes without saying that these embodiments can be selectively applied or modified to the embodiments to be described later.

25 to 27 are diagrams for explaining a variable low resistance region memory device according to another embodiment of the present invention.

Referring first to FIG. 25 , the variable low resistance region memory device 900 may include a base 910 , a gate 920 , a source 931 , and a drain 932 .

The base 910 may include the active layer material described above, for example, a spontaneously polarizable material. For example, the base 910 may include an insulating material and may include a ferroelectric material. That is, the base 910 may comprise a material with spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment, the base 910 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 ,} BiFe3, PbTiO3, PbZrO3, SrBi2Ta2O9.

Also, as another example, the base 910 has an ABX3 structure, where A is an alkyl group of CnH2n+1, and one or more materials selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, B may include at least one material selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. Specific examples are the same as those described in the above-described embodiment, and thus will be omitted.

The base 910 has spontaneous polarization and can control the degree and direction of polarization according to application of an electric field. Also, the base 910 may maintain a polarized state even when the applied electric field is removed.

A gate 920 may be positioned on the base 910 .

When a voltage is applied through the gate 920 , the base 910 including the active layer material may include a first region that is a polarization region in one direction around the gate 920 , and is adjacent to the first region and includes a second region. A second region having a polarization direction different from the polarization direction of the first region may be included. Since the contents of the first area and the second area are similar to those described in the above-described embodiments, a detailed description thereof will be omitted.

In this way, a first variation low resistance region 941 may be formed between the first region and the second region having polarizations in opposite directions. The properties of the first variation low resistance region 941 are the same as those of the variation low resistance region described in the above-described embodiments. As shown in FIG. 25 , when viewed from a direction perpendicular to the base 910 , the first variable low resistance region 941 is spaced apart from the gate 920 to make one circumference of the gate 920 .

In this case, the size of the first region may be controlled by controlling the first voltage, and one end of the first variation low resistance region 941 may be connected to the source 931 and the other end may be connected to the drain 932 . .

In this case, a current may flow from the source 931 to the drain 932 through the first variation low resistance region 941 .

For example, the first variable low resistance region 941 may have a shape similar to a part of a quadrangle, a source 931 is formed to overlap one side of the quadrangle, and a drain 932 is formed on the other side of the quadrangle. can be

As an optional embodiment, the first variable low resistance region 941 may have a shape similar to a quadrangle, and the source 931 and the drain 932 may be formed to overlap two opposite sides of the quadrangle.

Also, referring to FIG. 26 , it is shown that a second variation low resistance region 942 is formed inside the first variation low resistance region 941 with respect to the gate 920 . The properties of the second variation low resistance region 942 are the same as those of the variation low resistance region described in the above-described embodiments. As shown in FIG. 26 , when viewed from a direction perpendicular to the base 910 , the second variable low resistance region 942 is spaced apart from the gate 920 to make one circumference of the gate 920 .

One end of the second variable low resistance region 942 may be connected to the source 931 and the other end may be connected to the drain 932 .

For example, the second variation low resistance region 942 may include a shape similar to a portion of a rectangle smaller than the first variation low resistance region 941, and the source 931 is formed to overlap one side of the rectangle, and , a drain 932 may be formed on the other side.

As an optional embodiment, the second variable low resistance region 942 may have a shape similar to a quadrangle, and the source 931 and the drain 932 may be formed to overlap two opposite sides of the quadrangle.

Since the second variation low resistance region 942 is formed inside the first variation low resistance region 941 , current flows from the source 931 to the drain 932 through the first variation low resistance region 941 . The length of may be greater than the length of the flow of current from the source 931 to the drain 932 through the second variation low resistance region 942 .

The first variation low-resistance region 941 and the second variation low-resistance region 942 may be formed in a linear current path, and specifically, the first variation low-resistance region 941 and the second variation low-resistance region Reference numeral 942 denotes a region whose electrical resistance is lower than that of other adjacent regions.

The process of forming the first variation low resistance region 941 and the second variation low resistance region 942 may be similarly or similarly applied to those described with reference to FIGS. 7A to 7D of the above-described embodiment.

For example, a polarization state may be formed by applying a voltage to the base 910 through the gate 920 , thereby forming the first variable low resistance region 941 . Then, an electric field in the opposite direction may be applied to form a second low variation low resistance region 942 spaced apart from the first variation low resistance region 941 .

In addition, since the polarization state is maintained even when the voltage is removed from the gate 920 , the first variable low resistance region 941 and the second variable low resistance region 942 may be maintained as they are.

As an optional embodiment, the source 931 may be formed to be connected to both the first variation low resistance region 941 and the second variation low resistance region 942 . For example, the source 931 may have a structure elongated in one direction, and as a specific example, may be formed elongated in a direction away from the gate 920 .

Also, the drain 932 may be formed to be connected to both the first variation low resistance region 941 and the second variation low resistance region 942 . For example, the drain 932 may have a structure elongated in one direction, and as a specific example, may be formed elongated in a direction away from the gate 920 .

The source 931 and the drain 932 may have a structure formed on both sides with the gate 920 interposed therebetween.

The variable low resistance region memory device formed as described above can be used as a nonvolatile memory device because the variable low resistance regions 941 and 942 can maintain their state even when power to the gate 920 is turned off.

Since the variable low-resistance region memory device is capable of writing/erasing about 10 ¹² times, it may have a memory lifespan of about 10 ⁷ times that of a conventional semiconductor device-based memory device.

In terms of memory speed, the variable low-resistance region memory device can be about 10 ^-9 sec, so that the memory speed can be increased by about 10 ⁶ times compared to the conventional semiconductor device-based memory device.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and lifespan.

In addition, through the control of the electric field through the gate 920, only the first variation low resistance region 941 is formed, or both the first variation low resistance region 941 and the second variation low resistance region 942 are formed you can control

On the other hand, when a current flows between the source 931 and the drain 932 , the current value when only the first variation low resistance region 941 is formed is the first variation low resistance region 941 and the second variation low resistance region 941 . The current value when all of the resistive regions 942 are formed may be different, for example, small.

Through this, the present memory device 900 can store not only two pieces of information, for example, 1 or 0, but also four more pieces of information, and these can be referred to as 0, 1, 2, and 3 for convenience. .

That is, as shown in FIG. 26 , the case in which current flows between the source 931 and the drain 932 through the first variable low resistance region 941 and the second variable low resistance region 942 may be referred to as 3 .

As shown in FIG. 25 , when only the first variation low resistance region 941 is generated, a case in which current flows between the source 931 and the drain 932 through the first variation low resistance region 941 can be referred to as 1. .

Also, referring to FIG. 27 , by controlling the size of the polarization region through voltage control through the gate 920 , the size of the first region may be formed to reach the second variable low resistance region 942 , which Through this, only the second variation low resistance region 942 is formed, and the first variation low resistance region 941 is not generated.

If the first variation low resistance region 941 is formed, the second variation low resistance region 942 may be formed after the first variation low resistance region 941 is removed through initialization. For example, the first variable low resistance region 941 may be extinguished by controlling the voltage application through the gate 920 . This may be done by enlarging the first region to the edge, or as another example, by converting the first region into a second region, that is, through application of an electric field in the opposite direction.

A current may flow between the source 931 and the drain 932 through the second variable low resistance region 942 .

Since the second variation low resistance region 942 is formed inside the first variation low resistance region 941 , current flows from the source 931 to the drain 932 through the second variation low resistance region 942 . The length of may be smaller than the length of the flow of current from the source 931 to the drain 932 through the first variation low resistance region 941 .

The length of the current flow can be a resistance to the current from the source 931 to the drain 932, and the longer the length of the current flow from the source 931 to the drain 932, the greater the resistance. there is.

Therefore, the measurement of the current from source 931 to drain 932 through second variation low resistance region 942 is from source 931 to drain 932 through first variation low resistance region 941 . It may be greater than the measured value of the current.

Therefore, as shown in FIG. 27 , when only the second variable low resistance region 942 is generated, the case in which current flows between the source 931 and the drain 932 through the second variable low resistance region 942 can be referred to as 2. there is.

In addition, a case in which the first and second variable low resistance regions 941 and 942 are extinguished by voltage control through the gate 920 and no current flow between the source 931 and the drain 932 is defined as 0. can

That is, since the first variation low resistance region 941 and the second variation low resistance region 942 may be formed by controlling the gate 920 through the gate 920 , the first variation low resistance region 941 and the second variation low resistance region 941 and A memory may be formed as four different pieces of information by measuring a current according to the control of the resistance region 942 .

Therefore, when a single low-resistance region is used in designing a memory device, two pieces of information 0 and 1 can be stored, and when the number of low-resistance regions is increased to n, at least n+1 pieces of information can be stored. Through this, it is possible to easily provide a design of a memory device capable of integrating more information.

Through this, the degree of freedom in memory design is increased and high information can be integrated.

28 to 34 are diagrams for explaining a variable low-resistance region memory device according to still another embodiment of the present invention.

Referring to FIG. 28 , the variable low resistance region memory device 1000 may include a base 1010 , a gate 1020 , a source 1031 , and a drain 1032 .

The base 1010 may include the active layer material described above, for example, a spontaneously polarizable material. For example, the base 1010 may include an insulating material and may include a ferroelectric material. That is, the base 1010 may comprise a material having a spontaneous electrical polarization (electric dipole) that can be reversed in the presence of an electric field.

As an alternative embodiment, the base 1010 may include a perovskite-based material, for example, BaTiO ₃ , SrTiO _{3 ,} BiFe3, PbTiO3, PbZrO3, SrBi2Ta2O9.

Also, as another example, the base 1010 has an ABX3 structure, where A is an alkyl group of CnH2n+1, and at least one material selected from inorganic materials such as Cs and Ru capable of forming a perovskite solar cell structure, B may include at least one material selected from the group consisting of Pb, Sn, Ti, Nb, Zr, and Ce, and X may include a halogen material. Specific examples are the same as those described in the above-described embodiment, and thus will be omitted.

The base 1010 has spontaneous polarization and can control the degree and direction of polarization according to application of an electric field. Also, the base 1010 may maintain a polarized state even when the applied electric field is removed.

A gate 1020 may be positioned on the base 1010 .

When a voltage is applied through the gate 1020 , the base 1010 including the active layer material may include a first region that is a polarization region in one direction around the gate 1020 , and is adjacent to the first region and includes a second region. A second region having a polarization direction different from the polarization direction of the first region may be included. The contents of the first region and the second region may be formed similarly to those described in the above-described embodiments, and detailed descriptions thereof will be omitted.

In this way, the first variation low resistance region 1041 may be formed between the first region and the second region having polarizations in opposite directions.

In this case, the size of the first region may be controlled by controlling the first voltage, and one end of the first variation low resistance region 1041 may be connected to the source 1031 and the other end may be connected to the drain 1032 . .

In this case, a current may flow from the source 1031 to the drain 1032 through the first variation low resistance region 1041 .

For example, the first variable low resistance region 1041 may have a shape similar to a part of a quadrangle, and a source 1031 is formed to overlap one side of the quadrangle, and a drain 1032 is formed on the other side thereof. can be

As an optional embodiment, the first variable resistance region 1041 may have a shape similar to a quadrangle, and the source 1031 and the drain 1032 may be formed to overlap two opposite sides of the quadrangle.

Also, referring to FIG. 29 , by controlling the size of the polarization region through voltage control through the gate 1020 , the size of the first region may be formed to reach the second variation low resistance region 1042 , which Through this, only the second variation low resistance region 1042 is formed and the first variation low resistance region 1041 is not generated.

If the first variation low resistance region 1041 is formed, the second variation low resistance region 1042 may be formed after the first variation low resistance region 1041 is removed through initialization. For example, the first variable low resistance region 1041 may be extinguished by controlling voltage application through the gate 1020 . This may be done by enlarging the first region to the edge, or as another example, by converting the first region into a second region, that is, through application of an electric field in the opposite direction.

A current may flow between the source 1031 and the drain 1032 through the second variable low resistance region 1042 .

Since the second variation low resistance region 1042 is formed inside the first variation low resistance region 1041 , the flow of current from the source 1031 to the drain 1032 through the second variation low resistance region 1042 . The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the first variation low resistance region 1041 .

The length of this current flow can be the resistance to the current from the source 1031 to the drain 1032, and the longer the length of the current flow from the source 1031 to the drain 1032, the greater the resistance. there is.

Therefore, the measurement of the current from source 1031 to drain 1032 through second low variation low resistance region 1042 is the current from source 1031 to drain 1032 through first variation low resistance region 1041. It may be greater than the measured value of the current.

Therefore, as shown in FIG. 29 , when only the second variable low resistance region 1042 is generated, the case in which current flows between the source 1031 and the drain 1032 through the second variable low resistance region 1042 is different from FIG. 28 . Value information can be stored.

Also, referring to FIG. 30 , by controlling the size of the polarization region through voltage control through the gate 1020 , the size of the first region may be formed to reach the third variable low resistance region 1043 , which Through this, only the third variation low resistance region 1043 is formed, and the first variation low resistance region 1041 or the second variation low resistance region 1042 is not generated.

If the first variation low resistance region 1041 is formed, the third variation low resistance region 1043 may be formed after the first variation low resistance region 1041 is removed through initialization. For example, the first variable low resistance region 1041 may be extinguished by controlling voltage application through the gate 1020 . This may be done by enlarging the first region to the edge, or as another example, by converting the first region into a second region, that is, through application of an electric field in the opposite direction.

A current flow between the source 1031 and the drain 1032 may be formed through the third variable low resistance region 1043 .

Since the third variation low resistance region 1043 is formed inside the second variation low resistance region 1042 , current flows from the source 1031 to the drain 1032 through the third variation low resistance region 1043 . The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the second variable low resistance region 1042 .

The length of this current flow can be the resistance to the current from the source 1031 to the drain 1032, and the longer the length of the current flow from the source 1031 to the drain 1032, the greater the resistance. there is.

Therefore, the measurement of the current from source 1031 to drain 1032 through third variable low resistance region 1043 is from source 1031 to drain 1032 through second variable low resistance region 1042 . It may be greater than the measured value of the current.

Therefore, as shown in FIG. 30 , in the case where only the third variable low resistance region 1043 is generated, the current flow between the source 1031 and the drain 1032 is formed through the third variable low resistance region 1043 in FIGS. 28 and FIG. You can store information with a value other than 29.

Also, referring to FIG. 31 , by controlling the size of the polarization region through voltage control through the gate 1020 , the size of the first region may be formed to reach the fourth low-variable resistance region 1044 , which Through this, only the fourth variable low resistance region 1044 is formed, and the first variable low resistance region 1041 to the third variable low resistance region 1043 are not generated.

If the first variation low resistance region 1041 is formed, the fourth variation low resistance region 1044 may be formed after the first variation low resistance region 1041 is removed through initialization. For example, the first variable low resistance region 1041 may be extinguished by controlling voltage application through the gate 1020 . This may be done by enlarging the first region to the edge, or as another example, by converting the first region into a second region, that is, through application of an electric field in the opposite direction.

A current flow between the source 1031 and the drain 1032 may be formed through the fourth variable low resistance region 1044 .

Since the fourth variation low resistance region 1044 is formed inside the third variation low resistance region 1043 , current flows from the source 1031 to the drain 1032 through the fourth low variation low resistance region 1044 . The length of may be smaller than the length of the flow of current from the source 1031 to the drain 1032 through the third variable low resistance region 1043 .

The length of this current flow can be the resistance to the current from the source 1031 to the drain 1032, and the longer the length of the current flow from the source 1031 to the drain 1032, the greater the resistance. there is.

Therefore, the measurement of the current from source 1031 to drain 1032 through fourth variable low resistance region 1044 is the current from source 1031 to drain 1032 through third variable low resistance region 1043 . It may be greater than the measured value of the current.

Therefore, as shown in FIG. 31 , in the case where only the fourth variable low resistance region 1044 is generated, the current flow between the source 1031 and the drain 1032 through the fourth variable low resistance region 1044 is formed in FIGS. 28 and FIG. 29 and 30 may be stored.

As an alternative embodiment, a plurality of variable low-resistance regions may be simultaneously formed. For example, as shown in FIG. 26, a plurality of variable low resistance regions may be formed by applying the structure of FIG. 5 and the contents of FIGS. 7A to 7D explaining it, and as a specific example, it may be similar to that described in FIG. there is.

In this way, it is possible to store more various types of information, so that it is possible to easily form a memory device with improved directness.

A specific example will be described.

Also, referring to FIG. 32 , it is shown that the second low variation low resistance region 1042 is formed inside the first low variation low resistance region 1041 with respect to the gate 1020 .

One end of the second variation low resistance region 1042 may be connected to the source 1031 and the other end to the drain 1032 .

For example, the second variation low resistance region 1042 may include a shape similar to a portion of a rectangle smaller than the first variation low resistance region 1041 , and the source 1031 is formed to overlap one side of the rectangle, and , a drain 1032 may be formed on the other side.

As an optional embodiment, the second variable low resistance region 1042 may have a shape similar to a quadrangle, and the source 1031 and the drain 1032 may be formed to overlap two opposite sides of the quadrangle.

Since the second variation low resistance region 1042 is formed inside the first variation low resistance region 1041 , the flow of current from the source 1031 to the drain 1032 through the second variation low resistance region 1042 . The length of may be shorter than the length of the flow of current from the source 1031 to the drain 1032 through the first variation low resistance region 1041 .

Compared to the current value when only one of the first variation low resistance region 1041 or the second variation low resistance region 1042 is formed as shown in FIG. 28 or 29, as shown in FIG. 32, the first variation low resistance region 1041 or A current value when all of the second variable low resistance regions 1042 are formed may be greater.

Through this, the memory device 1000 can store information different from that when only one of the first variation low resistance region 1041 or the second variation low resistance region 1042 is formed, thereby improving the degree of integration.

Also, referring to FIG. 33 , it is additionally illustrated that a third low variation low resistance region 1043 is formed inside the second low variation low resistance region 1042 with respect to the gate 1020 .

One end of the third variable low resistance region 1043 may be connected to the source 1031 and the other end to the drain 1032 .

For example, the third variation low resistance region 1043 may include a shape similar to a portion of a rectangle smaller than the second variation low resistance region 1042, and the source 1031 is formed to overlap one side of the rectangle, and , a drain 1032 may be formed on the other side.

As an optional embodiment, the third variable low resistance region 1043 may have a shape similar to a quadrangle, and the source 1031 and the drain 1032 may be formed to overlap two opposite sides of the quadrangle.

Since the third variation low resistance region 1043 is formed inside the second variation low resistance region 1042 , current flows from the source 1031 to the drain 1032 through the third variation low resistance region 1043 . The length of may be shorter than the length of the flow of current from the source 1031 to the drain 1032 through the second variable low resistance region 1042 .

The first fluctuation low resistance region 1041 and the second fluctuation low resistance region 1041 of Fig. 33 are lower than the current values when the first fluctuation low resistance region 1041 and the second fluctuation resistance region 1042 shown in Fig. 32 are formed. When the resistance region 1042 and the third variable low resistance region 1043 are formed, the current value may be larger.

Through this, the memory device 1000 can store information having a value different from that of FIG. 32 , so that the degree of integration can be improved.

Also, referring to FIG. 34 , it is additionally illustrated that a fourth low variation low resistance region 1044 is formed inside the third low variation low resistance region 1043 with respect to the gate 1020 .

One end of the fourth variable low resistance region 1044 may be connected to the source 1031 and the other end to the drain 1032 .

For example, the fourth variation low resistance region 1044 may include a shape similar to a portion of a rectangle smaller than the third low variation low resistance region 1043, and the source 1031 is formed so as to overlap one side of the rectangle, and , a drain 1032 may be formed on the other side.

As an optional embodiment, the fourth low-variance resistance region 1044 may have a shape similar to a quadrangle, and the source 1031 and the drain 1032 may be formed to overlap two opposite sides of the quadrangle.

Since the fourth variation low resistance region 1044 is formed inside the third variation low resistance region 1043 , current flows from the source 1031 to the drain 1032 through the fourth low variation low resistance region 1044 . The length of may be shorter than the length of the flow of current from the source 1031 to the drain 1032 through the third variable low resistance region 1043 .

The first variation low in FIG. 34 is lower than the current value when the first variation low resistance region 1041, the second variation low resistance region 1042, and the third variation low resistance region 1043 shown in FIG. 33 are formed. When the resistance region 1041 , the second variation low resistance region 1042 , the third variation low resistance region 1043 , and the fourth variation low resistance region 1044 are formed, the current value may be greater.

Through this, the memory device 1000 can store information having a value different from that of FIG. 33 , so that the degree of integration can be improved.

The low variation low resistance region memory element formed as described above has the first variation low resistance region 1041 , the second variation low resistance region 1042 , the third variation low resistance region 1043 , or the fourth low variation low resistance region 1043 , as described above. The region 1044 can be used as a non-volatile memory device because it can maintain its state even when the power to the gate 1020 is turned off.

Since the variable low-resistance region memory device is capable of writing/erasing about 10 ¹² times, it may have a memory lifespan of about 10 ⁷ times that of a conventional semiconductor device-based memory device.

In terms of memory speed, the variable low-resistance region memory device can be about 10 ^-9 sec, so that the memory speed can be increased by about 10 ⁶ times compared to the conventional semiconductor device-based memory device.

As such, the variable low-resistance region memory device may be a memory device having very excellent speed and lifespan.

In addition, through the control of the electric field through the gate 1020, only the first variation low resistance region 1041 is formed, the first and second low variation low resistance regions 1041 and 1042 are formed, or the first, second, The three variable low resistance regions 1041 , 1042 , 1043 may be formed, or the first, second, third, and fourth variable low resistance regions 1041 , 1042 , 1043 , 1044 may be formed.

On the other hand, when a current flows between the source 1031 and the drain 1032 , the current value when only the first variable low resistance region 1041 is formed, the first and second variable low resistance regions 1041 and 1042 are The current value when formed, the current value when the first, second, and third variable low-resistance regions 1041, 1042, 1043 are formed, and the first, second, third, and fourth variable low-resistance regions 1041, 1042, 1043 , 1044) may be all different from each other, and different information may be stored using this.

In addition, as described above, only the first variation low resistance region 1041 is formed, only the second low variation low resistance region 1042 is formed, or the third low variation low resistance region is formed through the control of the electric field through the gate 1020 , as described above. Only the region 1043 may be formed, or only the fourth variation low resistance region 1044 may be formed.

And, the current value when only the first variation low resistance region 1041 is formed, the current value when only the second variation low resistance region 1042 is formed, the current value when only the third low variation low resistance region 1043 is formed, When only the fourth variable low-resistance region 1044 is formed, all current values are different, and different information can be stored by using them.

Through this, the degree of freedom in memory design is increased and high information can be integrated.

35 is a diagram for explaining an example of an operation of a memory device according to an embodiment of the present invention.

Referring to FIG. 35 , after a time t1 has elapsed, a constant one current value is stably maintained, and after a time t2 has elapsed, the current value is stably maintained, and subsequently after a time t3 has elapsed. It shows stably maintaining a current value larger than that.

For example, the case of stably maintaining a constant one current value after time t1 has elapsed may be described in FIG. 28, and subsequently, the case of stably maintaining a larger current value after time t2 has elapsed FIG. 29 may be explained, and the case of stably maintaining a current value larger than that after time t3 has elapsed may explain FIG. 30 .

As another example, the case in which a constant one current value is stably maintained after time t1 has elapsed may be described in FIG. 28 , and a case of stably maintaining a current value larger than that stably after time t2 has elapsed may explain FIG. 32 , and the case of stably maintaining a current greater than that after time t3 may explain FIG. 33 .

As described above, the current value varies in each case, and various information can be stored accordingly. As described above, the present invention has been described with reference to the embodiment shown in the drawings, but this is only exemplary, and it is common in the art to It will be appreciated by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

The specific implementations described in the embodiment are only embodiments, and do not limit the scope of the embodiment in any way. In addition, unless there is a specific reference such as "essential", "importantly", etc., it may not be a necessary component for the application of the present invention.

In the specification of embodiments (especially in the claims), the use of the term “the” and similar referential terms may be used in both the singular and the plural. In addition, when a range is described in the embodiment, it includes the invention to which individual values belonging to the range are applied (unless there is a description to the contrary), and each individual value constituting the range is described in the detailed description. . Finally, the steps constituting the method according to the embodiment may be performed in an appropriate order, unless the order is clearly stated or there is no description to the contrary. The embodiments are not necessarily limited according to the description order of the steps. The use of all examples or exemplary terms (eg, etc.) in the embodiment is merely for describing the embodiment in detail, and unless it is limited by the claims, the scope of the embodiment is limited by the examples or exemplary terminology. it is not In addition, those skilled in the art will appreciate that various modifications, combinations, and changes may be made in accordance with design conditions and factors within the scope of the appended claims or their equivalents.

10, 100, 200: electronic circuit
11, 21, 110, 210: active layer
12, 120, 220: applied electrode
131, 132, 231, 232: connection electrode part
VL: fluctuating low resistance region
300, 400, 500, 600, 700, 800, 900, 1000: memory element
320, 420, 520, 620, 720, 821, 822, 920, 1020: gate

Claims (10)

a base comprising a spontaneously polarizable material;
a gate disposed adjacent to the base;
a polarization region formed in the base by applying an electric field to the base through the gate and formed to correspond to an entire thickness in a thickness direction of the base;
a variable low resistance region corresponding to the boundary of the polarization region and including a region having a lower electrical resistance than other adjacent regions;
a source spaced apart from the gate and connected to the variable low resistance region; and
and a drain spaced apart from the gate and connected to the variable low resistance region;
The variable low resistance region is formed to selectively include at least one of a first variable low resistance region and a second variable low resistance region through the control of the gate;
The first variation low resistance region surrounds the gate and is formed to correspond to the entire thickness in the thickness direction of the base,
A second variation low resistance region surrounds the gate, is disposed closer to the gate than the first variation low resistance region, and is formed to correspond to an entire thickness in a thickness direction of the base,
The source extends to have a length in one direction and has both sides in a direction crossing the length,
The drain extends to have a length in one direction and has both sides in a direction crossing the length,
Two ends of the second variation low resistance region are connected to both sides of the source, and the two ends of the first variation low resistance region are further away from the gate than the two ends of the second variation low resistance region connected,
The other two ends of the second variable resistance region are connected to both sides of the drain, and the other two ends of the first variable resistance region are farther from the gate than the other two ends of the second variable resistance region. A variable low-resistance region-based memory device comprising two ends connected to each other. According to claim 1,
and a length of the first variable resistance region connecting the source and drain is greater than a length of the second variable resistance region connecting the source and drain. According to claim 1,
and the variable low resistance region includes a third variable low resistance region spaced apart from the first variable low resistance region and the second variable low resistance region. According to claim 1,
A variable low-resistance region-based memory device configured to store different information according to the formation of the first variable-low-resistance region or the second variable-low-resistance region. According to claim 1,
The variable low-resistance region controls an electric field through the gate to generate or disappear according to the control of the polarization region. According to claim 1,
The variable low-resistance region-based memory device is maintained even when the electric field applied through the gate is removed. For a variable low-resistance region-based memory device comprising a base comprising a spontaneously polarizable material, a gate disposed adjacent to the base, a source spaced apart from the gate, and a drain spaced apart from the gate, the memory device comprising:
forming a polarization region of the base by applying an electric field to the base through the gate; and
A current between the source and drain through the source and drain connected to the variable low resistance region by forming a variable low resistance region including a region having a lower electrical resistance than other adjacent regions corresponding to the boundary of the polarization region comprising the step of allowing a flow of
The variable low resistance region is formed to selectively include at least one of a first variable low resistance region and a second variable low resistance region through the control of the gate;
The first variation low resistance region surrounds the gate and is formed to correspond to the entire thickness in the thickness direction of the base,
The second variation low resistance region surrounds the gate, is disposed closer to the gate than the first variation low resistance region, and is formed to correspond to the entire thickness in the thickness direction of the base,
The source extends to have a length in one direction and has both sides in a direction crossing the length,
The drain extends to have a length in one direction and has both sides in a direction crossing the length,
Two ends of the second variation low resistance region are connected to both sides of the source, and two ends of the first variation low resistance region are connected to a region farther from the gate than the two ends of the second variation low resistance region become,
The other two ends of the second variable resistance region are connected to both side surfaces of the drain, and the other two ends of the first variable resistance region are farther from the gate than the other two ends of the second variable resistance region. A method for controlling a variable low-resistance region-based memory device comprising the ends being connected. 8. The method of claim 7,
and a length of the first variable resistance region connecting the source and drain is greater than a length of the second variable resistance region connecting the source and drain. 8. The method of claim 7,
and measuring a current between the source and the drain as the first variation low resistance region or the second variation low resistance region is formed while controlling the gate. 8. The method of claim 7,
and controlling an electric field through the gate to generate or destroy the variable low resistance region according to the control of the polarization region.

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