KR20190021184A - 구리 인터커넥트들을 위한 시드 층들 - Google Patents

구리 인터커넥트들을 위한 시드 층들 Download PDF

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KR20190021184A
KR20190021184A KR1020180097909A KR20180097909A KR20190021184A KR 20190021184 A KR20190021184 A KR 20190021184A KR 1020180097909 A KR1020180097909 A KR 1020180097909A KR 20180097909 A KR20180097909 A KR 20180097909A KR 20190021184 A KR20190021184 A KR 20190021184A
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Prior art keywords
layer
copper
ruthenium
substrate
forming
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Korean (ko)
Inventor
즈위안 우
멩 추 쩽
메훌 비. 나익
벤-리 슈
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어플라이드 머티어리얼스, 인코포레이티드
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Publication of KR20190021184A publication Critical patent/KR20190021184A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
KR1020180097909A 2017-08-22 2018-08-22 구리 인터커넥트들을 위한 시드 층들 Ceased KR20190021184A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762548604P 2017-08-22 2017-08-22
US62/548,604 2017-08-22
US16/102,533 2018-08-13
US16/102,533 US10847463B2 (en) 2017-08-22 2018-08-13 Seed layers for copper interconnects

Publications (1)

Publication Number Publication Date
KR20190021184A true KR20190021184A (ko) 2019-03-05

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KR1020180097909A Ceased KR20190021184A (ko) 2017-08-22 2018-08-22 구리 인터커넥트들을 위한 시드 층들

Country Status (6)

Country Link
US (1) US10847463B2 (enExample)
EP (1) EP3447793B1 (enExample)
JP (2) JP7634930B2 (enExample)
KR (1) KR20190021184A (enExample)
CN (1) CN109461698B (enExample)
TW (1) TWI803510B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022005948A1 (en) * 2020-06-28 2022-01-06 Applied Materials, Inc. Impurity removal in doped ald tantalum nitride
WO2025005521A1 (ko) * 2023-06-30 2025-01-02 주성엔지니어링(주) 전극 형성 방법

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11177162B2 (en) * 2019-09-17 2021-11-16 International Business Machines Corporation Trapezoidal interconnect at tight BEOL pitch
CN114664656A (zh) * 2020-05-22 2022-06-24 北京屹唐半导体科技股份有限公司 使用臭氧气体和氢自由基的工件加工
US11764157B2 (en) * 2020-07-23 2023-09-19 Applied Materials, Inc. Ruthenium liner and cap for back-end-of-line applications

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7910165B2 (en) * 2002-06-04 2011-03-22 Applied Materials, Inc. Ruthenium layer formation for copper film deposition
US7101790B2 (en) 2003-03-28 2006-09-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a robust copper interconnect by dilute metal doping
JP2006097044A (ja) 2004-09-28 2006-04-13 L'air Liquide Sa Pour L'etude & L'exploitation Des Procede S Georges Claude 成膜用前駆体、ルテニウム含有膜の成膜方法、ルテニウム膜の成膜方法、ルテニウム酸化物膜の成膜方法およびルテニウム酸塩膜の成膜方法
US7265048B2 (en) * 2005-03-01 2007-09-04 Applied Materials, Inc. Reduction of copper dewetting by transition metal deposition
US20060246699A1 (en) * 2005-03-18 2006-11-02 Weidman Timothy W Process for electroless copper deposition on a ruthenium seed
JP2008098449A (ja) * 2006-10-12 2008-04-24 Ebara Corp 基板処理装置及び基板処理方法
US20080164613A1 (en) 2007-01-10 2008-07-10 International Business Machines Corporation ULTRA-THIN Cu ALLOY SEED FOR INTERCONNECT APPLICATION
US20100200991A1 (en) * 2007-03-15 2010-08-12 Rohan Akolkar Dopant Enhanced Interconnect
US20080223287A1 (en) * 2007-03-15 2008-09-18 Lavoie Adrien R Plasma enhanced ALD process for copper alloy seed layers
US7659204B2 (en) * 2007-03-26 2010-02-09 Applied Materials, Inc. Oxidized barrier layer
US7737028B2 (en) 2007-09-28 2010-06-15 Applied Materials, Inc. Selective ruthenium deposition on copper materials
JP2009116952A (ja) * 2007-11-06 2009-05-28 Hitachi Global Storage Technologies Netherlands Bv 垂直磁気記録媒体およびこれを用いた磁気記憶装置
TW200951241A (en) 2008-05-30 2009-12-16 Sigma Aldrich Co Methods of forming ruthenium-containing films by atomic layer deposition
US7964497B2 (en) * 2008-06-27 2011-06-21 International Business Machines Corporation Structure to facilitate plating into high aspect ratio vias
US20090321935A1 (en) 2008-06-30 2009-12-31 O'brien Kevin Methods of forming improved electromigration resistant copper films and structures formed thereby
US8084104B2 (en) 2008-08-29 2011-12-27 Asm Japan K.K. Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition
JP2010215982A (ja) 2009-03-18 2010-09-30 Tosoh Corp ルテニウム錯体有機溶媒溶液を用いたルテニウム含有膜製造方法、及びルテニウム含有膜
JP2012074608A (ja) * 2010-09-29 2012-04-12 Tokyo Electron Ltd 配線形成方法
CN102332426A (zh) * 2011-09-23 2012-01-25 复旦大学 一种用于纳米集成电路的铜扩散阻挡层的制备方法
US9076661B2 (en) * 2012-04-13 2015-07-07 Applied Materials, Inc. Methods for manganese nitride integration
US9142509B2 (en) * 2012-04-13 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Copper interconnect structure and method for forming the same
CN102903699A (zh) * 2012-10-15 2013-01-30 复旦大学 一种铜互连结构及其制备方法
US20140134351A1 (en) * 2012-11-09 2014-05-15 Applied Materials, Inc. Method to deposit cvd ruthenium
CN103266304B (zh) 2013-05-31 2015-12-23 江苏科技大学 一种高热稳定性无扩散阻挡层Cu(Ru)合金材料的制备方法
US9984975B2 (en) * 2014-03-14 2018-05-29 Taiwan Semiconductor Manufacturing Company Barrier structure for copper interconnect
JP6278827B2 (ja) 2014-05-14 2018-02-14 株式会社Adeka 銅化合物、薄膜形成用原料及び薄膜の製造方法
US20160032455A1 (en) 2014-07-31 2016-02-04 Applied Materials, Inc. High through-put and low temperature ald copper deposition and integration
US9768060B2 (en) * 2014-10-29 2017-09-19 Applied Materials, Inc. Systems and methods for electrochemical deposition on a workpiece including removing contamination from seed layer surface prior to ECD
US10002834B2 (en) 2015-03-11 2018-06-19 Applied Materials, Inc. Method and apparatus for protecting metal interconnect from halogen based precursors
KR20160123793A (ko) * 2015-04-17 2016-10-26 포항공과대학교 산학협력단 이중층 구조를 가지는 저항변화메모리 및 이중층 구조를 가지는 저항변화메모리의 제조방법
CN105355620B (zh) * 2015-12-17 2018-06-22 上海集成电路研发中心有限公司 一种铜互连结构及其制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022005948A1 (en) * 2020-06-28 2022-01-06 Applied Materials, Inc. Impurity removal in doped ald tantalum nitride
US11410881B2 (en) 2020-06-28 2022-08-09 Applied Materials, Inc. Impurity removal in doped ALD tantalum nitride
US12243774B2 (en) 2020-06-28 2025-03-04 Applied Materials, Inc. Impurity removal in doped ALD tantalum nitride
WO2025005521A1 (ko) * 2023-06-30 2025-01-02 주성엔지니어링(주) 전극 형성 방법

Also Published As

Publication number Publication date
CN109461698A (zh) 2019-03-12
TW201920735A (zh) 2019-06-01
CN109461698B (zh) 2024-04-12
EP3447793A1 (en) 2019-02-27
JP2023182638A (ja) 2023-12-26
JP2019062190A (ja) 2019-04-18
TWI803510B (zh) 2023-06-01
US20190067201A1 (en) 2019-02-28
JP7634930B2 (ja) 2025-02-25
US10847463B2 (en) 2020-11-24
EP3447793B1 (en) 2021-01-06

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