KR20180014689A - 분할 버스트 대역폭 중재를 위한 방법 및 장치 - Google Patents

분할 버스트 대역폭 중재를 위한 방법 및 장치 Download PDF

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Publication number
KR20180014689A
KR20180014689A KR1020177031595A KR20177031595A KR20180014689A KR 20180014689 A KR20180014689 A KR 20180014689A KR 1020177031595 A KR1020177031595 A KR 1020177031595A KR 20177031595 A KR20177031595 A KR 20177031595A KR 20180014689 A KR20180014689 A KR 20180014689A
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KR
South Korea
Prior art keywords
channel
data transmissions
programmable
data
arbitration schemes
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Withdrawn
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KR1020177031595A
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English (en)
Korean (ko)
Inventor
신 스티드만
용 유엔용스굴
자코부스 알버투스 반 에덴
데이비드 오텐
나빈 라지
프라샨스 푸리파카
프라산나 수라칸티
Original Assignee
마이크로칩 테크놀로지 인코포레이티드
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Publication of KR20180014689A publication Critical patent/KR20180014689A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30—

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Bus Control (AREA)
KR1020177031595A 2015-06-01 2016-06-01 분할 버스트 대역폭 중재를 위한 방법 및 장치 Withdrawn KR20180014689A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562169354P 2015-06-01 2015-06-01
US62/169,354 2015-06-01
US15/169,352 US10318457B2 (en) 2015-06-01 2016-05-31 Method and apparatus for split burst bandwidth arbitration
US15/169,352 2016-05-31
PCT/US2016/035156 WO2016196549A1 (en) 2015-06-01 2016-06-01 Method and apparatus for split burst bandwidth arbitration

Publications (1)

Publication Number Publication Date
KR20180014689A true KR20180014689A (ko) 2018-02-09

Family

ID=57397562

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020177031595A Withdrawn KR20180014689A (ko) 2015-06-01 2016-06-01 분할 버스트 대역폭 중재를 위한 방법 및 장치

Country Status (7)

Country Link
US (1) US10318457B2 (enExample)
EP (1) EP3304327B1 (enExample)
JP (1) JP2018516406A (enExample)
KR (1) KR20180014689A (enExample)
CN (1) CN107667357B (enExample)
TW (1) TW201701161A (enExample)
WO (1) WO2016196549A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106294233B (zh) * 2015-06-29 2019-05-03 华为技术有限公司 一种直接内存访问的传输控制方法及装置
US10838896B2 (en) 2018-10-15 2020-11-17 Texas Instruments Incorporated Split direct memory access (DMA)
CN110138553B (zh) * 2019-05-10 2022-08-19 郑州信大捷安信息技术股份有限公司 一种IPSec VPN网关数据包处理装置及方法
US20250291754A1 (en) * 2024-03-12 2025-09-18 Texas Instruments Incorporated Adaptive Burst Transfer for Direct Memory Access

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371517A (en) * 1991-11-08 1994-12-06 Texas Instruments Incorporated Video interface palette, systems and method
US7752400B1 (en) 2000-12-14 2010-07-06 F5 Networks, Inc. Arbitration and crossbar device and method
JP5040050B2 (ja) * 2001-06-12 2012-10-03 富士通株式会社 複数チャネルｄｍａコントローラおよびプロセッサシステム
EP1899828B1 (en) * 2005-06-30 2009-11-25 Freescale Semiconductor, Inc. Device and method for arbitrating between direct memory access task requests
JP4470183B2 (ja) * 2006-08-28 2010-06-02 エルピーダメモリ株式会社 半導体記憶装置
CN101150486A (zh) * 2007-11-15 2008-03-26 曙光信息产业(北京)有限公司 一种零拷贝缓冲区队列网络数据接收的管理方法
US7877524B1 (en) * 2007-11-23 2011-01-25 Pmc-Sierra Us, Inc. Logical address direct memory access with multiple concurrent physical ports and internal switching
JP2010054989A (ja) * 2008-08-29 2010-03-11 Mitsubishi Electric Corp 階調制御方法および表示装置
US8812898B1 (en) * 2012-09-27 2014-08-19 Cadence Design Systems, Inc. System and method for transfer of data between memory with dynamic error recovery
US8880756B1 (en) 2013-07-01 2014-11-04 Atmel Corporation Direct memory access controller
CN104536921A (zh) * 2015-01-19 2015-04-22 浪潮电子信息产业股份有限公司 一种edma控制器分离式并行数据通道的设计方法

Also Published As

Publication number Publication date
US10318457B2 (en) 2019-06-11
TW201701161A (zh) 2017-01-01
US20160350246A1 (en) 2016-12-01
EP3304327A1 (en) 2018-04-11
CN107667357B (zh) 2021-05-25
JP2018516406A (ja) 2018-06-21
CN107667357A (zh) 2018-02-06
EP3304327B1 (en) 2020-01-08
WO2016196549A1 (en) 2016-12-08

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Date Code Title Description
PA0105 International application

Patent event date: 20171031

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination