JP2018516406A - 分割バースト帯域幅調停のための方法および装置 - Google Patents

分割バースト帯域幅調停のための方法および装置 Download PDF

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Publication number
JP2018516406A
JP2018516406A JP2017561329A JP2017561329A JP2018516406A JP 2018516406 A JP2018516406 A JP 2018516406A JP 2017561329 A JP2017561329 A JP 2017561329A JP 2017561329 A JP2017561329 A JP 2017561329A JP 2018516406 A JP2018516406 A JP 2018516406A
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JP
Japan
Prior art keywords
data transfer
scheme
channel
embedded system
arbitration
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Pending
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JP2017561329A
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English (en)
Japanese (ja)
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JP2018516406A5 (enExample
Inventor
ショーン スティードマン，
ショーン スティードマン，
ヨン ユエンヨンスグール，
ヨン ユエンヨンスグール，
イーデン， ジャコバス アルベルトゥス バン
イーデン， ジャコバス アルベルトゥス バン
デイビッド オッテン，
デイビッド オッテン，
ナヴィーン ラジ，
ナヴィーン ラジ，
プレシャント プリパカ，
プレシャント プリパカ，
プラサンナ スラカンティ，
プラサンナ スラカンティ，
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Microchip Technology Inc
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Microchip Technology Inc
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Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of JP2018516406A publication Critical patent/JP2018516406A/ja
Publication of JP2018516406A5 publication Critical patent/JP2018516406A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Bus Control (AREA)
JP2017561329A 2015-06-01 2016-06-01 分割バースト帯域幅調停のための方法および装置 Pending JP2018516406A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562169354P 2015-06-01 2015-06-01
US62/169,354 2015-06-01
US15/169,352 US10318457B2 (en) 2015-06-01 2016-05-31 Method and apparatus for split burst bandwidth arbitration
US15/169,352 2016-05-31
PCT/US2016/035156 WO2016196549A1 (en) 2015-06-01 2016-06-01 Method and apparatus for split burst bandwidth arbitration

Publications (2)

Publication Number Publication Date
JP2018516406A true JP2018516406A (ja) 2018-06-21
JP2018516406A5 JP2018516406A5 (enExample) 2019-06-13

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JP2017561329A Pending JP2018516406A (ja) 2015-06-01 2016-06-01 分割バースト帯域幅調停のための方法および装置

Country Status (7)

Country Link
US (1) US10318457B2 (enExample)
EP (1) EP3304327B1 (enExample)
JP (1) JP2018516406A (enExample)
KR (1) KR20180014689A (enExample)
CN (1) CN107667357B (enExample)
TW (1) TW201701161A (enExample)
WO (1) WO2016196549A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106294233B (zh) * 2015-06-29 2019-05-03 华为技术有限公司 一种直接内存访问的传输控制方法及装置
US10838896B2 (en) 2018-10-15 2020-11-17 Texas Instruments Incorporated Split direct memory access (DMA)
CN110138553B (zh) * 2019-05-10 2022-08-19 郑州信大捷安信息技术股份有限公司 一种IPSec VPN网关数据包处理装置及方法
US20250291754A1 (en) * 2024-03-12 2025-09-18 Texas Instruments Incorporated Adaptive Burst Transfer for Direct Memory Access

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002366507A (ja) * 2001-06-12 2002-12-20 Fujitsu Ltd 複数チャネルｄｍａコントローラおよびプロセッサシステム
JP2009505169A (ja) * 2005-06-30 2009-02-05 フリースケール セミコンダクター インコーポレイテッド ダイレクトメモリアクセスタスク要求のアービトレーションを行うためのデバイスおよび方法

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US5371517A (en) * 1991-11-08 1994-12-06 Texas Instruments Incorporated Video interface palette, systems and method
US7752400B1 (en) 2000-12-14 2010-07-06 F5 Networks, Inc. Arbitration and crossbar device and method
JP4470183B2 (ja) * 2006-08-28 2010-06-02 エルピーダメモリ株式会社 半導体記憶装置
CN101150486A (zh) * 2007-11-15 2008-03-26 曙光信息产业(北京)有限公司 一种零拷贝缓冲区队列网络数据接收的管理方法
US7877524B1 (en) * 2007-11-23 2011-01-25 Pmc-Sierra Us, Inc. Logical address direct memory access with multiple concurrent physical ports and internal switching
JP2010054989A (ja) * 2008-08-29 2010-03-11 Mitsubishi Electric Corp 階調制御方法および表示装置
US8812898B1 (en) * 2012-09-27 2014-08-19 Cadence Design Systems, Inc. System and method for transfer of data between memory with dynamic error recovery
US8880756B1 (en) 2013-07-01 2014-11-04 Atmel Corporation Direct memory access controller
CN104536921A (zh) * 2015-01-19 2015-04-22 浪潮电子信息产业股份有限公司 一种edma控制器分离式并行数据通道的设计方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002366507A (ja) * 2001-06-12 2002-12-20 Fujitsu Ltd 複数チャネルｄｍａコントローラおよびプロセッサシステム
JP2009505169A (ja) * 2005-06-30 2009-02-05 フリースケール セミコンダクター インコーポレイテッド ダイレクトメモリアクセスタスク要求のアービトレーションを行うためのデバイスおよび方法

Also Published As

Publication number Publication date
KR20180014689A (ko) 2018-02-09
US10318457B2 (en) 2019-06-11
TW201701161A (zh) 2017-01-01
US20160350246A1 (en) 2016-12-01
EP3304327A1 (en) 2018-04-11
CN107667357B (zh) 2021-05-25
CN107667357A (zh) 2018-02-06
EP3304327B1 (en) 2020-01-08
WO2016196549A1 (en) 2016-12-08

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