KR20140081856A - 패키지 기판으로의 와이어 본드 없이 어셈블리에서 신호 단자의 복제 세트를 이용한 스터브 최소화 - Google Patents

패키지 기판으로의 와이어 본드 없이 어셈블리에서 신호 단자의 복제 세트를 이용한 스터브 최소화 Download PDF

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KR20140081856A
KR20140081856A KR1020147012125A KR20147012125A KR20140081856A KR 20140081856 A KR20140081856 A KR 20140081856A KR 1020147012125 A KR1020147012125 A KR 1020147012125A KR 20147012125 A KR20147012125 A KR 20147012125A KR 20140081856 A KR20140081856 A KR 20140081856A
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South Korea
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microelectronic
package
terminal
terminals
signal
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Korean (ko)
Inventor
리차드 드윗 크리스프
와엘 조니
벨가셈 하바
프랭크 람브레히트
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인벤사스 코포레이션
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Priority claimed from US13/439,228 external-priority patent/US8659139B2/en
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Publication of KR20140081856A publication Critical patent/KR20140081856A/ko
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/853—On the same surface
    • H10W72/859—Bump connectors and bond wires
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/879—Bump connectors and bond wires
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/941—Dispositions of bond pads
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
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    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
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    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
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    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
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    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/00—Package configurations
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
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  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Wire Bonding (AREA)
KR1020147012125A 2011-10-03 2012-09-26 패키지 기판으로의 와이어 본드 없이 어셈블리에서 신호 단자의 복제 세트를 이용한 스터브 최소화 Withdrawn KR20140081856A (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201161542553P 2011-10-03 2011-10-03
US61/542,553 2011-10-03
US201261600483P 2012-02-17 2012-02-17
US61/600,483 2012-02-17
US13/439,228 2012-04-04
US13/439,228 US8659139B2 (en) 2011-10-03 2012-04-04 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
PCT/US2012/057173 WO2013052321A2 (en) 2011-10-03 2012-09-26 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

Publications (1)

Publication Number Publication Date
KR20140081856A true KR20140081856A (ko) 2014-07-01

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Application Number Title Priority Date Filing Date
KR1020147012125A Withdrawn KR20140081856A (ko) 2011-10-03 2012-09-26 패키지 기판으로의 와이어 본드 없이 어셈블리에서 신호 단자의 복제 세트를 이용한 스터브 최소화
KR1020147012058A Withdrawn KR20140073559A (ko) 2011-10-03 2012-09-26 패키지 기판으로의 와이어 본드 없이 어셈블리에서 신호 단자의 복제 세트를 이용한 스터브 최소화

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KR1020147012058A Withdrawn KR20140073559A (ko) 2011-10-03 2012-09-26 패키지 기판으로의 와이어 본드 없이 어셈블리에서 신호 단자의 복제 세트를 이용한 스터브 최소화

Country Status (5)

Country Link
EP (2) EP2764512A2 (https=)
JP (3) JP5966009B2 (https=)
KR (2) KR20140081856A (https=)
TW (4) TW201639110A (https=)
WO (3) WO2013052320A1 (https=)

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TWI615717B (zh) * 2016-01-25 2018-02-21 凌陽科技股份有限公司 高階製程晶片與低階製程晶片的資料傳輸方法以及使用其之積體電路
US20180005944A1 (en) * 2016-07-02 2018-01-04 Intel Corporation Substrate with sub-interconnect layer
US10607977B2 (en) 2017-01-20 2020-03-31 Google Llc Integrated DRAM with low-voltage swing I/O
US10096362B1 (en) 2017-03-24 2018-10-09 Crossbar, Inc. Switching block configuration bit comprising a non-volatile memory cell
JP7059970B2 (ja) * 2019-03-11 2022-04-26 株式会社デンソー 半導体装置
KR102026163B1 (ko) * 2019-07-02 2019-09-27 김복문 반도체 패키지의 배선 보정방법
TWI768294B (zh) 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法

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WO2013052321A3 (en) 2013-10-17
WO2013052324A2 (en) 2013-04-11
TWI527188B (zh) 2016-03-21
TWI520284B (zh) 2016-02-01
JP5964438B2 (ja) 2016-08-03
KR20140073559A (ko) 2014-06-16
EP2764513B1 (en) 2017-04-19
TW201322412A (zh) 2013-06-01
EP2764512A2 (en) 2014-08-13
JP2016195269A (ja) 2016-11-17
WO2013052324A3 (en) 2013-10-31
WO2013052321A2 (en) 2013-04-11
JP2015503214A (ja) 2015-01-29
TW201324708A (zh) 2013-06-16
JP5966009B2 (ja) 2016-08-10
WO2013052320A4 (en) 2013-07-11
TW201639110A (zh) 2016-11-01
TWI546930B (zh) 2016-08-21
TW201320297A (zh) 2013-05-16
EP2764513A2 (en) 2014-08-13
WO2013052320A1 (en) 2013-04-11

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