KR20130115907A - Display device - Google Patents

Abstract

PURPOSE: A display device is provided to improve output characteristics by enhancing turn on/off characteristics of a depletion mode TFT. CONSTITUTION: A pull up transistor (TPU1) outputs an X clock signal to the output terminal of an n stage in response to a potential of node Q. A pull down transistor (TPD1) outputs a first low potential voltage to the output terminal of the n stage in response to a potential of node QB. A node Q charging and discharging unit (T4) charges or discharges the node Q to a voltage of the output terminal of an n-1 stage in response to an X-1 clock signal. A node QB charging and discharging unit (CLK[X+2]) charges or discharges the node QB in response to an X+2 clock signal.

Description

[0001]

An embodiment of the present invention relates to a display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as organic light emitting display (OLED), liquid crystal display (LCD), plasma display panel (PDP), and the like is increasing.

Some of the aforementioned display devices, for example, a liquid crystal display or an organic light emitting display device, include a display panel including a plurality of subpixels arranged in a matrix form and a driving unit for driving the display panel. The driver includes a gate driver for supplying a gate signal (or scan signal) to the display panel and a data driver for supplying a data signal to the display panel.

In the above display device, when a gate signal and a data signal are supplied to subpixels arranged in a matrix form, the selected subpixel emits light, thereby displaying an image.

The gate driver outputting the gate signal is classified into an external circuit mounted on an external substrate of the display panel in the form of an integrated circuit and an embedded type directly formed on the display panel in the form of a gate in panel formed with a thin film transistor process.

Since the gate driver is composed of a plurality of thin film transistors (hereinafter, TFTs), the performance depends on the characteristics of the TFTs. TFTs used in the gate driver include an enhancement mode in which the threshold voltage is located in the positive (+) direction and a depletion mode in which the threshold voltage is located in the negative (-) direction.

In the case of the depletion mode TFT, the threshold voltage is shifted in the negative (-) direction, so that the current blocking function (turn off function) is not properly performed at Vgs = 0V. Therefore, current leakage occurs in the turned off pull-down transistor, and as a result, the gate signal is not normally output.

Therefore, when the gate driver is formed in a built-in type, there is a need for a method of avoiding malfunction of the circuit and improving operation characteristics even when using the depletion mode TFT as well as the enhancement mode TFT.

Embodiments of the present invention for solving the above-described problems of the related art include a gate driver capable of improving output characteristics by improving turn-on / off operation characteristics of a depletion mode TFT as well as an enhancement mode TFT. It is to provide a display device.

Embodiment of the present invention by the above-described problem solving means, the display panel; And a shift register connected to the display panel and outputting clock signals overlapping some sections, and a shift register configured to shift gate output pulses in response to the clock signals, wherein the nth stage of the stages is a Q node. A pull-up transistor for outputting the X-th clock signal to the output terminal of the nth stage in response to the potential of?, A pull-down transistor for outputting the first low potential voltage to the output terminal of the nth stage in response to the potential of the QB node, and a Q node A display including a Q node charging and discharging unit for charging and discharging at the output terminal voltage of the n-th stage in response to the X-1 clock signal, and a QB node charging and discharging unit for charging and discharging the QB node in response to the X + 2 clock signal. Provide a device.

In the pull-up transistor, the gate electrode is connected to the Q node, the first electrode is connected to the X clock signal terminal, the second electrode is connected to the output terminal, and the pull-down transistor is connected to the gate electrode of the QB node, and the first electrode is connected to the output terminal. The second electrode is connected to the first low potential voltage terminal, the Q node charge / discharge unit is connected to the gate electrode at the X-1 clock signal terminal, and the first electrode is connected to the output node of the n-1 stage, and is connected to the Q node. The second electrode may be connected, and the QB node charging and discharging unit may include a wiring connected between the X + 2 clock signal terminal and the gate electrode of the pull-down transistor.

The nth stage may include a first transistor configured to discharge the Q node to the first low potential voltage in response to the potential of the QB node.

The QB node charging and discharging unit includes a second transistor that charges the QB node to a high potential voltage in response to the X + 2 clock signal, and a third transistor that discharges the QB node to the first low potential voltage in response to the Q node potential. can do.

The QB node charging and discharging unit has a 2-1 transistor connected to a gate electrode and a first electrode at a high potential voltage terminal, a gate electrode connected to a second electrode of a 2-1 transistor, and a first electrode connected to a high potential voltage terminal. A 2-1 transistor, a 3-1 transistor having a gate electrode connected to the Q node, a first electrode connected to the second electrode of the 2-1 transistor, and a second electrode connected to the first low potential voltage terminal; The gate electrode may be connected to the Q node, the second electrode of the second-2 transistor, and the first electrode connected to the QB node, and the third-2 transistor connected to the second electrode at the first low potential voltage terminal.

The QB node charging and discharging unit discharges the QB node to a second low potential voltage lower than the first low potential voltage in response to the potential of the Q node, and then charges the QB node to a high potential voltage in response to the potential and high potential voltage of the Q node. You can.

The QB node charge / discharge unit includes a 2-1 transistor having a gate electrode and a first electrode connected to a high potential voltage terminal, a second electrode connected to a second electrode of a 21st transistor and a first electrode connected to a high potential voltage terminal. A -2 transistor, a 3-1 transistor connected with a gate electrode to a Q node, a first electrode connected to a second electrode of a 2-1 transistor, and a second electrode connected to a first low potential voltage terminal, and a Q node The third electrode may include a third electrode connected to a gate electrode, a second electrode connected to a second electrode and a QB node of the second transistor, and a second electrode connected to a second low potential voltage terminal.

The Q-node charge and discharge unit has a 4-1 transistor connected to a gate electrode connected to the X-1 clock signal terminal and a first electrode connected to an output terminal of the n-1 stage, and a gate electrode connected to the X-1 clock signal terminal. And a 4-2 transistor connected to the second electrode of the 4-1 transistor and a second electrode connected to the Q node, a gate electrode connected to the X clock signal terminal, and a first electrode connected to the output terminal of the nth stage. The first electrode may include a 4-3 transistor having a second electrode connected to the first electrode of the 4-2 transistor.

The QB node charging and discharging unit includes a second transistor having a gate electrode and a first electrode connected to a high potential voltage terminal, a second electrode connected to a QB node, a gate electrode connected to a Q node, and a first electrode connected to a QB node. The third transistor may include a third transistor connected to a first potential voltage terminal or a second potential voltage terminal.

The logic low voltage of the clock signals may be lower than the first low potential voltage.

According to the embodiment of the present invention, even when the depletion mode TFT as well as the enhancement mode TFT is applied, the voltage Vgs between the gate sources of the TFTs is made negative and the turn-on / off operation characteristics of the TFTs are improved to improve output characteristics. There is an effect of providing a display device including a gate driver that can be improved.

1 is a schematic block diagram of a display device;
2 is a configuration diagram of stages constituting a shift register.
3 is a diagram showing a threshold voltage according to a mode of a TFT constituting a shift register.
4 is a circuit diagram of an nth stage according to a first embodiment of the present invention;
5 is an input / output signal waveform diagram of an nth stage.
6 is a simulated waveform diagram of a Q node and an output stage.
7 is a circuit diagram of an nth stage according to a second embodiment of the present invention;
8 is a circuit diagram of an nth stage according to a third embodiment of the present invention;
9 is a circuit diagram of an nth stage according to a fourth embodiment of the present invention;
10 is a circuit diagram of an nth stage according to a fifth embodiment of the present invention;
11 is a circuit diagram illustrating a Q node charge and discharge unit according to a modified example.
12 is a circuit diagram illustrating a QB node charge and discharge unit according to a modified example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a display device, FIG. 2 is a configuration diagram of stages constituting a shift register, and FIG. 3 is a diagram illustrating a threshold voltage according to a mode of a TFT constituting a shift register.

As shown in FIG. 1, the display device includes a display panel 10, a timing controller 11, a data driver 12, and gate drivers 13 and 14.

The display panel 10 includes subpixels separated from and connected to the data lines DL and the gate lines GL. The display panel 10 includes a display area 10A in which subpixels are formed, and a non-display area 10B in which various signal lines or pads are formed outside the display area 10A. The display panel 10 may be implemented by any one of a liquid crystal display (LCD), an organic light emitting display (OLED), and an electrophoretic display (EPD).

The timing controller 11 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock DCLK through an LVDS or TMDS interface receiving circuit connected to an image board. Receive a timing signal. The timing controller 11 generates timing control signals for controlling the operation timing of the data driver 12 and the gate drivers 13 and 14 based on the input timing signal.

The data driver 12 includes a plurality of source drive integrated circuits (ICs). The source drive ICs receive the digital video data RGB and the source timing control signal DDC from the timing controller 11. The source drive ICs convert the digital video data RGB into a gamma compensation voltage in response to the source timing control signal DDC to generate a data voltage, and transmit the data voltage to the data lines DL of the display panel 10. Supply. The source drive ICs are connected to the data lines DL of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate drivers 13 and 14 include a level shifter 13 and a shift register 14. The gate drivers 13 and 14 are formed by a gate in panel (GIP) method or an IC method in which the level shifter 13 and the shift register 14 are divided. In the following embodiment, the GIP method in which the shift register 14 is formed in the non-display area 10B is taken as an example.

The level shifter 13 receives the clock signals CLK input from the timing controller 11 to the TTL (Transistor-Transistor-Logic) level of 0V to 3.3V, and the gate high level Vgh and the first or second gate low. After level shifting to the levels Vgl1 and Vgl2, it is supplied to the shift register 14. Here, the first gate low level Vgl1 and the second gate low level Vgl2 have a relationship of Vgl1> Vgl2.

The shift register 14 is formed of a plurality of thin film transistors (hereinafter TFTs) by the GIP method. The shift register 14 is composed of stages for shifting the gate output pulse in response to the clock signals CLK. Stages included in the shift register 14 sequentially output gate signals through the output stages.

The shift register 14 of the embodiment has the output stages Vg [n-2] to Vg [n + 2] of the respective stages ST [n-2] to ST [n + 2] as shown in FIG. ) Consists of a cascade connected to the stage located in the next stage.

On the other hand, the TFTs constituting the shift register 14 are located in the enhancement mode E and the negative direction where the threshold voltage is located in the positive (+) direction as shown in FIG. 3. There is a depletion mode (D).

Unlike the enhancement mode TFT, in the depletion mode TFT, the threshold voltage is located in the negative (-) direction. Therefore, if the voltage condition between gate sources is not satisfied (the current is not small enough at Vgs = 0V), the turn off function will not be performed properly.

Therefore, the embodiment is based on the gate drivers 13 and 14 of the GIP method (embedded type) which can avoid malfunction of the circuit and improve the operation characteristics even when using the depletion mode TFT as well as the enhancement mode TFT. A display device is provided, which will be described below.

≪ Embodiment 1 >

4 is a circuit diagram of the n-th stage according to the first embodiment of the present invention, FIG. 5 is an input / output signal waveform diagram of the n-th stage, and FIG. 6 is a simulation waveform diagram of the Q node and the output terminal.

As shown in FIG. 4, the n-th stage according to the first embodiment of the present invention includes a Q node charging and discharging unit T4, a QB node charging and discharging unit CLK [X + 2], a pull-up transistor TPU1, and a pull-down transistor. (TPD1) is included.

The Q-node charge / discharge unit T4, the pull-up transistor TPU1, and the pull-down transistor TPD1 are composed of enhancement mode or depletion mode TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. In the first embodiment, since the TFTs are n-type, the drain / source electrode is referred to as a first electrode / second electrode.

The Q node charge / discharge unit T4 has a gate electrode connected to the X-1 clock signal terminal CLK [X-1] and a first electrode connected to the output terminal Vg [n-1] of the n-1 stage. And a fourth transistor T4 having a second electrode connected to the Q node Q.

The fourth transistor T4 charges the Q node Q with the output terminal voltage of the n-th stage in response to the X-1 clock signal, and then outputs the n-th stage in response to the X-1 clock signal. The Q node Q is discharged by the voltage. The first electrode of the fourth transistor T4 constituting the Q-node charge / discharge unit T4 is connected to the output terminal Vg [n-1] of the n-th stage. Therefore, the Q node Q is charged when the output voltage of the front end becomes logic high, but the output voltage of the front end becomes logic low, thereby maintaining the discharge state. That is, the Q node charging and discharging unit T4 is turned on in response to the X-th clock signal and maintains a discharge state after charging the Q node Q according to the output terminal voltage of the n-th stage.

The QB node charge / discharge unit CLK [X + 2] charges and discharges the QB node QB node in response to the X + 2 clock signal supplied through the X + 2 clock signal terminal CLK [X + 2]. It is configured to. Therefore, the QB node charging and discharging portion is free of elements such as transistors. The QB node charge / discharge unit CLK [X + 2] is discharged when the X + 2 clock signal is logic low, but is charged when the X + 2 clock signal is logic high.

The pull-up transistor TPU1 has a gate electrode connected to the Q node Q, a first electrode connected to the X clock signal terminal CLK [X], and a second electrode connected to the output terminal Vg [n]. The pull-up transistor TPU1 outputs the X-th clock signal to the output terminal Vg [n] of the nth stage in response to the potential of the Q node Q.

In the pull-down transistor TPD1, a gate electrode is connected to the QB node QB, a first electrode is connected to the output terminal Vg [n], and a second electrode is connected to the first low potential voltage terminal VGL1. The pull-down transistor TPD1 outputs the first low potential voltage to the output terminal Vg [n] of the nth stage in response to the potential of the QB node QB.

As illustrated in FIG. 5, the Xth clock signal terminal CLK [X] of the nth stage may receive one of the first to fourth clock signals CLK1 to CLK4. In the drawing, the shift register receives four phase clock signals in which some sections overlap each other. However, the shift register of the first embodiment can also be driven by clock signals of two or more phases. In addition, the logic low voltages of the first to fourth clock signals CLK1 to CLK4 are the first low potential voltage corresponding to the first gate low level Vgl1 and the second low voltage corresponding to the second gate low level Vgl2. It can have a voltage between the low potential voltage. For example, the logic low voltages of the first to fourth clock signals CLK1 to CLK4 have the same or similar voltage as the second low potential voltage corresponding to the second gate low level Vgl2.

On the other hand, when the Q node Q is charged by the Q node charge / discharge unit T4, the QB node QB is discharged by the QB node charge / discharge unit CLK [X + 2]. As a result, since the Q node Q and the QB (QB) node are charged and discharged in reverse, the output terminal of the nth stage outputs a gate signal as follows.

First, when the Q node Q is charged, the pull-up transistor TPU1 is turned on. Therefore, the output terminal Vg [n] of the nth stage outputs the gate signal switched from the first gate low level Vgl1 to the gate high level Vgh.

As described above, after the output of the output terminal Vg [n] of the nth stage is generated during the charging period of the Q node Q, the Q node Q is discharged and the pull-up transistor TPU1 remains turned off. Done.

Next, when the QB node QB is charged, the pull-down transistor TPD1 is turned on. Therefore, the output terminal Vg [n] of the nth stage outputs the gate signal switched from the gate high level Vgh to the first gate low level Vgl1.

As described above, after the output of the output terminal Vg [n] of the nth stage is made during the charging period of the QB node QB, the QB node QB is discharged and the pull-down transistor TPD1 remains turned off. Done.

In the nth stage according to the first embodiment, X + 2 corresponding to the second gate low level Vgl2 is applied to the gate electrode of the pull-down transistor TPD1 while the potential of the Q node Q is maintained in the charged state. The clock signal is applied to the source electrode, and the first low potential voltage corresponding to the first gate low level Vgl1 is applied to the source electrode. The second gate low level Vgl2 applied to the gate electrode of the pull-down transistor TPD1 has a lower potential than the first gate low level Vgl1 applied to the source electrode. Therefore, the voltage Vgs between the gate sources of the pull-down transistor TPD1 satisfies the conditions Vgl2-Vgl1 <0V lower than 0V. Accordingly, since the voltage Vgs between the gate sources of the pull-down transistor TPD1 becomes negative and the current Ids between the drain sources becomes I2 rather than I1 as shown in FIG. 3, no current leakage occurs. As a result, the output terminal Vg [n] of the nth stage can output the gate signal while maintaining the normal gate high level (or gate low level) as shown in FIG. 5.

In addition, during the period in which the potential of the Q node Q is maintained in the discharged state, the X-1 clock signal applied to the gate electrode of the fourth transistor T4 overlaps the X clock signal and a part of the section, so that the fourth transistor ( T4) is turned on. At this time, the potential of the Q node Q is discharged through the output terminal of the n-th stage by the turned-on fourth transistor T4. Accordingly, the Q-node charge / discharge unit T4 may perform charge and discharge only with the fourth transistor T4 without a separate discharge transistor, and maintain the discharge state at the output terminal voltage of the n-th stage.

According to the first embodiment, since the voltage condition between the gate sources of the transistors constituting the shift register is satisfied with Vgs = 0V, the turn-on / off operation characteristic of the TFT can be improved by the above-described configuration and operation, thereby improving output characteristics. Will be. This is because the clock signals corresponding to the first low potential voltage and the second low potential voltage having a relationship of Vgl1> Vgl2 are used as described above. This is because the Q node charge / discharge unit T4 can maintain the discharge state of the Q node Q in conjunction with the front end.

According to the above configuration, the shift register of FIG. 4 may configure stages to have a form as shown in FIG. 2. As can be seen from the Q node voltage (Q-node) and the output voltage (Vg [n]) shown in the waveform diagram of the simulation of FIG. 6, the first embodiment shows a normal output even if the shift register is configured as a depletion mode TFT. Will be able to perform

On the other hand, the shift register according to the first embodiment may be configured as follows to improve the operation and output characteristics of the circuit.

&Lt; Embodiment 2 >

7 is a circuit diagram of the n-th stage according to the second embodiment of the present invention.

As shown in FIG. 7, the n-th stage according to the second embodiment of the present invention includes a Q node charging and discharging unit T4, a QB node charging and discharging unit CLK [X + 2], a pull-up transistor TPU1, and a pull-down transistor. (TPD1) and first transistor (T1) are included.

The Q-node charge / discharge unit T4, the pull-up transistor TPU1, the pull-down transistor TPD1, and the first transistor T1 are composed of enhancement mode or depletion mode TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. The second embodiment also assumes that the TFTs are n-type, so that the drain / source electrode is referred to as the first electrode / second electrode.

The nth stage according to the second embodiment of the present invention is the same as the first embodiment except for the configuration and the connection relationship of the first transistor T1. Therefore, only portions different from those of the first embodiment will be described in order to prevent duplication of description.

The first transistor T1 has a gate electrode connected to the QB node QB and a first electrode connected to the second electrode and the Q node Q of the fourth transistor T4 constituting the Q node charge / discharge unit T4. The second electrode is connected to the first low potential voltage terminal VGL1. The first transistor T1 discharges the Q node Q to the first low potential voltage in response to the potential of the QB node QB, that is, serves as a reset.

In the second embodiment and like the first embodiment, after the output terminal Vg [n] is output during the charging period of the Q node Q, the Q node Q is discharged and the pull-up transistor TPU1 is turned on. Will remain turned off.

After the output of the output terminal Vg [n] is output during the charging period of the QB node QB, the QB node QB is discharged and the pull-down transistor TPD1 is maintained in the turn-off state.

In particular, in the second embodiment, since the first transistor T1 is turned on during the charging period of the QB node QB, the Q node Q can maintain a stable discharge state by the first low potential voltage.

Third Embodiment

8 is a circuit diagram of the n-th stage according to the third embodiment of the present invention.

As shown in FIG. 8, the n-th stage according to the third embodiment of the present invention includes a Q node charging and discharging unit T4, a QB node charging and discharging unit T2 and T3, a pull-up transistor TPU1, and a pull-down transistor TPD1. Included.

The Q node charging and discharging portion T4, the QB node charging and discharging portions T2 and T3, the pull-up transistor TPU1 and the pull-down transistor TPD1 are composed of enhancement mode or depletion mode TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. The third embodiment also assumes that the TFTs are n-type, so the drain / source electrode is referred to as the first electrode / second electrode.

The nth stage according to the third embodiment of the present invention is the same as the first embodiment except for the configuration and connection relationship of the QB node charge / discharge units T2 and T3. Therefore, only portions different from those of the first embodiment will be described in order to prevent duplication of description.

The QB node charge / discharge units T2 and T3 are composed of a second transistor T2 and a third transistor T3. The second transistor T2 has a gate electrode connected to the X + 2 clock signal terminal CLK [X + 2], a first electrode connected to the high potential voltage terminal VDD, and a third transistor T3 of the second transistor T3. The second electrode is connected to one electrode. In the third transistor T3, a gate electrode is connected to the Q node Q, a first electrode is connected to the second electrode of the second transistor T2, and a second electrode is connected to the first low potential voltage terminal VGL1. do.

The second transistor T2 is turned on when the X + 2 clock signal becomes logic high. When the second transistor T2 is turned on, the QB node QB is charged by the high potential voltage. The third transistor T3 is turned on when the Q node Q is charged and becomes logic high. When the third transistor T3 is turned on, the QB node QB is discharged by the first low potential voltage.

When the second transistor T2 is turned on to charge the QB node QB, the third transistor T3 is turned off by the potential of the Q node Q. In contrast, when the third transistor T3 is turned on to discharge the QB node QB, the second transistor T2 is turned off by the X + 2 clock signal.

In the third embodiment and like in the first embodiment, after the output terminal Vg [n] is output during the charging period of the Q node Q, the Q node Q is discharged and the pull-up transistor TPU1 is turned on. Will remain turned off.

After the output of the output terminal Vg [n] is output during the charging period of the QB node QB, the QB node QB is discharged and the pull-down transistor TPD1 is maintained in the turn-off state.

<Fourth Embodiment>

9 is a circuit diagram of an nth stage according to a fourth embodiment of the present invention.

As shown in FIG. 9, the n-th stage according to the fourth embodiment of the present invention includes a Q node charging and discharging unit T4 and a QB node charging and discharging unit T2-1, T2-2, T3-1, and T3-2. , A pull-up transistor TPU1 and a pull-down transistor TPD1 are included.

The Q node charge / discharge unit T4, the QB node charge / discharge unit T2-1, T2-2, T3-1, T3-2, the pull-up transistor TPU1, and the pull-down transistor TPD1 may be enhanced or depletion mode. It is composed of TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. The fourth embodiment also uses TFTs as n-type (n-type) as an example, so the drain / source electrode is referred to as the first electrode / second electrode.

The nth stage according to the fourth embodiment of the present invention is the same as that of the first embodiment except for the configuration and connection relationship of the QB node charge / discharge units T2-1, T2-2, T3-1, and T3-2. Therefore, only portions different from those of the first embodiment will be described in order to prevent duplication of description.

The QB node charge / discharge units T2-1, T2-2, T3-1, and T3-2 discharge the QB node QB to the first low potential voltage in response to the potential of the Q node Q, and then the Q node ( The QB node QB is charged to the high potential voltage in response to the potential and the high potential voltage of Q). To this end, the QB node charging and discharging units T2-1, T2-2, T3-1, and T3-2 are the 2-1 transistors T2-1, the 2-2 transistors, and the 3-3 transistors. It consists of one transistor T3-1 and a third-2 transistor T3-2.

In the 2-1 transistor T2-1, the gate electrode and the first electrode are connected to the high potential voltage terminal VDD. In the second-2 transistor T2-2, a gate electrode is connected to the second electrode of the 2-1 transistor T2-1, and a first electrode is connected to the high potential voltage terminal VDD. In the 3-1 transistor T3-1, a gate electrode is connected to the Q node Q, and a first electrode is connected to the second electrode of the 2-1 transistor T2-1, and the first low potential voltage terminal ( The second electrode is connected to VGL1). A gate electrode is connected to the Q node Q and a first electrode is connected to the second electrode and the QB node QB of the second-2 transistor T2-2. The second electrode is connected to the first low potential voltage terminal VGL1.

Since the gate electrode is connected to the high potential voltage terminal VDD, the 2-1 transistor T2-1 maintains a turn-on state at all times. On the other hand, in the 2-2 transistor T2-2, the gate electrode is connected to the first electrode of the 2-1 transistor T2-1, so whether the 2-1 transistor T2-1 is turned on or off. Will be turned on. Therefore, the QB node QB is charged when the 2-1 and 2-2 transistors T2-1 and T2-2 are turned on.

Since the gate electrode is connected to the Q node Q, the 3-1 transistor T3-1 is turned on when the potential of the Q node Q is logic high, and is turned on when the potential of the Q node Q is logic low. Is off. Therefore, when the 3-1 transistor T3-1 is turned on, the 2-2 transistor T2-2 is turned off by the first low potential voltage. Since the gate electrode is connected to the Q node Q, the third node T3-2 is turned on when the potential of the Q node Q is logic high, and is turned on when the potential of the Q node Q is logic low. Is off. Accordingly, the QB node QB is discharged by the first low potential voltage when the third-2 transistor T3-2 is turned on.

Similar to the first embodiment, after the output terminal Vg [n] is output during the charging period of the Q node Q, the fourth node Q is discharged and the pull-up transistor TPU1 is applied. Will remain turned off.

After the output of the output terminal Vg [n] is output during the charging period of the QB node QB, the QB node QB is discharged and the pull-down transistor TPD1 is maintained in the turn-off state.

<Fifth Embodiment>

10 is a circuit diagram of an nth stage according to a fifth embodiment of the present invention.

As shown in FIG. 10, the n-th stage according to the fifth embodiment of the present invention includes a Q node charging and discharging unit T4 and a QB node charging and discharging unit T2-1, T2-2, T3-1, and T3-2. , A pull-up transistor TPU1 and a pull-down transistor TPD1 are included.

The Q node charge / discharge unit T4, the QB node charge / discharge unit T2-1, T2-2, T3-1, T3-2, the pull-up transistor TPU1, and the pull-down transistor TPD1 may be enhanced or depletion mode. It is composed of TFTs. The enhancement mode and depletion mode TFTs have a gate, a source and a drain electrode. The fifth embodiment also assumes that the TFTs are n-type, so that the drain / source electrode is referred to as the first electrode / second electrode.

The nth stage according to the fifth embodiment of the present invention is the same as the fourth embodiment except for the connection relationship between the QB node charge and discharge units T2-1, T2-2, T3-1, and T3-2. Therefore, only portions different from those in the fourth embodiment will be described in order to avoid duplication of description.

The QB node charging and discharging units T2-1, T2-2, T3-1, and T3-2 have a 2-1 transistor T2-1, a 2-2 transistor T2-2, and a 3-1 transistor ( T3-1) and 3-2 transistor T3-2.

In the 2-1 transistor T2-1, the gate electrode and the first electrode are connected to the high potential voltage terminal VDD. In the second-2 transistor T2-2, a gate electrode is connected to the second electrode of the 2-1 transistor T2-1, and a first electrode is connected to the high potential voltage terminal VDD. In the 3-1 transistor T3-1, a gate electrode is connected to the Q node Q, and a first electrode is connected to the second electrode of the 2-1 transistor T2-1, and the first low potential voltage terminal ( The second electrode is connected to VGL1). A gate electrode is connected to the Q node Q and a first electrode is connected to the second electrode and the QB node QB of the second-2 transistor T2-2. The second electrode is connected to the second low potential voltage terminal VGL2.

Since the gate electrode is connected to the high potential voltage terminal VDD, the 2-1 transistor T2-1 maintains a turn-on state at all times. On the other hand, since the gate electrode is connected to the first electrode of the 3-1 transistor T3-1, the 2-2 transistor T2-2 turns on or off the 3-1 transistor T3-1. Will be turned on. Therefore, the QB node QB is charged when the 2-1 and 2-2 transistors T2-1 and T2-2 are turned on.

Since the gate electrode is connected to the Q node Q, the 3-1 transistor T3-1 is turned on when the potential of the Q node Q is logic high, and is turned on when the potential of the Q node Q is logic low. Is off. Therefore, when the 3-1 transistor T3-1 is turned on, the 2-2 transistor T2-2 is turned off by the first low potential voltage. Since the gate electrode is connected to the Q node Q, the third node T3-2 is turned on when the potential of the Q node Q is logic high, and is turned on when the potential of the Q node Q is logic low. Is off. Accordingly, the QB node QB is discharged by the second low potential voltage when the third-2 transistor T3-2 is turned on.

Meanwhile, the Q node charge / discharge unit T4 of the shift registers according to the first to fifth embodiments described above may be configured as follows to increase the stability of the operation.

11 is a circuit diagram illustrating a Q node charge and discharge unit according to a modified example.

As shown in FIG. 11A, the Q node charge / discharge units T4 of the first to fifth embodiments charge and discharge the Q node Q using one transistor. On the other hand, as shown in Fig. 11 (b), the Q node charge and discharge unit (T4-1, 4-2, 4-3) according to the modified example charges and discharges the Q node (Q) using three transistors. do.

The Q-node charge / discharge units T4-1, T4-2, and T4-3 include the 4-1 transistor T4-1, the 4-2 transistor T4-2, and the 4-3 transistor T4-3. It consists of.

In the 4-1 transistor T4-1, a gate electrode is connected to the X-1 clock signal terminal CLK [X-1] and a first terminal is output to the output terminal Vg [n-1] of the n-1 stage. The electrode is connected and the second electrode is connected to the first electrode of the 4-2 transistor T4-2. A gate electrode is connected to the X-1 clock signal terminal CLK [X-1] and the first electrode is connected to the second electrode of the 4-1 transistor T4-1. The second electrode is connected to the Q node Q. In the fourth transistor T4-3, a gate electrode is connected to the X clock signal terminal CLK [X], and a first electrode is connected to the output terminal Vg [n] of the nth stage. The second electrode is connected to the first electrode of the transistor T4-2.

The 4-1 and 4-2 transistors T4-1 and T4-2 are simultaneously turned on and off in response to the X-1 clock signal. Accordingly, the 4-1 and 4-2 transistors T4-1 and T4-2 charge the Q node Q with the output terminal voltage of the n-1 stage in response to the X-1 clock signal. The Q node Q is discharged to the output terminal voltage of the n-th stage in response to the X-1 clock signal.

The fourth-3 transistor T4-3 is turned on and off in response to the X clock signal terminal CLK [X]. Accordingly, the fourth to third transistors T4-3 are turned off after maintaining the state of charge of the Q node Q at the voltage of the output terminal Vg [n] of the nth stage, and thus the fourth to fourth transistors 4-1 and 4-2. The turn-off states of the transistors T4-1 and T4-2 are maintained. That is, the 4-3 transistor T4-3 prevents the voltage of the Q node Q from being discharged through the 4-1 transistor T4-1 during the output period of the nth stage to increase the stability of the operation. Play a role.

The QB node charge / discharge units T2-1, T2-2, T3-1, and T3-2 of the shift registers according to the fourth and fifth embodiments described above may be configured by simplifying the circuit as follows.

12 is a circuit diagram illustrating a QB node charge and discharge unit according to a modified example.

As shown in FIG. 12A, the QB node charge / discharge units T2-1, T2-2, T3-1, and T3-2 of the first to fifth embodiments use the QB node QB using four transistors. Charge / discharge). On the other hand, as shown in Figure 12 (b), the QB node charge and discharge unit (T2, T3) according to the modified example charges and discharges the QB node (QB) using two transistors.

The QB node charge / discharge units T2 and T3 are composed of a second transistor T2 and a third transistor T3. In the second transistor T2, the gate electrode and the first electrode are connected to the high potential voltage terminal VDD, and the second electrode is connected to the first electrode and the QB node QB of the third transistor T3. In the third transistor T3, a gate electrode is connected to the Q node, a first electrode is connected to the second electrode and the QB node QB of the second transistor T2, and the first or second low potential voltage terminal VGL1 or The second electrode is connected to VGL2).

In the modified example, the QB node charge / discharge units T2 and T3 also charge the QB node QB to the high potential voltage terminal VDD at a frame period corresponding to the charge / discharge state of the Q node Q, or the first or second low potential. The function of discharging to the voltage terminal VGL1 or VGL2 is the same. The QB node charge / discharge units T2 and T3 of the modified example as described above have an advantage of reducing the manufacturing cost by simplifying the circuit.

Meanwhile, in the shift register circuits according to the above-described embodiments, the QB node QB consists of only one node, and the QB node QB consists of two nodes and alternately drives a frame period by adding a transistor accordingly. It may be implemented.

The shift register according to the above-described embodiments has an n-type TFT of negative threshold voltage and a p-type of positive threshold voltage as well as a TFT in enhancement mode. It can be applied to TFT. In addition, the above-described embodiments may be configured in other forms by appropriately combining circuits so as to improve and improve the output characteristics of the shift register.

As described above, the present invention is configured such that the voltage (Vgs) between the gate sources of the TFTs becomes negative even when the depletion mode TFTs as well as the enhancement mode TFTs are applied, and the output characteristics are improved by improving the turn-on / off operation characteristics of the TFTs (output There is an effect of providing a display device including a gate driver capable of solving a problem such as no occurrence.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

10: Display panel 11: Timing controller
12: data driver 13, 14: gate driver
T1: first transistor T2: second transistor
T3: 3rd transistor T4: Q node charging / discharging part or 4th transistor
TPU1: Pullup Transistor TPD2: Pulldown Transistor
T2-1, T2-2, T3-1, T3-2: QB node charging / discharging part
T4-1, T4-2, T4-3: Q node charging / discharging part

Claims (10)

Display panel; And
A shift shifter connected to the display panel and outputting clock signals overlapping some sections, and a shift register configured to shift gate output pulses in response to the clock signals;
The nth stage of the stages
A pull-up transistor for outputting an X-th clock signal to an output terminal of the n-th stage corresponding to the potential of the Q node;
A pull-down transistor for outputting a first low potential voltage to an output terminal of the nth stage in response to a potential of a QB node;
A Q node charging and discharging unit for charging and discharging the Q node to the output terminal voltage of the n-1 stage in response to the X-1 clock signal;
And a QB node charge and discharge unit configured to charge and discharge the QB node in response to an X + 2 clock signal. The method of claim 1,
The pull-up transistor has a gate electrode connected to the Q node, a first electrode connected to an X clock signal terminal, and a second electrode connected to the output terminal.
The pull-down transistor has a gate electrode connected to the QB node, a first electrode connected to the output terminal, and a second electrode connected to a first low potential voltage terminal.
The Q node charging and discharging unit has a gate electrode connected to the X-1 clock signal terminal, a first electrode connected to the output terminal of the n-1 stage, and a second electrode connected to the Q node.
And the QB node charging and discharging unit is formed of a wire connected between an X + 2 clock signal terminal and a gate electrode of the pull-down transistor. The method of claim 1,
The n-th stage
And a first transistor configured to discharge the Q node to the first low potential voltage in response to the potential of the QB node. The method of claim 1,
The QB node charge and discharge unit
A second transistor configured to charge the QB node with a high potential voltage in response to the X + 2 clock signal;
And a third transistor configured to discharge the QB node to the first low potential voltage in response to the Q node potential. The method of claim 1,
The QB node charge and discharge unit
A 2-1 transistor having a gate electrode and a first electrode connected to a high potential voltage terminal;
A 2-2 transistor having a gate electrode connected to the second electrode of the 2-1 transistor and a first electrode connected to the high potential voltage terminal;
A 3-1 transistor having a gate electrode connected to the Q node, a first electrode connected to a second electrode of the 2-1 transistor, and a second electrode connected to a first low potential voltage terminal;
And a third-2 transistor connected with a gate electrode to the Q node, a second electrode of the second-2 transistor, a first electrode connected to the QB node, and a second electrode connected to the first low potential voltage terminal. Display. The method of claim 1,
The QB node charge and discharge unit
Discharging the QB node to a second low potential voltage lower than the first low potential voltage in response to the potential of the Q node, and then turning the QB node to the high potential voltage in response to the potential and high potential voltage of the Q node. Display device characterized in that for charging. The method according to claim 6,
The QB node charge and discharge unit
A 2-1 transistor having a gate electrode and a first electrode connected to a high potential voltage terminal;
A second-2 transistor having a gate electrode connected to a second electrode of the twenty-first transistor and a first electrode connected to the high potential voltage terminal;
A 3-1 transistor having a gate electrode connected to the Q node, a first electrode connected to a second electrode of the 2-1 transistor, and a second electrode connected to a first low potential voltage terminal;
A gate electrode connected to the Q node, a second electrode of the second-2 transistor, a third electrode connected to the QB node, and a second electrode connected to a second low potential voltage terminal; Display. The method of claim 1,
The Q node charging and discharging unit
A 4-1 transistor having a gate electrode connected to the X-1 clock signal terminal and a first electrode connected to an output terminal of the n-1 stage;
A 4-2 transistor having a gate electrode connected to the X-1 clock signal terminal, a first electrode connected to a second electrode of the 4-1 transistor, and a second electrode connected to the Q node;
A display device including a 4-3 transistor having a gate electrode connected to an X-clock signal terminal, a first electrode connected to an output terminal of the nth stage, and a second electrode connected to a first electrode of the 4-2 transistor. . The method of claim 1,
The QB node charge and discharge unit
A second transistor having a gate electrode and a first electrode connected to a high potential voltage terminal, and a second electrode connected to the QB node;
And a third transistor having a gate electrode connected to the Q node, a first electrode connected to the QB node, and a second electrode connected to a first potential voltage terminal or a second potential voltage terminal. The method of claim 1,
The logic low voltage of the clock signals
And a voltage lower than the first low potential voltage.

Images