KR20070044942A - A shift register - Google Patents

Abstract

The present invention relates to a shift register capable of improving output characteristics, comprising: a shift register including a plurality of stages sequentially outputting a gate-on voltage for driving gate lines, the shift register including at least one stage positioned at a front end of the shift register; It is enabled at least twice according to the gate on voltages from the two stages.

LCD, Shift Register, Stage, Enable

Description

A shift register

1 is a block diagram of a conventional shift register

2 illustrates a shift register according to a first embodiment of the present invention.

FIG. 3 is a diagram illustrating various input signals supplied to each stage of FIG. 2 and output signals output from each stage.

4 is a diagram showing the detailed configuration of the third stage of FIG.

5 is a diagram illustrating a circuit configuration provided in the third stage.

FIG. 6 is a diagram illustrating a circuit configuration of the first to third stages of FIG. 2.

7 illustrates a shift register according to a second embodiment of the present invention.

8 is a diagram illustrating various input signals supplied to each stage of FIG. 7 and output signals output from each stage;

9 is a diagram illustrating a detailed configuration of a third stage of FIG. 7.

10 is a diagram showing a circuit configuration provided in the third stage.

FIG. 11 is a diagram illustrating a circuit configuration of the first to third stages of FIG. 7.

12 is a simulation waveform diagram for explaining a change in voltage of the first node of each stage.

* Explanation of symbols on the main parts of the drawings

CLK: Clock Pulse ST: Stage

Von: Gate on voltage Vdc: DC voltage source Vst: Start pulse GL: Gate line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly to a shift register and a driving method thereof capable of improving output characteristics.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a gate on voltage applied to the gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The gate driver sequentially supplies gate-on voltages to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a gate-on voltage is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register to sequentially output the gate on voltages as described above. This will be described in more detail with reference to the accompanying drawings.

1 is a block diagram of a conventional shift register.

The conventional shift register is composed of m stages ST101 to ST10m and one dummy stage ST10m + 1 connected to each other, as shown in FIG. 1. Here, each of the stages ST101 to ST10m + 1 outputs one gate-on voltage Von1 to Vonm + 1, and in this case, gates are sequentially formed from the first stage ST101 to the dummy stages ST101 to ST10m + 1. The on voltages Von1 to Vonm + 1 are output. Here, the gate on voltages Von1 to Vonm output from the remaining stages ST101 to ST10m except for the dummy stage ST10m + 1 are sequentially supplied to gate lines of the liquid crystal panel, thereby sequentially ordering the gate lines. Scanning is done with.

The entire stages ST101 to ST10m + 1 of the shift registers configured as described above are among the first DC voltage source and the second DC voltage source Vdc2 and the first to fourth clock pulses CLK1 to CLK4 having sequential phase differences with each other. Two clock pulses are applied. Here, the first DC voltage source Vdc1 means a positive voltage source, and the second DC voltage source Vdc2 means a negative voltage source.

Meanwhile, the first stage ST101 positioned at the uppermost side of the stages ST101 to ST10m + 1 may be started in addition to the first DC voltage source Vdc1, the second DC voltage source Vdc2, and the two clock pulses. The pulse Vst is supplied.

The operation of the conventional shift register configured as described above will be described in detail as follows.

First, when a start pulse Vst from a timing controller (not shown) is applied to the first stage ST101, the first stage ST101 is enabled in response to the start pulse Vst.

Subsequently, the enabled first stage ST101 receives the first and second clock pulses CLK1 and CLK2 from the timing controller and outputs a first gate on voltage Von1, and the first gate line and the first gate line are connected to the first gate line. It supplies to the 2nd stage ST102 together. Then, the second stage ST102 is enabled in response to the first gate on voltage Von1.

Subsequently, the enabled second stage ST102 receives the second and third clock pulses CLK2 and CLK3 from the timing controller and outputs a second gate on voltage Von2, which is then output to the second gate line. The first stage ST103 and the first stage ST101 are supplied together. Then, the third stage ST103 is enabled in response to the second gate on voltage Von2, and the first stage ST101 is disabled in response to the second gate on voltage Von2. To supply a second DC voltage source Vdc2 to the first gate line.

Subsequently, the enabled third stage ST103 receives the third and fourth clock pulses CLK3 and CLK4 from the timing controller and outputs a third gate on voltage Von3, which is then converted into a third gate line. And supply to the fourth stage ST104 and the second stage ST102 together. Then, the fourth stage ST104 is enabled in response to the third gate on voltage Von3, and the second stage ST102 is disabled in response to the third gate on voltage Von3. To supply a second DC voltage source Vdc2 to the second gate line.

In this manner, the fourth to mth gate on voltages Von4 to Vonm are sequentially output to the remaining fourth to mth stages ST104 to ST10m and sequentially applied to the fourth to mth gate lines. As a result, the first to m th gate lines are sequentially scanned by the sequentially output first to m th gate on voltages Von1 to Vonm.

In general, the first to mth stages ST101 to ST10m and the dummy stage ST10m + 1 may include a node controller for controlling charge and discharge states of the first and second nodes, and the first and second nodes. And a pull-up switching device that outputs a first gate on voltage according to a node state, and a pull-down switching device that outputs a gate off voltage according to a state of the second node.

Here, the first node and the second node are alternately charged and discharged. Specifically, when the first node is in a charged state, the second node is maintained in a discharged state, and the second node is charged. In this state, the first node maintains a discharged state.

At this time, each of the stages ST101 to ST10m + 1 charges its first node to a constant voltage and discharges the second node in response to the gate-on voltage from the immediately preceding stage (the stage located at the first front end thereof). Enabled by

Meanwhile, as the liquid crystal display device becomes larger, the number of gate lines increases, and as the number of gate lines increases, the number of stages ST101 to ST10m + 1 also increases. At this time, as the number of stages ST101 to ST10m + 1 increases, the load increases to weaken the state of charge of the first node provided in each of the stages ST101 to ST10m + 1. Therefore, the output characteristics of each stage ST101 to ST10m + 1 are inferior. Such weakening of the output characteristics of the stages ST101 to ST10m + 1 results in poor image quality of the image display apparatus.

The present invention has been made to solve the above problems, the shift register and its driving that can improve the output characteristics of the stage by enabling each stage at least twice through the gate on voltage from at least two front stages The purpose is to provide a method.

A shift register according to the present invention for achieving the above object, in the shift register including a plurality of stages for sequentially outputting a gate on voltage for driving the gate lines, each stage is at least in front of itself It is characterized in that it is enabled at least twice in accordance with the gate-on voltages from the two stages.

Hereinafter, the shift register according to the first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to a first exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating an input waveform supplied to each stage of FIG. 2 and an output waveform output from each stage.

As illustrated in FIG. 2, the shift register according to the first embodiment of the present invention includes m stages ST201 to ST20m and one dummy stage ST20m + 1 connected to each other. Here, each of the stages ST201 to ST20m + 1 outputs one gate on voltage Von1 to Vonm + 1, and in this case, the gate on voltage is sequentially supplied from the first stage ST201 to the dummy stage ST20m + 1. (Von1 to Vonm + 1) is output. Here, the gate on voltages Von1 to Vonm output from the remaining stages ST201 to ST20m except for the dummy stage ST20m + 1 are sequentially supplied to the gate lines of the liquid crystal panel, thereby sequentially ordering the gate lines. Scanning is done with.

That is, first, the first stage ST201 outputs the first gate on voltage Von1, and then the second stage ST202 outputs the second gate on voltage Von2, and then, the third stage ( ST203 outputs the third gate on voltage Von3, and finally, the m-th stage ST20m outputs the m-th gate on voltage. On the other hand, after the m-th stage ST20m outputs the m-th gate on voltage, the dummy stage ST20m + 1 outputs the n + 1 gate-on voltage, from which the dummy stage ST20m + 1 The output nth + 1 gate on voltage is not supplied to the gate line but is supplied only to the mth stage ST20m. Each of the stages ST201 to ST20m + 1 outputs a gate off voltage for the remaining periods except for the periods for outputting the gate on voltages Von1 to Vonm + 1. Each gate line maintains a discharge state by this gate off voltage.

On the other hand, the entire stages ST201 to ST20m + 1 of the shift registers configured as described above are circulated with the first DC voltage source Vdc1 and the second DC voltage source Vdc2 and have a sequential phase difference to the first to fourth clocks. Two clock pulses among the pulses CLK1 to CLK4 are applied. Here, the first DC voltage source Vdc1 means a positive DC voltage source, and the second DC voltage source Vdc2 means a negative DC voltage source. The second DC voltage source Vdc2 is a voltage source set as the gate off voltage.

Here, the first stage ST201 located on the uppermost side of the stages ST201 to ST20m + 1 may include the first DC voltage source Vdc1, the second DC voltage source Vdc2, and the first to fourth clocks. In addition to the two clock pulses among the pulses CLK1 to CLK4, the first and second start pulses Vst1 and Vst2 are supplied.

On the other hand, as described above, the first to fourth clock pulses (CLK1 to CLK4) are phase-delayed by one pulse width each other and output. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is one pulse than the second clock pulse CLK2. Phase delayed by a width is output, the fourth clock pulse (CLK4) is phase-delayed by one pulse width than the third clock pulse (CLK3) and output, and the first clock pulse (CLK1) is the fourth clock pulse Phase delayed by one pulse width from (CLK4) is output.

On the other hand, the first start pulse Vst1 is output before the second start pulse Vst2. That is, the first start pulse Vst1 is output by one clock pulse width ahead of the second start pulse Vst2. In addition, the second start pulse Vst2 is output earlier than the clock pulses CLK1 to CLK4. That is, the second start pulse Vst2 is output by one clock pulse width ahead of the first clock pulse CLK1. In addition, the start pulse is output only once per frame. That is, the first and second start pulses Vst1 and Vst2 are first outputted every frame, and then the first to fourth clock pulses CLK1 to CLK4 are sequentially output.

In this case, the first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2.

The third clock pulse CLK3 and the first start pulse Vst1 may be output in synchronization with each other, and the fourth clock pulse CLK4 and the second start pulse Vst2 may be output in synchronization with each other. . In this case, the third clock pulse CLK3 is first outputted among the clock pulses.

Each of the first to fourth clock pulses CLK1 to CLK4 is continuously output at a predetermined period. Therefore, when four clock pulses are used as described above, the first to fourth stages ST201 to ST204 output the first to fourth clock pulses CLK1 to CLK4 as gate on voltages. At this time, since the first to fourth clock pulses CLK1 to CLK4 are phase-delayed by one clock pulse as described above, each gate-on output from the first to fourth stages ST201 to ST204 is performed. The voltages Von1 to Von4 are also phase-delayed by one clock pulse width and outputted. That is, the gate on voltages Von1 to Von4 are sequentially output. The fifth stage again outputs the first clock pulse CLK1 as a gate on voltage. At this time, the first clock pulse CLK1 output by the fifth stage is a pulse delayed by one period from the first clock pulse CLK1 output from the first stage ST201.

Meanwhile, the shift register according to the present invention may use two or more clock pulses. That is, the shift register according to the present invention may use only the first and second clock pulses CLK1 and CLK2 among the first to fourth clock pulses CLK4, and the first to third clock pulses CLK1 to CLK3. ) Can also be used. In addition, the shift register according to the present invention may use five or more clock pulses sequentially output.

In the shift register according to the first embodiment of the present invention configured as described above, each stage ST201 to ST20m + 1 is enabled at least twice in accordance with the gate-on voltages from at least two stages generating an output ahead of it. . That is, each stage ST201 to ST20m + 1 is enabled primarily according to the gate-on voltage from the second front stage (the stage located second front from the current stage), and the first front stage (from the current stage) It is enabled secondly according to the gate on voltage from the stage located at the first front end.

For example, the third stage ST203 is first enabled according to the first gate on voltage Von1 from the first stage ST201, and the second gate on voltage Von2 from the second stage ST202. Is enabled secondary.

In addition, each stage ST201 to ST20m + 1 is disabled according to the gate-on voltage from the first next stage.

For example, the third stage ST203 is disabled according to the fourth gate on voltage Von4 from the fourth stage ST204.

However, since there is no stage at the front end and the front end of the first stage ST201, the first stage ST201 is first enabled according to the first start pulse Vst1 from the timing controller. Secondary enable according to the second start pulse Vst2 from the controller.

Since there is no stage at the front end of the second stage ST202, the second stage ST202 is first enabled according to the second start pulse Vst2 from the timing controller.

In addition, since there is no stage in the first next stage of the dummy stage ST20m + 1, the dummy stage ST20m + 1 is disabled according to the first start pulse Vst1 from the timing controller.

Each of the stages ST201 to ST20m + 1 is enabled according to the gate on voltage from the first front stage (after being secondarily activated) and corresponds to the gate on voltage from the first front stage. A clock pulse having a phase delayed from that of the clock pulse is output as a gate on voltage. This gate on voltage is supplied to the corresponding gate line, the first front stage, the first next stage, and the second next stage.

For example, after the third stage ST203 is enabled (after being secondarily enabled) according to the second gate on voltage Von2 from the second stage ST202, the third clock pulse CLK3 is applied. It outputs as 3rd gate-on voltage Von3. The third gate on voltage Von3 is supplied to the third gate line, the second stage ST202, the fourth stage ST204, and the fifth stage. Here, the second gate on voltage Von2 is a signal corresponding to the second clock pulse CLK2, and the third gate on voltage Von3 is a signal corresponding to the third clock pulse CLK3.

Herein, the configuration of each stage included in the shift register according to the first embodiment of the present invention will be described in more detail.

4 is a diagram illustrating a detailed configuration of the third stage of FIG. 2.

Each stage includes a node controller 401 for controlling charging and discharging of the first node Q and charging and discharging of the second node QB, and a gate-on voltage according to the state of the first node Q. And a pull-down switching device Trpd for outputting a gate-off voltage according to the state of the second node QB.

The first node Q and the second node QB are alternately charged and discharged. Specifically, when the first node Q is charged, the second node QB is discharged. When the second node QB is in a charged state, the first node Q is maintained in a discharged state. The charging and discharging states of the first node Q and the second node QB are controlled by a plurality of switching elements (not shown) provided in the node controller 401.

Here, the enabling of each of the stages ST201 to ST20m + 1 means that the first node Q of each of the stages ST201 to ST20m + 1 is charged and the second node QB is discharged. . The disabling of each of the stages ST201 to ST20m + 1 means that the first node Q of the stages ST201 to ST20m + 1 is discharged and the second node QB is charged. do.

At this time, the node controller 401 of each stage ST201 to ST20m + 1 charges the first node Q primarily according to the gate on voltage from the second front stage, and the gate on voltage from the first front stage. As a result, the stage is twice enabled by charging the first node Q secondaryly. Of course, at this time, the node controller 401 of each stage ST201 to ST20m + 1 discharges the second node QB according to the gate on voltage.

For example, as illustrated in FIG. 4, the node controller 401 of the third stage ST203 may be configured to perform the first node Q according to the first gate on voltage Von1 from the first stage ST201. Charge (primary charge) and charge the second node (Q2) again in accordance with the second gate on voltage (Von2) from the second stage (ST202) (the second charge). Enable) twice. In this case, the node controller 401 of the third stage ST203 discharges the second node QB according to the first and second gate on voltages Von1 and Von2. Accordingly, the pull-up switching device Trpu having a gate terminal connected to the first node Q maintains a turn-on state, and the pull-down switching device Trpd having a gate terminal connected to the second node QB is turned on. Keep turned off.

Subsequently, when the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching device Trpu, the turned-on pull-up switching device Trpu applies the third clock pulse CLK3 to the third gate on voltage (Trpu). Output as Von3). The third gate on voltage Von3 is supplied to the third gate line, the second stage ST202, the fourth stage ST204, and the fifth stage. Here, the third gate on voltage Von3 supplied to the second stage ST202 disables the second stage ST202 and the third gate on supplied to the fourth and fifth stages ST204. The voltage Von3 enables the fourth and fifth stages ST204.

Here, a circuit configuration of each of the stages ST201 to ST20m + 1 will be described.

5 is a diagram illustrating a circuit configuration provided in the third stage.

Each stage includes first to eighth switching elements Tr1 to Tr8, a pull-up switching element Trpu, a pull-down switching element Trpd, a first capacitor C1, and a second capacitor C2.

The first switching device Tr1 charges the first node Q of the stage to which it belongs to the first DC voltage source Vdc1 in response to the gate-on voltage from the second front stage.

For example, the first switching device Tr1 included in the third stage ST203 of FIG. 5 may respond to the third stage ST203 in response to the first gate on voltage Von1 from the first stage ST201. Is charged to the first DC voltage source Vdc1. To this end, a gate terminal of the first switching device Tr1 provided in the third stage ST203 is connected to the first stage ST201, and a drain terminal of the power supply line for transmitting the first DC voltage source Vdc1. The source terminal is connected to the first node Q of the third stage ST203.

The second switching device Tr2 charges the first node Q of the stage to which it belongs to the first DC voltage source Vdc1 in response to the gate-on voltage from the first front stage.

For example, the second switching device Tr2 included in the third stage ST203 of FIG. 5 may respond to the second gate on voltage Von2 from the second stage ST202. Is charged to the first DC voltage source Vdc1. To this end, the gate terminal of the second switching device Tr2 provided in the third stage ST203 is connected to the second stage ST202, and the drain terminal is a power line for transmitting the first DC voltage source Vdc1. The source terminal is connected to the first node Q of the third stage ST203.

The third switching device Tr3 discharges the first node Q of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the first next stage.

For example, the third switching device Tr3 included in the third stage ST203 of FIG. 5 may respond to the fourth gate on voltage Von4 from the fourth stage ST204. The first node (Q) of D is discharged to the second DC voltage source (Vdc2). To this end, a gate terminal of the third switching device Tr3 provided in the third stage ST203 is connected to the fourth stage ST204, a drain terminal is connected to the first node Q, and a source The terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

In response to the first DC voltage source Vdc1 charged in the second node QB of the stage to which the fourth switching element Tr4 belongs, the fourth switching element Tr4 connects the first node Q of the stage to the second DC voltage source ( Discharge to Vdc2).

For example, the fourth switching device Tr4 included in the third stage ST203 of FIG. 5 responds to the first DC voltage source Vdc1 charged in the second node QB of the third stage ST203. As a result, the first node Q of the third stage ST203 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the fourth switching device Tr4 provided in the third stage ST203 is connected to the second node QB of the third stage ST203, and the drain terminal thereof is the second DC voltage source. It is connected to the power line for transmitting (Vdc2), the source terminal is connected to the first node (Q) of the third stage (ST203).

The fifth switching device Tr5 receives the clock pulse corresponding to the gate-on voltage output from the first next stage to charge the second node QB to which the fifth switching element Tr5 belongs to the first DC voltage source Vdc1.

For example, the fifth switching device Tr5 of the third stage ST203 of FIG. 5 is connected to the fourth gate on voltage Von4 output from the fourth clock pulse CLK4 (the fourth stage ST204). In response to this), the second node QB of the third stage ST203 is charged with the first DC voltage source Vdc1. To this end, the gate terminal of the fifth switching device Tr5 provided in the third stage ST203 is connected to a clock transmission line for transmitting the fourth clock pulse CLK4, and the drain terminal of the fifth DC voltage source. It is connected to the power line for transmitting (Vdc1), the source terminal is connected to the second node (QB) of the third stage (ST203).

The sixth switching device Tr6 discharges the second node QB of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the second front stage.

For example, the sixth switching device Tr6 of the third stage ST203 of FIG. 5 may respond to the first gate on voltage Von1 from the first stage ST201. Discharges the second node QB to the second DC voltage source Vdc2. To this end, a gate terminal of the sixth switching device Tr6 provided in the third stage ST203 is connected to the first stage ST201, and a drain terminal of the second node ST203 of the third stage ST203 is provided. QB), and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The seventh switching element Tr7 discharges the second node QB of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the first front stage.

For example, the seventh switching device Tr7 included in the third stage ST203 of FIG. 5 may respond to the second gate on voltage Von2 from the second stage ST202. Discharges the second node QB to the second DC voltage source Vdc2. To this end, the gate terminal of the seventh switching device Tr7 provided in the third stage ST203 is connected to the second stage ST202, and the drain terminal of the second node ST203 is connected to the second node ST203 of the third stage ST203. QB), and the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The eighth switching device Tr8 connects the second node QB of the stage to which it belongs to the second DC voltage source in response to the first DC voltage source Vdc1 charged to the first node Q of the stage to which it belongs. Discharge to Vdc2).

For example, the eighth switching device Tr8 of the third stage ST203 of FIG. 5 may respond to the first DC voltage source Vdc1 charged in the first node Q of the third stage ST203. The second node QB of the third stage ST203 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the eighth switching element Tr8 of the third stage ST203 is connected to the first node Q of the third stage ST203, and the drain terminal of the third stage ST203 is provided. It is connected to the second node (QB) of, the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The pull-up switching device Trpu outputs the clock pulse as a gate on voltage in response to the first DC voltage source Vdc1 charged to the first node Q of the stage to which the pull-up switching device Trpu belongs, and outputs the gate on voltage to the corresponding gate. Feed to the line, the first shear stage, the first next stage, and the second next stage. In this case, the gate on voltage output to the first front stage serves as a signal for disabling the first front stage, and the gate on voltage output to the first next stage corresponds to the first next stage. The gate on voltage output to the second next stage stage serves as a start pulse for first enabling the second next stage stage.

For example, the pull-up switching device Trpu provided in the third stage ST203 of FIG. 5 receives the third clock pulse CLK3 in response to the first DC voltage source Vdc1 charged in the first node Q. The third gate on voltage Von3 is output, and the third gate on voltage Von3 is supplied to the third gate line, the second stage ST202, the fourth stage ST204, and the fifth stage. To this end, the gate terminal of the pull-up switching device Trpu provided in the third stage ST203 is connected to the first node Q of the third stage ST203, and the drain terminal of the second clock pulse ( It is connected to a clock transmission line for transmitting CLK2, and a source terminal is connected to the third gate line, the second stage ST202, the fourth stage ST204, and the fifth stage.

The pull-down switching device Trpd outputs the second DC voltage source Vdc2 as the gate-off voltage in response to the first DC voltage source Vdc1 charged to the second node QB of the stage to which the pull-down switching element Trpd belongs. The voltage is supplied to the corresponding gate line, the first front stage, the first next stage, and the second next stage.

For example, the pull-down switching device Trpd included in the third stage ST203 of FIG. 5 may respond to the first DC voltage source Vdc1 charged in the second node QB of the third stage ST203. The second DC voltage source Vdc2 is output as the gate off voltage, and the gate off voltage is supplied to the third gate line, the second stage ST202, the fourth stage ST204, and the fifth stage. To this end, the gate terminal of the pull-down switching device (Trpd) provided in the third stage (ST203) is connected to the second node (QB) of the third stage (ST203), the source terminal of the second DC voltage source ( Vdc2) is connected to the power supply line, and the drain terminal is connected to the third gate line, the second stage ST202, the fourth stage ST204, and the fifth stage.

The first capacitor C1 is connected between the gate terminal and the source terminal of the pull-up switching device Trpu to facilitate a bootstrapping operation of the pull-up switching device Trpu.

The second capacitor C2 is connected between the gate terminal and the drain terminal of the pull-down switching device Trpd to facilitate the bootstrapping operation of the pull-down switching device Trpd.

Each switching element provided in the first and second stages ST201 and ST202, the fourth to mth stages ST204 to ST20m, and the dummy stage ST20m + 1 also operates in the same manner as described above.

However, since the stage does not exist at the front end of the first stage ST201, the first and sixth switching elements Tr1 and Tr6 included in the first stage ST201 have a first start pulse from the timing controller. It operates by receiving (Vst1). That is, the first stage ST201 is first enabled by the first start pulse Vst1.

In addition, since the stage does not exist in the front stage of the first stage ST201, the second and seventh switching elements Tr2 and Tr7 included in the first stage ST201 start the second start from the timing controller. It operates by receiving the pulse Vst2. That is, the first stage ST201 is secondly enabled by the second start pulse Vst2.

In addition, since the stage is not present at the front end of the second stage ST202, the first and sixth switching elements Tr1 and Tr6 included in the second stage ST202 are started by the second controller from the timing controller. It operates by receiving the pulse Vst2. That is, the second stage ST202 is first enabled by the second start pulse Vst2.

In addition, since the stage does not exist in the first next stage of the dummy stage ST20m + 1, the third switching device Tr3 included in the dummy stage ST20m + 1 starts the first start from the timing controller. It operates by receiving the pulse Vst1. That is, the dummy stage ST20m + 1 is disabled by the first start pulse Vst1.

The operation of the shift register according to the first embodiment of the present invention configured as described above will be described in detail as follows.

FIG. 6 is a diagram illustrating a circuit configuration of the first to third stages of FIG. 2.

First, the operation of the first initial period T0A in the first frame is as follows.

During the first initial period T0A, as illustrated in FIG. 3, only the first start pulse Vst1 and the third clock pulse CLK3 synchronized with the first start pulse Vst1 are output from the timing controller. It remains high and the remaining clock pulses remain low.

The first start pulse Vst1 output from the timing controller is input to the first stage ST201. In detail, as illustrated in FIG. 6, the first start pulse Vst1 may include the gate terminal of the first switching element Tr1 and the sixth switching element Tr6 of the first stage ST201. It is supplied to the gate terminal.

Then, the first and sixth switching elements Tr1 and Tr6 are turned on, and at this time, the first DC voltage source Vdc1 is turned on by the first node Q through the turned-on first switching element Tr1. Is applied to. Accordingly, the first node Q is first charged, and both the pull-up switching device Trpu and the eighth switching device Tr8 having a gate terminal connected to the charged first node Q are turned on. do.

Here, the second DC voltage source Vdc2 is supplied to the second node QB through the turned-on eighth and sixth switching elements Tr8 and Tr6. Accordingly, the second node QB is discharged, and the pull-down switching device Trpd and the fourth switching device Tr4 connected to the discharged second node QB are turned off.

As such, during the first initial period T0A, as illustrated in FIG. 3, the first node Q of the first stage ST201 is first charged with the first DC voltage source Vdc1, and As the second node QB is discharged to the second DC voltage source Vdc2, the first stage ST201 is primarily enabled.

Next, the operation during the second initial period T0B will be described.

During the second initial period T0B, as shown in FIG. 3, only the second start pulse Vst2 and the fourth clock pulse CLK4 synchronized with the second start pulse Vst2 are output from the timing controller. It remains high and the remaining clock pulses are kept low.

The second start pulse Vst2 output from the timing controller is input to the first stage ST201. In detail, as illustrated in FIG. 6, the second start pulse Vst2 may include the gate terminal of the second switching element Tr2 and the seventh switching element Tr7 of the first stage ST201. It is supplied to the gate terminal.

Then, the second and seventh switching elements Tr2 and Tr7 are turned on, and at this time, the first DC voltage source Vdc1 is connected to the first node Q through the turned-on second switching element Tr2. Is applied to. Accordingly, the first node Q is charged secondly, and both the pull-up switching device Trpu and the eighth switching device Tr8 having the gate terminal connected to the charged first node Q are turned on. Maintain state.

Here, the second DC voltage source Vdc2 is supplied to the second node QB through the turned-on eighth and seventh switching elements Tr8 and Tr7. Accordingly, the second node QB is discharged, and the pull-down switching device Trpd and the fourth switching device Tr4 connected to the discharged second node QB are turned off.

In addition, the second start pulse Vst2 output in the second initial period T0B is also supplied to the second stage ST202. In detail, as illustrated in FIG. 6, the second start pulse Vst2 may include the gate terminal of the first switching device Tr1 and the sixth switching device Tr6 of the second stage ST202. It is supplied to the gate terminal.

Therefore, in the second initial period T0B, the second stage ST202 is first enabled as the first stage ST201 is first enabled in the first initial period T0A. . That is, in the second initial period T0B, the first node Q of the second stage ST202 is first charged and the second node QB is discharged.

As described above, during the second initial period T0B, as illustrated in FIG. 3, the first node Q of the first stage ST201 is secondary charged to the first DC voltage source Vdc1, and As the second node QB is discharged to the second DC voltage source Vdc2, the first stage ST201 is secondly enabled. In addition, in this period T, the second stage ST202 is first enabled.

Next, the operation during the first period T1 will be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Accordingly, the first, second, sixth, and seventh switching elements Tr1, Tr2, Tr6, of the first stage ST201 in response to the first and second start pulses Vst1 and Vst2 in the low state. Tr7 is turned off, so that the first node Q of the first stage ST201 is kept in a floating state.

Meanwhile, as the first node Q of the first stage ST201 is continuously maintained as the first DC voltage source Vdc1 applied during the first and second initial periods T0B, the first stage ST201 The pull-up switching device Trpu maintains the turn-on state. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Trpu, a first DC voltage source charged in the first node Q of the first stage ST201. Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Trpu of the first stage ST201 is stably output through the source terminal of the pull-up switching device Trpu. In this case, the output first clock pulse CLK1 is applied to a first gate line to function as a first gate on voltage Von1 driving the first gate line.

In addition, the first gate on voltage Von1 output from the first stage ST201 in the first period T1 is also input to the second stage ST202. In detail, as illustrated in FIG. 6, the first gate on voltage Von1 may include a gate terminal of the second switching device Tr2 provided in the second stage ST202, and a seventh switching device Tr7. Is input to the gate terminal of.

Therefore, in the first period T1, the second stage ST202 is secondly enabled, as if the first stage ST201 is secondly enabled in the second initial period T0B. That is, in the first period T1, the first node Q of the second stage ST202 is charged secondary and the second node QB is discharged.

In addition, the first gate on voltage Von1 output from the first stage ST201 in the first period T1 is also supplied to the third stage ST203. In detail, as illustrated in FIG. 6, the first gate on voltage Von1 may include a gate terminal of the first switching device Tr1 provided in the third stage ST203, and a sixth switching device Tr6. Is input to the gate terminal of.

Therefore, the third stage ST203 is first enabled in the first period T1 as if the first stage ST201 is first enabled in the first initial period T0A. That is, in the first period T1, the first node Q of the third stage ST203 is first charged and the second node QB is discharged.

As described above, during the first period T1, as illustrated in FIG. 3, the first stage ST201 outputs the first gate on voltage Von1. The second stage ST202 is secondary enabled and the third stage ST203 is primary enabled according to the first gate on voltage Von1.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

During the second period T2, the second enabled stage ST202 receives the second clock pulse CLK2 and outputs the second clock pulse CLK2 as a second gate on voltage Von2. The second gate on voltage Von2 is supplied to the second gate line, the first stage ST201, the third stage ST203, and the fourth stage ST204.

Accordingly, the third stage ST203 is secondly enabled and the fourth stage ST204 is firstly enabled during the second period T2.

Meanwhile, the second gate on voltage Von2 output from the second stage ST202 and the second clock pulse CLK2 output from the timing controller during the second period T2 are the first stage ST201. It is supplied to the to disable the second stage (ST202). If this is explained in more detail as follows.

In the second period T2, the second gate on voltage Von2 output from the second stage ST202 is supplied to the third switching device Tr3 of the first stage ST201. Specifically, the second gate on voltage Von2 is supplied to the gate terminal of the third switching element Tr3. Then, the third switching device Tr3 is turned on, and the second DC voltage source Vdc2 is turned on through the turned-on third switching device Tr3 to the first node Q of the first stage ST201. Is supplied. Accordingly, the first node Q is discharged, and both the pull-up switching device Trpu and the eighth switching device Tr8 having the gate terminal connected to the discharged first node Q are turned off.

In addition, the second clock pulse CLK2 output from the timing controller in the second period T2 is supplied to the fifth switching device Tr5 of the first stage ST201. That is, the second clock pulse CLK2 is supplied to the gate terminal of the fifth switching device Tr5. Then, the fifth switching device Tr5 is turned on, and the first DC voltage source Vdc1 is connected to the second node QB of the first stage ST201 through the turned-on fifth switching device Tr5. Is supplied. Accordingly, the second node QB is charged, and both the pull-down switching device Trpd and the fourth switching device Tr4 having the gate terminal connected to the charged second node QB are turned on.

Accordingly, in the second period T2, the first node Q of the first stage ST201 is discharged, and the second node QB is charged. That is, in the second period T2, the first stage ST201 is disabled.

At this time, the second DC voltage source Vdc2 is supplied as a gate-off voltage to the first gate line through the turned-on pull-down switching device Trpd. On the other hand, the turned-on fourth switching device Tr4 discharges the first node Q by supplying the second DC voltage source Vdc2 to the first node Q of the first stage ST201. Accelerate the speed.

Subsequently, in the third period T3, the third stage ST203 outputs the third gate on voltage Von3, and converts the third gate on voltage Von3 to the third gate line, the second stage ST202, It supplies to a 4th stage ST204 and a 5th stage. Therefore, in the third period T3, the second stage ST202 is disabled, the fourth stage ST204 is secondary enabled, and the fifth stage is primary enabled.

In the same manner, the remaining fourth to mth stages ST204 to ST20m operate.

Meanwhile, the first stage ST201 may operate by receiving one start pulse. That is, the first stage ST201 may operate by receiving the second start pulse Vst2. In this case, the first stage ST201 is enabled only once by receiving the second start pulse Vst2.

In this case, the first and sixth switching elements Tr1 and Tr6 included in the first stage ST201 are removed.

Hereinafter, the shift register according to the second embodiment of the present invention will be described in detail.

7 is a diagram illustrating a shift register according to a second exemplary embodiment of the present invention, and FIG. 8 is a diagram illustrating waveforms of first and second AC voltage sources supplied to each stage of FIG. 7.

The shift register according to the second embodiment of the present invention is the same as the shift register according to the first embodiment of the present invention. However, as shown in FIG. 7, each stage ST701 to ST70m + 1 of the shift register according to the second embodiment has first, second, and third nodes Q, QB1, and QB2. The first and second AC voltage sources Vac1 and Vac2 are further supplied.

As shown in Fig. 8, the first and second AC voltage sources Vac1 and Vac2 alternate between a high voltage source and a low voltage source at regular intervals. In this case, the first AC voltage source Vac1 has a phase inverted by 180 degrees with respect to the second AC voltage source Vac2. Therefore, in the same period, the first AC voltage source Vac1 and the second AC voltage source Vac2 have voltage values of different polarities.

That is, the high voltage source may have the same voltage as the first DC voltage source Vdc1 as a positive voltage source, and the low voltage source may have the same voltage as the second DC voltage source Vdc2 as the negative voltage source. .

The first and second alternating current voltage sources Vac1 and Vac2 are preferably changed in a fixed period, that is, in units of frames. For example, the first AC voltage source Vac1 may have a low voltage in the odd frame and the second AC voltage source Vac2 may have a high voltage in the odd frame, and the first AC voltage source Vac1 in the even frame. ) May have a high voltage and the second AC voltage source Vac2 may have a low voltage.

In addition, the first AC voltage source Vac1 may have a low voltage and the second AC voltage source Vac2 may have a high voltage for several consecutive frames, and conversely, the first AC voltage source may have a high voltage for several consecutive frames. Vac1 may have a high voltage and the second AC voltage source Vac2 may have a low voltage.

Herein, the configuration of each stage included in the shift register according to the first embodiment of the present invention will be described in more detail.

9 is a diagram illustrating a detailed configuration of the third stage of FIG. 7.

Each stage ST701 to ST70m + 1 controls the charge / discharge state of the first node Q, the charge / discharge state of the second node QB1, and the charge / discharge state of the third node QB2. The node controller 901, a pull-up switching device Trpu for outputting a gate-on voltage according to the state of the first node Q, and a gate-off voltage for outputting the gate-off voltage according to the state of the second node QB1. The first pull-down switching device Trpd1 and the second pull-down switching device Trpd2 outputting a gate-off voltage according to the state of the third node QB2.

Here, the first, second and third nodes Q, QB1 and QB2 are selectively charged and discharged. Specifically, when the first node Q is in a charged state, the second node QB1 and All of the third node QB2 maintains a discharge state, and when the first node Q is in a discharge state, either one of the second node QB1 and the third node QB2 maintains a charge state. The charging and discharging states of the first node Q and the second node QB1 are controlled by a plurality of switching elements (not shown) provided in the node controller 901.

Here, the fact that each of the stages ST701 to ST70m + 1 is enabled means that the first node Q of each of the stages ST701 to ST70m + 1 is charged and the second and third nodes QB1 and QB2 are charged. It means to be discharged. In addition, the stages ST701 to ST70m + 1 being disabled means that the first node Q of each of the stages ST701 to ST70m + 1 is discharged, and among the second and third nodes QB1 and QB2. It means that either node is charged.

The node controller 901 of each stage ST701 to ST70m + 1 charges the first node Q first according to the gate on voltage from the second front stage, and according to the gate on voltage from the first front stage. The stage is enabled twice by charging the first node Q secondary. Of course, at this time, the node controller 901 of each stage ST701 to ST70m + 1 discharges the second and third nodes QB1 and QB2 according to the gate on voltage.

For example, as shown in FIG. 9, the node controller 901 of the third stage ST703 is configured to perform the first node Q according to the first gate-on voltage Von1 from the first stage ST701. Charge (primary charge) and charge the second node (Q2) again in accordance with the second gate on voltage (Von2) from the second stage (ST702) (secondary charge). Enable) twice.

In this case, the node controller 901 of the third stage ST703 discharges the second and third nodes QB1 and QB2 according to the first and second gate on voltages Von2. Accordingly, the pull-up switching device Trpu having a gate terminal connected to the first node Q maintains a turn-on state, and the first pull-down switching device Trpd1 having a gate terminal connected to the second node QB1. ) And the second pull-down switching device Trpd2 having the gate terminal connected to the third node QB2 maintain the turn-off state.

Subsequently, when the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching device Trpu, the turned-on pull-up switching device Trpu applies the third clock pulse CLK3 to the third gate on voltage (Trpu). Output as Von3). The third gate on voltage Von3 is supplied to the third gate line, the second stage ST702, the fourth stage ST704, and the fifth stage. The third gate on voltage Von3 supplied to the second stage ST702 disables the second stage ST702 and the third gate on voltage V3 supplied to the fourth and fifth stages ST704. Von3) enables the fourth and fifth stages ST704.

Here, a circuit configuration of each of the stages ST701 to ST70m + 1 will be described.

10 is a diagram illustrating a circuit configuration provided in the third stage.

Each stage ST701 to ST70m + 1 includes first to seventeenth switching elements Tr1 to Tr17, a pullup switching element Trpu, a first pulldown switching element Trpd1, a second pulldown switching element Trpd2, and a first Capacitor C1, second capacitor C2, and third capacitor C3 are included.

The first switching device Tr1 charges the first node Q of the stage to which the stage belongs to the gate on voltage in response to the gate on voltage from the second front stage.

For example, the first switching device Tr1 included in the third stage ST703 of FIG. 10 may respond to the third stage ST703 in response to the first gate on voltage Von1 from the first stage ST701. Is charged to the first gate on voltage Von1. To this end, the gate terminal and the drain terminal of the first switching device Tr1 provided in the third stage ST703 are connected to the first stage ST701, and the source terminal of the third stage ST703 is provided. It is connected to one node Q.

Meanwhile, the first switching device Tr1 may charge the first node Q using a separate first DC voltage source Vdc1. In this case, the first switching device Tr1 charges the first node Q of the stage to which the stage belongs to the first DC voltage source Vdc1 in response to the gate-on voltage from the second front stage.

For example, the first switching device Tr1 included in the third stage ST703 may be formed in response to the first gate on voltage Von1 from the first stage ST701. One node Q is charged with the first DC voltage source Vdc1. To this end, a gate terminal of the first switching device Tr1 provided in the third stage ST703 is connected to the first stage ST701, and a drain terminal is a power source for transmitting the first DC voltage source Vdc1. The source terminal is connected to the line, and the source terminal is connected to the first node Q of the third stage ST703.

The second switching device Tr2 charges the first node Q of the stage to which it belongs to the gate on voltage in response to the gate on voltage from the first front end stage.

For example, the second switching device Tr2 included in the third stage ST703 of FIG. 10 may respond to the third stage ST703 in response to the second gate on voltage Von2 from the second stage ST702. Is charged to the second gate on voltage Von2. To this end, the gate terminal and the drain terminal of the first switching device Tr1 provided in the third stage ST703 are connected to the second stage ST702, and the source terminal of the first stage ST703 is connected to the first stage of the third stage ST703. It is connected to node Q.

The third switching device Tr3 discharges the first node Q of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the first next stage.

For example, the third switching device Tr3 included in the third stage ST703 of FIG. 5 may respond to the fourth gate on voltage Von4 from the fourth stage ST704. The first node (Q) of D is discharged to the second DC voltage source (Vdc2). For this purpose, the gate terminal of the third switching device Tr3 provided in the third stage ST703 is connected to the fourth stage ST704, the drain terminal is connected to the first node Q, and the source The terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

In response to the first AC voltage source Vac1 charged in the second node QB1 of the stage to which the fourth switching element Tr4 belongs, the fourth switching element Tr4 connects the first node Q of the stage to which the fourth switching element Tr4 belongs to the second DC voltage source. Discharge to Vdc2).

For example, the fourth switching device Tr4 included in the third stage ST703 of FIG. 10 responds to the first AC voltage source Vac1 charged in the second node QB1 of the third stage ST703. As a result, the first node Q of the third stage ST703 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the fourth switching device Tr4 provided in the third stage ST703 is connected to the second node QB1 of the third stage ST703, and the drain terminal thereof is the second DC voltage source. It is connected to the power supply line transmitting Vdc2, and the source terminal is connected to the first node Q of the third stage ST703.

The fifth switching device Tr5 supplies the first node Q of the stage to which it belongs to the second DC voltage source in response to the second AC voltage source Vac2 charged to the third node QB2 of the stage to which it belongs. Discharge to Vdc2).

For example, the fifth switching device Tr5 provided in the third stage ST703 of FIG. 10 responds to the second AC voltage source Vac2 charged in the third node QB2 of the third stage ST703. As a result, the first node Q of the third stage ST703 is discharged to the second DC voltage source Vdc2. To this end, a gate terminal of the fifth switching device Tr5 provided in the third stage ST703 is connected to a third node QB2 of the third stage ST703, and a drain terminal of the second DC voltage source It is connected to the power supply line transmitting Vdc2, and the source terminal is connected to the first node Q of the third stage ST703.

The sixth switching element Tr6 responds to a gate on voltage (gate on voltage from the second front stage or gate on voltage from the first front stage) charged to the first node Q of the stage to which it belongs. The first common node N1 of the stage to which it belongs is discharged to the second DC voltage source Vdc2.

For example, the sixth switching device Tr6 included in the third stage ST703 of FIG. 10 may include the first gate on voltage Von1 charged in the first node Q of the third stage ST703 or The first common node N1 is discharged to the second DC voltage source Vdc2 in response to the second gate on voltage Von2. To this end, the gate terminal of the sixth switching element Tr6 provided in the third stage ST703 is connected to the first node Q of the third stage ST703, and the drain terminal of the third stage ST703 It is connected to the first common node N1 of ST703, and the source terminal is connected to a power supply line for transmitting the second DC voltage source Vdc2.

The seventh switching element Tr7 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the seventh switching element Tr7 turns the first AC voltage source Vac1 into the first common node of the stage to which it belongs. Supply to N1).

For example, the seventh switching element Tr7 included in the third stage ST703 of FIG. 10 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the first switching element Tr7 is turned on. The AC voltage source Vac1 is supplied to the first common node N1 of the third stage ST703. To this end, the gate terminal and the drain terminal of the seventh switching element Tr7 provided in the third stage ST703 are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal of the third stage ST703 is connected to the third terminal ST703. It is connected to the first common node N1 of the stage ST703.

The eighth switching device Tr8 is turned on or off in response to the second DC voltage source Vdc2 and the first AC voltage source Vac1 supplied to the first common node N1 of the stage to which the eighth switching device Tr8 belongs. At turn-on, the second node QB1 of the stage to which it belongs is charged or discharged to the first AC voltage source Vac1.

For example, the eighth switching device Tr8 of the third stage ST703 of FIG. 10 is the second DC voltage source Vdc2 supplied to the first common node N1 of the third stage ST703. And a turn-on or turn-off in response to a first AC voltage source Vac1, and charge or discharge the second node QB1 of the third stage ST703 to the first AC voltage source Vac1 when turned on. Let's do it. To this end, the gate terminal of the eighth switching device Tr8 of the third stage ST703 is connected to the first common node N1 of the third stage ST703, and the drain terminal of the eighth switching device Tr8 is connected to the first AC. It is connected to the power supply line for transmitting the voltage source Vac1, and the source terminal is connected to the second node QB1 of the third stage ST703.

The ninth switching element Tr9 discharges the second node QB1 of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the second front stage.

For example, the ninth switching device Tr9 included in the third stage ST703 of FIG. 10 may respond to the third gate ST703 in response to the first gate on voltage Von1 from the first stage ST701. Discharges the second node QB1 to the second DC voltage source Vdc2. To this end, the gate terminal of the ninth switching element Tr9 provided in the third stage ST703 is connected to the first stage ST701, and the drain terminal thereof is the second node QB1 of the third stage ST703. Is connected to the power supply line for transmitting the second DC voltage source Vdc2.

The tenth switching device Tr10 transfers the second node QB1 of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage charged in the first node Q of the stage to which it belongs. Discharge.

For example, the tenth switching element Tr10 included in the third stage ST703 of FIG. 10 may have the first gate on voltage Von1 or the second gate on voltage Von2 charged in the first node Q. In response, the second node QB1 of the third stage ST703 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the tenth switching element Tr10 of the third stage ST703 is connected to the first node Q of the third stage ST703, and the drain terminal of the third stage ST703 is It is connected to the second node QB1 of ST703, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The eleventh switching element Tr11 discharges the second node QB1 of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the first front stage.

For example, the eleventh switching element Tr11 included in the third stage ST703 of FIG. 10 may respond to the second gate on voltage Von2 from the second stage ST702. Discharges the second node QB1 to the second DC voltage source Vdc2. To this end, the gate terminal of the eleventh switching element Tr11 provided in the third stage ST703 is connected to the second stage ST702, and the drain terminal thereof is the second node QB1 of the third stage ST703. Is connected to the power supply line for transmitting the second DC voltage source Vdc2.

The twelfth switching element Tr12 responds to the gate on voltage (gate on voltage from the second front stage or gate on voltage from the first front stage) charged to the first node Q of the stage to which it belongs. The second common node N2 of the stage to which it belongs is discharged to the second DC voltage source Vdc2.

For example, the twelfth switching element Tr12 included in the third stage ST703 of FIG. 10 may include the first gate on voltage Von1 charged in the first node Q of the third stage ST703, or The second common node N2 is discharged to the second DC voltage source Vdc2 in response to the second gate on voltage Von2. To this end, the gate terminal of the twelfth switching element Tr12 provided in the third stage ST703 is connected to the first node Q of the third stage ST703, and the drain terminal of the third stage ST703 It is connected to the second common node N2 of ST703, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The thirteenth switching device Tr13 is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the second common node of the stage to which the second AC voltage source Vac2 belongs Supply to N2).

For example, the thirteenth switching device Tr13 included in the third stage ST703 of FIG. 10 is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the second switching device Tr13 is turned on. The AC voltage source Vac2 is supplied to the second common node N2 of the third stage ST703. To this end, the gate terminal and the drain terminal of the thirteenth switching element Tr13 provided in the third stage ST703 are connected to a power line for transmitting the second AC voltage source Vac2, and the source terminal of the third stage ST703 is connected to the third terminal ST703. It is connected to the second common node N2 of the stage ST703.

The fourteenth switching element Tr14 is turned on or turned off in response to the second DC voltage source Vdc2 and the second AC voltage source Vac2 supplied to the second common node N2 of the stage to which the fourteenth switching element Tr14 belongs. At turn-on, the third node QB2 of the stage to which it belongs is charged or discharged to the second AC voltage source Vac2.

For example, the 14th switching element Tr14 included in the third stage ST703 of FIG. 10 may include the second DC voltage source Vdc2 supplied to the second common node N2 of the third stage ST703. And a turn-on or turn-off in response to a second AC voltage source Vac2, and charge or discharge the third node QB2 of the third stage ST703 to the second AC voltage source Vac2 when turned on. Let's do it. To this end, the gate terminal of the fourteenth switching element Tr14 provided in the third stage ST703 is connected to the second common node N2 of the third stage ST703, and the drain terminal of the second AC It is connected to a power supply line for transmitting the voltage source Vac2, and the source terminal is connected to the third node QB2 of the third stage ST703.

The fifteenth switching element Tr15 discharges the third node QB2 of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the second front stage.

For example, the fifteenth switching element Tr15 included in the third stage ST703 of FIG. 10 may respond to the first gate on voltage Von1 from the first stage ST701. Discharges the third node QB2 to the second DC voltage source Vdc2. To this end, the gate terminal of the fifteenth switching element Tr15 provided in the third stage ST703 is connected to the first stage ST701, and the drain terminal thereof is the third node QB2 of the third stage ST703. Source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The sixteenth switching device Tr16 discharges the third node QB2 of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the first front stage.

For example, the sixteenth switching device Tr16 included in the third stage ST703 of FIG. 10 may respond to the second gate on voltage Von2 from the second stage ST702. Discharges the third node QB2 to the second DC voltage source Vdc2. To this end, the gate terminal of the sixteenth switching element Tr16 provided in the third stage ST703 is connected to the second stage ST702, and the drain terminal thereof is the third node QB2 of the third stage ST703. Is connected to the power supply line for transmitting the second DC voltage source Vdc2.

The seventeenth switching device Tr17 discharges the third node QB2 of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage charged in the first node Q of the stage to which it belongs. Let's do it.

For example, the seventeenth switching element Tr17 included in the third stage ST703 of FIG. 10 may have the first gate on voltage Von1 or the second gate on voltage Von2 charged in the first node Q. In response, the third node QB2 of the third stage ST703 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the seventeenth switching element Tr17 of the third stage ST703 is connected to the first node Q of the third stage ST703, and the drain terminal of the third stage ST703 is connected to the first node Q of the third stage ST703. It is connected to the third node QB2 of ST703, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The pull-up switching device Trpu outputs the clock pulse as a gate on voltage in response to the first DC voltage source Vdc1 charged to the first node Q of the stage to which the pull-up switching device Trpu belongs, and outputs the gate on voltage to the corresponding gate. Feed to the line, the first shear stage, the first next stage, and the second next stage. In this case, the gate on voltage output to the first front stage serves as a signal for disabling the first front stage, and the gate on voltage output to the first next stage corresponds to the first next stage. It functions as a start pulse for enabling the difference, and the gate on voltage output to the second next stage stage serves as a start pulse for first enabling the second next stage.

For example, the pull-up switching device Trpu provided in the third stage ST703 of FIG. 10 receives the third clock pulse CLK3 in response to the first DC voltage source Vdc1 charged in the first node Q. The third gate on voltage Von3 is output as the third gate on voltage Von3, and the third gate on voltage Von3 is supplied to the third gate line, the second stage ST702, the fourth stage ST704, and the fifth stage. To this end, the gate terminal of the pull-up switching device Trpu provided in the third stage ST703 is connected to the first node Q of the third stage ST703, and the drain terminal of the second clock pulse The source terminal is connected to the third gate line, the second stage ST702, the fourth stage ST704, and the fifth stage.

The first pull-down switching device Trpd1 outputs the second DC voltage source Vdc2 as a gate-off voltage in response to the first DC voltage source Vdc1 charged in the second node QB1 of the stage to which it belongs. The gate off voltage is supplied to the corresponding gate line, the first front stage, the first next stage, and the second next stage.

For example, the first pull-down switching device Trpd1 included in the third stage ST703 of FIG. 10 responds to the first DC voltage source Vdc1 charged in the second node QB1 of the third stage ST703. The second DC voltage source Vdc2 is output as a gate-off voltage, and the gate-off voltage is supplied to the third gate line, the second stage ST702, the fourth stage ST704, and the fifth stage. To this end, the gate terminal of the pull-down switching device provided in the third stage ST703 is connected to the second node QB1 of the third stage ST703, and the source terminal of the pull-down switching element is connected to the second DC voltage source Vdc2. The drain terminal is connected to the third gate line, the second stage ST702, the fourth stage ST704, and the fifth stage.

The second pull-down switching device Trpd2 outputs the second DC voltage source Vdc2 as a gate-off voltage in response to the first DC voltage source Vdc1 charged in the third node QB2 of the stage to which the second pull-down switching device Trpd2 belongs. The gate off voltage is supplied to the corresponding gate line, the first front stage, the first next stage, and the second next stage.

For example, the second pull-down switching device Trpd2 included in the third stage ST703 of FIG. 10 responds to the first DC voltage source Vdc1 charged in the third node QB2 of the third stage ST703. The second DC voltage source Vdc2 is output as the gate off voltage, and the gate off voltage is supplied to the third gate line, the second stage ST702, the fourth stage ST704, and the fifth stage. To this end, the gate terminal of the second pull-down switching device Trpd2 provided in the third stage ST703 is connected to the third node QB2 of the third stage ST703, and the source terminal of the second direct current The drain terminal is connected to the power source line for transmitting the voltage source Vdc2, and the drain terminal is connected to the third gate line, the second stage ST702, the fourth stage ST704, and the fifth stage.

The first capacitor C1 is connected between the gate terminal and the source terminal of the pull-up switching device Trpu to facilitate a bootstrapping operation of the pull-up switching device Trpu.

The second capacitor C2 is connected between the gate terminal and the drain terminal of the first pull-down switching device Trpd1 to facilitate the bootstrapping operation of the first pull-down switching device Trpd1.

The third capacitor C3 is connected between the gate terminal and the drain terminal of the second pull-down switching device Trpd2 to facilitate the bootstrapping operation of the second pull-down switching device Trpd2.

Each switching element provided in the first and second stages ST701 and ST702, the fourth to mth stages ST704 to ST70m, and the dummy stage ST70m + 1 also operates in the same manner as described above.

However, since the stage does not exist in the second front end of the first stage ST701, the first, ninth, and fifteen switching elements Tr1, Tr9, and Tr15 included in the first stage ST701 may be timingd. The controller operates by receiving the first start pulse Vst1 from the controller. That is, the first stage ST701 is first enabled by the first start pulse Vst1.

In addition, since the stage is not present at the first front end of the first stage ST701, the second, eleventh, and sixteenth switching elements Tr2, Tr11, and Tr16 included in the first stage ST701 may be provided. The second start pulse Vst2 is supplied from the timing controller to operate. That is, the first stage ST701 is secondary enabled by the second start pulse Vst2.

In addition, since the stage does not exist at the second front end of the second stage ST702, the first, ninth, and fifteenth switching elements Tr15 included in the second stage ST702 are separated from the timing controller. It operates by receiving the second start pulse Vst2. That is, the second stage ST702 is first enabled by the second start pulse Vst2.

In addition, since there is no stage in the first next stage of the dummy stage ST70m + 1, the third switching device Tr3 included in the dummy stage ST70m + 1 starts the first start from the timing controller. It operates by receiving the pulse Vst1. That is, the dummy stage ST70m + 1 is disabled by the first start pulse Vst1.

The operation of the shift register according to the second embodiment of the present invention configured as described above will be described in detail as follows.

FIG. 11 is a diagram illustrating a circuit configuration of the first to third stages of FIG. 7.

First, the operation of the first initial period T0A in the first frame is as follows.

Here, assume that the first AC voltage source Vac1 is maintained as a high voltage source and the second AC voltage source Vac2 is maintained as a low voltage source during the first frame.

During the first initial period T0A, as shown in FIG. 8, the first start pulse Vst1 and the third clock pulse CLK3 synchronized with the first start pulse Vst1 are output from the timing controller. It stays high and the remaining clock pulses remain low.

The first start pulse Vst1 output from the timing controller is input to the first stage ST701. In detail, as illustrated in FIG. 11, the first start pulse Vst1 may include a gate terminal, a drain terminal, and a ninth switching device Tr9 of the first switching device Tr1 provided in the first stage ST701. ) And a gate terminal of the fifteenth switching element Tr15.

Then, the first, ninth, and fifteenth switching elements Tr1, Tr9, and Tr15 are turned on, and the first start pulse Vst1 is turned on through the turned-on first switching element Tr1. Is applied to the first node (Q). Accordingly, the first node Q is charged and the pull-up switching device Trpu, the sixth switching device Tr6, and the tenth switching device Tr10 having a gate terminal connected to the charged first node Q. ), The twelfth switching element Tr12, and the seventeenth switching element Tr17 are all turned on.

Meanwhile, as described above, since the first AC voltage source Vac1 is maintained as a high voltage source during the first frame, the seventh switching element Tr7 supplied with the first AC voltage source Vac1 is turned during the first frame. Keep it on. Therefore, the first common node N1, which receives the first AC voltage source Vac1 through the turned-on seventh switching element Tr7, is also supplied with the first AC voltage source Vac1 during the first frame.

In this case, the first common node N1 receives not only the first AC voltage source Vac1 but also a second DC voltage source Vdc2 applied through the turned-on sixth switching element Tr6. As a result, the first common node N1 is simultaneously supplied with the first AC voltage source Vac1 and the second DC voltage source Vdc2 in the first initial period T0A. However, the area (channel width) of the sixth switching device Tr6 for switching the second DC voltage source Vdc2 is the area (channel width) of the seventh switching device Tr7 for switching the first AC voltage source Vac1. The first common node N1 is maintained as the second DC voltage source Vdc2 switched from the sixth switching element Tr6. Accordingly, the first common node N1 is discharged in the first initial period T0A, and the eighth switching device Tr8 having the gate terminal connected to the first common node N1 is turned off.

In contrast, since the second AC voltage source Vac2 is maintained as a low voltage source during the first frame, the thirteenth switching device Tr13 supplied with the second AC voltage source Vac2 is turned off during the first frame. Keep it. Therefore, the second common node N2 is maintained as the second DC voltage source Vdc2 switched from the twelfth switching element Tr12. Accordingly, the second common node N2 is discharged in the first initial period T0A, and the fourteenth switching element Tr14 having a gate terminal connected to the second common node N2 is turned off. .

As such, the eighth and fourteenth switching elements Tr14 are turned off and the ninth, fifteenth, and seventeenth switching elements Tr9, Tr15, and Tr17 are turned off in the first initial period T0A. Since it is turned on, the second and third nodes QB1 and QB2 of the first stage ST701 are discharged.

That is, the second DC voltage source Vdc2 is supplied to the second node QB1 through the turned-on ninth and tenth switching elements Tr9 and Tr10, thereby discharging the second node QB1. The third node QB2 is discharged by supplying a second DC voltage source Vdc2 to the third node QB2 through the turned-on fifteenth and seventeenth switching elements Tr15 and Tr17.

Accordingly, the first pull-down switching device Trpd1 and the fourth switching device Tr4 having the gate terminal connected to the second node QB1 are turned off. In addition, the second pull-down switching device Trpd2 and the fifth switching device Tr5 having the gate terminal connected to the third node QB2 are turned off.

In summary, in the first initial period T0A, the first node Q of the first stage ST701 is charged, and the second and third nodes QB1 and QB2 are discharged, whereby the first stage ( ST701) is primary enabled.

Next, the operation during the second initial period T0B will be described.

During the second initial period T0B, as shown in FIG. 8, only the second start pulse Vst2 and the fourth clock pulse CLK4 synchronized with the second start pulse Vst2 are output from the timing controller. It remains high and the remaining clock pulses remain low.

The second start pulse Vst2 output from the timing controller is input to the first stage ST701. In detail, as illustrated in FIG. 11, the second start pulse Vst2 includes the gate terminal and the drain terminal of the second switching device Tr2 provided in the first stage ST701, and the eleventh switching device Tr11. ) And a gate terminal of the sixteenth switching element Tr16.

Then, the second, eleventh, and sixteenth switching elements Tr2, Tr11, and Tr16 are turned on, and the second start pulse Vst2 is turned on through the turned-on second switching element Tr2. Is applied to the first node (Q). Accordingly, the first node Q is charged and the pull-up switching device Trpu, the sixth switching device Tr6, and the tenth switching device Tr10 having a gate terminal connected to the charged first node Q. ), The twelfth switching element Tr12, and the seventeenth switching element Tr17 are all turned on.

In addition, the second DC voltage source Vdc2 is supplied to the second node QB1 through the turned-on eleventh switching element Tr11. Accordingly, the second node QB1 is discharged, and the first pull-down switching device Trpd1 and the fourth switching device Tr4 having the gate terminal connected to the second node QB1 maintain a turn-off state. . In addition, the second DC voltage source Vdc2 is supplied to the third node QB2 through the turned-on sixteenth switching element Tr16. Accordingly, the third node QB2 is discharged, and the second pull-down switching device Trpd2 and the fourth switching device Tr4 having the gate terminal connected to the third node QB2 maintain the turn-off state. .

As described above, as the first node Q is charged second by the second start pulse Vst2, the second and third nodes QB1 and QB2 of the first stage ST701 are discharged. That is, in the second initial period T0B, the first stage ST701 is secondary enabled.

In addition, the second start pulse Vst2 output in the second initial period T0B is also supplied to the second stage ST702. In detail, as illustrated in FIG. 11, the second start pulse Vst2 may include a gate terminal, a drain terminal, and a ninth switching element Tr9 of the first switching element Tr1 provided in the second stage ST702. ) And a gate terminal of the fifteenth switching element Tr15.

Therefore, in the second initial period T0B, the second stage ST702 is first enabled as the first stage ST701 is first enabled in the first initial period T0A. That is, in the second initial period T0B, the first node Q of the second stage ST702 is first charged and the second and third nodes QB1 and QB2 are discharged.

As such, during the second initial period T0B, as illustrated in FIG. 8, the first node Q of the first stage ST701 is charged secondly and the second and third nodes QB1,. As the QB2) is discharged, the first stage ST701 is secondary enabled. In addition, in the second initial period T0B, the second stage ST702 is first enabled.

Next, the operation during the first period T1 will be described.

During the first period T1, as shown in FIG. 8, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Therefore, in response to the first and second start pulses Vst1 and Vst2 in the low state, the first, second, fifth, ninth, eleventh, and fifteenth stages of the first stage ST701 are provided. The 16 switching elements Tr1, Tr2, Tr5, Tr9, Tr11, Tr15, and Tr16 are turned off, and thus the first node Q of the first stage ST701 is kept in a floating state.

Meanwhile, as the first node Q of the first stage ST701 is continuously maintained as the first and second start pulses Vst1 and Vst2 applied during the first and second initial periods T0B, The pull-up switching device Trpu of the first stage ST701 is turned on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Trpu, a first DC voltage source charged in the first node Q of the first stage ST701. Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Trpu of the first stage ST701 is stably output through the source terminal of the pull-up switching device Trpu. In this case, the output first clock pulse CLK1 is applied to a first gate line to function as a first gate on voltage Von1 driving the first gate line.

The first gate on voltage Von1 output from the first stage ST701 in the first period T1 is also input to the second stage ST702. In detail, the first gate on voltage Von1 may include a gate terminal of the second switching element Tr2, a gate terminal of the eleventh switching element Tr11, and a sixteenth switching element of the second stage ST702. It is input to the gate terminal of (Tr16).

Therefore, in the first period T1, the second stage ST702 is secondly enabled as if the first stage ST701 is secondly enabled in the second initial period T0B. That is, in the first period T1, the first node Q of the second stage ST702 is charged second and the second and third nodes QB1 and QB2 are discharged.

In addition, the first gate on voltage Von1 output from the first stage ST701 in the first period T1 is also supplied to the third stage ST703. In detail, the first gate on voltage Von1 may include a gate terminal of the first switching element Tr1, a gate terminal of the ninth switching element Tr9, and a fifteenth switching element of the third stage ST703. It is input to the gate terminal of (Tr15).

Therefore, the third stage ST703 is first enabled in the first period T1 as if the first stage ST701 is first enabled in the first initial period T0A. That is, in the first period T1, the first node Q of the third stage ST703 is first charged and the second node QB1 and the third node QB2 are discharged.

In this manner, during the first period T1, the first stage ST701 outputs the first gate on voltage Von1. The second stage ST702 is secondly enabled and the third stage ST703 is firstly enabled according to the first gate-on voltage Von1.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 8, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

During the second period T2, the second stage enabled STST702 receives the second clock pulse CLK2 and outputs the second clock pulse CLK2 as the second gate on voltage Von2. The second gate on voltage Von2 is supplied to the second gate line, the first stage ST701, the third stage ST703, and the fourth stage ST704.

Therefore, during the second period T2, the third stage ST703 is secondary enabled, and the fourth stage ST704 is primary enabled.

Meanwhile, the second gate on voltage Von2 output from the second stage ST702 in the second period T2 is supplied to the first stage ST701 to disable the second stage ST702. . If this is explained in more detail as follows.

The second gate on voltage Von2 output from the second stage ST702 in the second period T2 is supplied to the third switching device Tr3 of the first stage ST701. Specifically, the second gate on voltage Von2 is supplied to the gate terminal of the third switching element Tr3. Then, the third switching device Tr3 is turned on, and the second DC voltage source Vdc2 is turned on by the first node Q of the first stage ST701 through the turned-on third switching device Tr3. Is supplied. Accordingly, the first node Q is discharged and the pull-up switching device Trpu, the sixth switching device Tr6, and the tenth switching device Tr10 having a gate terminal connected to the discharged first node Q. , The twelfth switching element Tr12 and the seventeenth switching element Tr17 are turned off.

Here, as the sixth switching device Tr6 is turned off, the first common node N1 of the first stage ST701 switches the first AC voltage source Vac1 switched through the seventh switching device Tr7. Is maintained. Accordingly, the first common node N1 is charged, and the eighth switching device Tr8 having a gate terminal connected to the charged first common node N1 is turned on.

Then, the first AC voltage source Vac1 is supplied to the second node QB1 through the turned-on eighth switching device Tr8. Accordingly, the second node QB1 is charged, and the first pull-down switching device Trpd1 and the fourth switching device Tr4 having the gate terminal connected to the charged second node QB1 are turned on.

Meanwhile, as the twelfth and thirteenth switching elements Tr12 and Tr13 are turned off in the second period T2, the second common node N2 is connected to the previously supplied second DC voltage source Vdc2. maintain. Accordingly, the second common node N2 is discharged, and the fourteenth switching element Tr14 having the gate terminal connected to the discharged second common node N2 remains turned off. Accordingly, the third node QB2 of the first stage ST701 is still in a discharge state by the second DC voltage source Vdc2 that was previously supplied, and the third node QB2 has a gate terminal connected to the third node QB2. The second pull-down switching device Trpd2 and the fifth switching device Tr5 maintain a turn-off state.

At this time, the second DC voltage source Vdc2 is supplied as a gate-off voltage to the first gate line through the turned-on first pull-down switching device Trpd1. Meanwhile, the turned-on fourth switching device Tr4 discharges the first node Q by supplying the second DC voltage source Vdc2 to the first node Q of the first stage ST701. Accelerate the speed.

Thereafter, in the third period T3, the third stage ST703 outputs the third gate on voltage Von3, and the third gate on voltage Von3 is converted into the third gate line, the second stage ST702, It supplies to the 4th stage ST704 and the 5th stage. Therefore, in the third period T3, the second stage ST702 is disabled, the fourth stage ST704 is secondary enabled, and the fifth stage is primary enabled.

In the same manner, the remaining fourth to mth stages ST704 to ST70m operate during the first frame.

Meanwhile, in the second frame, as the first AC voltage source Vac1 is changed to a low voltage source and the second AC voltage source Vac2 is changed to a high voltage, the first frame of each stage ST701 to ST70m + 1 during the second frame. The seventh switching element Tr7 maintains the turn-off state and the thirteenth switching element Tr13 maintains the turn-on state.

Accordingly, in the disable operation, the second node QB1 of each stage ST701 to ST70m + 1 maintains a discharge state, and the third node QB2 is charged by the second AC voltage source Vac2. That is, during this second frame, the first pull-down switching device Trpd1 of each of the stages ST701 to ST70m + 1 has a rest period, and the second pull-down switching device Trpd2 operates. In this case, the third node QB2 of each of the stages ST701 to ST70m + 1 is charged by the second AC voltage source Vac2 supplied through the fourteenth switching element Tr14.

Meanwhile, the first stage ST701 may operate by receiving one start pulse. That is, the first stage ST701 may operate by receiving the second start pulse Vst2. In this case, the first stage ST701 is enabled only once by receiving the second start pulse Vst2.

In this case, the first, ninth, and fifteenth switching elements Tr1, Tr9, and Tr15 included in the first stage ST701 are removed.

As described above, the shift registers according to the first and second embodiments of the present invention reliably charge the first node Q of each of the stages ST701 to ST70m + 1, and also quickly charge it.

12 is a simulation waveform diagram for explaining the change in voltage of the first node of each stage. As shown in the figure, the first node Q of the current stage is placed between the first chargers Tc1. First charging is performed at a predetermined voltage according to the gate on voltage from the first front stage, and then second charging is performed at a predetermined voltage according to the gate on voltage from the first front stage between the second chargers Tc2. Thereafter, in the output period Tb, the voltage of the first node Q is further increased by bootstrapping. Meanwhile, the second node QB1 (or the third node QB2) is discharged to a predetermined voltage between the first and second chargers Tc1 and Tc2.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register according to the present invention as described above has the following advantages.

Each stage provided in the shift register according to the present invention is first enabled by the gate on voltage from the second front stage, and secondly enabled by the gate on voltage from the first front stage, and thus the first stage of each stage is provided. One node is quickly charged to a sufficiently large voltage. Therefore, the shift register according to the present invention can improve the output characteristic of each stage.

Claims (6)

A shift register comprising a plurality of stages sequentially outputting a gate on voltage for driving gate lines, Wherein each stage is enabled at least twice in response to a gate-on voltage from at least two stages located earlier than itself. The method of claim 1, The shift register is characterized in that the m (m is a natural number) stage is first enabled according to the gate-on voltage from the m-2 stage, and secondly enabled according to the gate-on voltage from the m-1 stage. . The method of claim 2, The m th stage, Charging the first node and discharging the second node in response to the gate on voltage from the m-th stage and the gate on voltage from the m-th stage, and according to the gate on voltage from the m + 1th stage. A node controller configured to discharge the first node and charge the second node; A pull-up switching device configured to output the gate on voltage according to the state of the first node; And, And a pull-down switching device configured to output the gate off voltage according to the state of the second node. The method of claim 3, wherein The node controller of the m th stage is A first switching element for first charging the first node with a first DC voltage source in response to a first start pulse from an external source or a gate-on voltage from an m-2th stage; A second switching device configured to secondary charge the first node with a first DC voltage source in response to a second start pulse from an external source or a gate on voltage from an m−1th stage; a third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from an m + 1 th stage; A fourth switching element configured to discharge the first node to a second DC voltage source in response to the first DC voltage source charged in the second node; a fifth switching device receiving a clock pulse corresponding to the gate on voltage output from the m + 1 th stage to charge the second node with a first DC voltage source; A sixth switching element discharging the second node to a second DC voltage source in response to the gate on voltage from the second start pulse or the m-2 th stage; A seventh switching device discharging the second node to a second DC voltage source in response to the gate on voltage from the second start pulse or the m-1 th stage; And, And an eighth switching device configured to discharge the second node to a second DC voltage source in response to the first DC voltage source charged in the first node. The method of claim 2, The m th stage, Charging a first node and discharging a second node and a third node in response to a gate on voltage from the m-2 th stage and a gate on voltage from the m-1 th stage, and a gate from the m + 1 th stage A node controller configured to discharge the first node and charge one of the second and third nodes according to the on voltage; A pull-up switching device configured to output the gate on voltage according to the state of the first node; A first pull-down switching device configured to output the gate off voltage according to the state of the second node; And, And a second pull-down switching device configured to output the gate off voltage according to the state of the third node. The method of claim 5, The node controller of the m th stage is A first switching device configured to first charge the first node to the first start pulse or the gate on voltage in response to a first start pulse from an external stage or a gate on voltage from an m−2th stage; A second switching device configured to secondary charge the first node to the second start pulse or the gate on voltage in response to a second start pulse from an external stage or a gate on voltage from an m−1th stage; a third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from an m + 1 th stage; A fourth switching element configured to discharge the first node to a second DC voltage source in response to a first AC voltage source charged in the second node; A fifth switching device configured to discharge the first node to a second DC voltage source in response to a second AC voltage source charged in the third node; A sixth switching device discharging the first common node to the second DC voltage source in response to the voltage source charged in the first node; A seventh switching element which is turned on or off in response to the first AC voltage source and supplies the first AC voltage source to the first common node when turned on; An eighth switching that is turned on or turned off in response to a second DC voltage source and a first AC voltage source supplied to the first common node, and charges or discharges the second node to the first AC voltage source at turn-on; device; A ninth switching device discharging the second node to a second DC voltage source in response to the gate on voltage from the first start pulse or the m-2 th stage; A tenth switching element configured to discharge the second node to a second DC voltage source in response to the voltage source charged in the first node; An eleventh switching device discharging the second node to a second DC voltage source in response to the gate on voltage from the second start pulse or the m-1 th stage; A twelfth switching element discharging a second common node to a second DC voltage source in response to the voltage source charged in the first node; A thirteenth switching element which is turned on or off in response to the second AC voltage source and supplies the second AC voltage source to the second common node when turned on; A fourteenth switching that is turned on or off in response to a second DC voltage source and a second AC voltage source supplied to the second common node, and charges or discharges the second node to the second AC voltage source at turn-on; device; A fifteenth switching element configured to discharge the third node to a second DC voltage source in response to the gate on voltage from the first start pulse or the m-2 th stage; A sixteenth switching element configured to discharge the third node to a second DC voltage source in response to the gate on voltage from the second start pulse or the m-1 th stage; And, And a seventeenth switching element configured to discharge the third node to a second DC voltage source in response to the voltage source charged in the first node.

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