KR20080062182A - A liquid crystal display device - Google Patents

A liquid crystal display device Download PDF

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Publication number
KR20080062182A
KR20080062182A KR1020060137642A KR20060137642A KR20080062182A KR 20080062182 A KR20080062182 A KR 20080062182A KR 1020060137642 A KR1020060137642 A KR 1020060137642A KR 20060137642 A KR20060137642 A KR 20060137642A KR 20080062182 A KR20080062182 A KR 20080062182A
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KR
South Korea
Prior art keywords
stage
switching
node
voltage source
response
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KR1020060137642A
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Korean (ko)
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KR101327840B1 (en
Inventor
장용호
전민두
조혁력
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엘지디스플레이 주식회사
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Priority to KR1020060137642A priority Critical patent/KR101327840B1/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit

Abstract

The present invention relates to a liquid crystal display device capable of reducing the size of the liquid crystal panel and improving output characteristics, the liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines; A shift register embedded in the liquid crystal panel and outputting a scan pulse for driving the gate lines; A plurality of control switching elements provided in the shift register to control an output of the shift register; A pixel switching element provided in the pixel region, for switching a data signal from the data line in response to a scan pulse from the gate line and supplying the data signal to a pixel electrode of the pixel region; A channel length of the pixel switching element and a channel length of the at least one control switching element are different from each other.

Description

Liquid crystal display device

1 is a block diagram of one stage in a conventional shift register

2 illustrates a shift register according to an embodiment of the present invention.

3 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 2 and an output signal output from each stage;

4 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth stages of FIG. 2.

5 is a view showing a liquid crystal panel with a shift register according to an embodiment of the present invention.

FIG. 6 is a diagram for explaining a comparison between an output from a conventional shift register and an output from a shift register according to the present invention. FIG.

* Explanation of symbols on the main parts of the drawings

205: node controller Tru: pull-up switching element

Trd: Pull-down switching element Vac: AC voltage source

Vdc: DC voltage source ST: Stage

Vout: Scan pulse Q: Enable node

QB: Node for disable

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing the size of the liquid crystal panel and improving output characteristics.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register to sequentially output the scan pulses as described above. This will be described in more detail with reference to the accompanying drawings.

The shift register has a plurality of stages arranged in a line. Each stage is connected to gate lines, respectively, to supply a scan pulse to each gate line.

Each stage is then enabled in response to the scan pulse from the preceding stage and disabled in response to the scan pulse from the next stage.

In general, each stage includes a node controller for controlling the charging and discharging states of the enable node and the disable node, a pull-up switching device that outputs a scan pulse according to the state of the enable node, and the disable And a pull-down switching device for outputting an off voltage according to the state of the node.

On the other hand, since each stage outputs an off voltage for the remaining period except one horizontal period (1H) of one frame, the time for which the disable node is kept in the charged state is maintained in the charged state. It will be much longer than it will be. Accordingly, the pull-down switching device connected to the disable node remains turned on for much longer than the pull-up switching device. This causes a problem that the pull-down switching device is easily degraded.

In order to solve this problem, a shift register having a stage having two or more disable nodes has been developed. Such a shift register may alternately charge the disable nodes on a frame-by-frame basis to prevent deterioration of a pull-down switching device connected to each disable node.

Hereinafter, a configuration of a conventional stage will be described in detail with reference to the accompanying drawings.

1 is a block diagram of one stage in a conventional shift register.

In the conventional stage, as shown in FIG. 1, the charge / discharge state of the enable node Q, the charge / discharge state of the first disable node QB1, and the second disable node ( The node control unit 201 for controlling the charge / discharge state of the QB2, the pull-up switching device Tru which outputs a scan pulse Vout according to the state of the enable node Q, and the first disable. A first pull-down switching device Trd1 outputting the off voltage source Vdc2 according to the state of the node QB1, and a second outputting off voltage source Vdc2 according to the state of the second disable node QB2. And a pull-down switching device Trd2.

Here, one of the first and second disable nodes QB2 is charged while the stage is disabled, and the other is discharged. For example, when the first disable node QB1 is charged and the second disable node QB2 is discharged, a first pull-down in which a gate terminal is connected to the first disable node QB1 is discharged. The switching element Trd1 operates, and the second pull-down switching element Trd2 having the gate terminal connected to the second disable node QB2 does not operate. That is, the second pull-down switching device Trd2 has a rest period.

As described above, since the first pull-down switching device Trd1 and the second pull-down switching device Trd2 are alternately driven, deterioration of each pull-down switching device can be prevented.

However, due to this structure, the node control unit 201 of the conventional stage is provided with a large number of switching elements. That is, the node controller 201 may have a large number of switching elements for controlling one enable node Q and two disable nodes QB1 and QB2. This increases the size of the stage and increases the cost associated with a large number of switching elements.

The present invention has been made to solve the above problems, by reducing the number of switching elements by allowing the node control unit of each stage to control the disable node and the disable node of the other stage together The purpose is to provide a shift register that can reduce the size of the stage.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines; A shift register embedded in the liquid crystal panel and outputting a scan pulse for driving the gate lines; A plurality of control switching elements provided in the shift register to control an output of the shift register; A pixel switching element provided in the pixel region, for switching a data signal from the data line in response to a scan pulse from the gate line and supplying the data signal to a pixel electrode of the pixel region; A channel length of the pixel switching element and a channel length of the at least one control switching element are different from each other.

Hereinafter, a shift register and a liquid crystal display having the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 2 and an output signal output from each stage.

Hereinafter, all the switching elements, the pull-up switching element, and the pull-down switching element are one of an N-type metal oxide semiconductor (MOS) transistor and a P-type MOS transistor, and the present invention will be described using an N-type MOS transistor.

The shift register according to the first embodiment of the present invention has a plurality of stages ST201, ST202, ST203, ... for driving the plurality of gate lines, as shown in FIG.

Here, each stage ST201, ST202, ST203, ... includes an enable node Q, a pull-up switching element Tru connected to the enable node Q, and a first disable node QB1. ), A first pull-down switching device Trd1 connected to the first disable node QB1, a second disable node QB2, and a second connect node connected to the second disable node QB2. 2 pull-down switching device (Trd2).

The node control unit 205 provided in the 2n-3 (n is a natural number of 2 or more) stages is used to charge / enable the enable node Q and the first disable node QB1 provided in the 2n-3 stage. In addition to controlling the discharge state, the charge / discharge state of the first disable node QB1 provided in the 2n-2 stage is controlled.

The node control unit 205 provided in the second n-2 stage controls the charging / discharging states of the enable node Q and the second disable node QB2 provided in the second n-2 stage. In addition, the charge / discharge state of the second disable node QB2 included in the second n-3 stage is controlled.

To this end, the first disable node QB1 of the 2n-3 stage and the first disable node QB1 of the 2n-2 stage are connected to each other, and the second disable node QB1 of the 2n-2 stage is connected to each other. The disable node QB2 and the second disable node QB2 of the 2n-2 stage are electrically connected to each other.

For example, the node controller 205 provided in the third stage ST203 may be configured to charge / charge the enable node Q and the first disable node QB1 provided in the third stage ST203. In addition to controlling the discharge state, the charge / discharge state of the first disable node QB1 included in the fourth stage ST204 is controlled.

The node control unit 205 provided in the fourth stage ST204 may be configured to charge / discharge states of the enable node Q and the second disable node QB2 provided in the fourth stage ST204. And control the charge / discharge state of the second disable node QB2 included in the third stage ST203.

To this end, the first disable node QB1 of the third stage ST203 and the first disable node QB1 of the fourth stage ST204 are connected to each other, and the fourth stage ST204 is connected to each other. The second disable node QB2 of FIG. 3) and the second disable node QB2 of the third stage ST203 are electrically connected to each other.

In particular, the node control unit 205 provided in the second n-3 stage includes the charge / discharge state of the first disable node QB1 provided in the second n-3 stage and the second nn stage. The charge / discharge state of the first disable node QB1 is controlled by the first AC voltage source.

The node control unit 205 provided in the 2n-2th stage is configured for the second disable node QB2 provided in the 2n-2 stage and the second disable unit provided in the 2n-3 stage. The charging / discharging state of the node QB2 is controlled by the second AC voltage source Vac2.

That is, each node control unit 205 provided in the odd stages ST201, ST203, ST205,..., Among the stages ST201, ST202, ST203,... ) Is supplied, and each node controller 205 provided in even-numbered stages ST202, ST204, ST206,... Is supplied with the second AC voltage source Vac2.

Here, the first AC voltage source Vac1 and the second AC voltage source Vac2 are AC voltage sources whose voltage changes in units of frames, and the first AC voltage source Vac1 is 180 degrees with respect to the second AC voltage source Vac2. It has a phase inverted form.

Meanwhile, each of the stages ST201, ST202, ST203, ... receives a first DC voltage source Vdc1 to charge its enable node Q, and receives a second DC voltage source Vdc2. This is output as an off voltage source.

In addition, each stage ST201, ST202, ST203, ... may receive the scan pulse from the front stage instead of the first DC voltage source Vdc1 to charge its enable node Q.

Here, the first DC voltage source Vdc1 means a positive voltage source, and the second DC voltage source Vdc2 means a negative voltage source.

Each of the stages ST201, ST202, ST203, ... configured as described above receives one of the first to fourth clock pulses CLK1 to CLK4 and outputs the supplied clock pulse as a scan pulse. .

As shown in FIG. 3, the first to fourth clock pulses CLK1 to CLK4 are delayed by one pulse width and output. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is one pulse than the second clock pulse CLK2. Phase delayed by a width and output, the fourth clock pulse (CLK4) is phase-delayed output by one pulse width than the third clock pulse (CLK3), and output by one pulse width than the fourth clock pulse (CLK4) The phase is delayed and output by being delayed by one pulse width than the first clock pulse CLK1.

In this case, the first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2.

Each of the first to fourth clock pulses CLK1 to CLK4 is continuously output at a predetermined period. Therefore, when four clock pulses are used as described above, the first to fourth stages ST201 to ST204 output the first to fourth clock pulses CLK1 to CLK4 as scan pulses.

At this time, since the first to fourth clock pulses CLK1 to CLK4 are phase-delayed by one clock pulse as described above, each of the scan pulses output from the first to fourth stages ST201 to ST204. (Vout1 to Vout4) are also phase-delayed by one pulse width and outputted.

That is, the scan pulses Vout1 to Vout4 are sequentially output. The fifth stage ST205 again outputs the first clock pulse CLK1 as a sixth scan pulse Vout6. At this time, the first clock pulse CLK1 output by the fifth stage ST205 is a pulse delayed by one period from the first clock pulse CLK1 output from the first stage ST201.

On the other hand, in order for each stage ST201, ST202, ST203, ... to output the scan pulse as described above, each stage ST201, ST202, ST203, ... must be enabled and Each stage ST201, ST202, ST203, ... must be disabled in order to output an off voltage source.

For this purpose, each stage ST201, ST202, ST203, ... is enabled in response to the scan pulse from the front stage, and disabled in response to the scan pulse from the rear stage.

The 2n-1 and 2n stages are simultaneously enabled in response to the 2n-2 scan pulses from the 2n-2 stages and simultaneously disabled in response to the 2n + 2 scan pulses from the 2n + 2 stages. do.

The enabled 2n stage outputs a 2n scan pulse, and supplies the 2n scan pulse to the 2n + 1 and 2n + 2 stages, thereby providing the 2n + 1 and 2n + 2 stages. Enable at the same time. In addition, the second n stage simultaneously disables the second n-3 and second n-2 stages by supplying the second n scan pulses to the second n-3 and second n-2 stages.

For example, the third stage ST203 and the fourth stage ST204 of FIG. 2 are simultaneously enabled in response to the second scan pulse Vout2 from the second stage ST202, and the sixth stage ST206. Are simultaneously disabled in response to the sixth scan pulse Vout6 from

The enabled fourth stage ST204 outputs the fourth scan pulse Vout4 and supplies the fourth scan pulse Vout4 to the fifth and sixth stages ST205 and ST206. And the sixth stages ST205 and ST206 at the same time. In addition, the fourth stage ST204 simultaneously disables the first and second stages ST201 and ST202 by supplying the fourth scan pulse Vout4 to the first and second stages ST201 and ST202. .

On the other hand, the first and second stages ST201 and ST202 are enabled in response to the start pulse Vst from the timing controller.

Here, the configuration of each node control unit 205 provided in the stages ST201, ST202, ST203, ... will be described in more detail as follows.

4 is a diagram illustrating a circuit configuration of the node controller provided in the third and fourth stages of FIG. 2.

Here, the odd-numbered stages (2n-1st stages ST201, ST203, ST205, ...) and the even-numbered stages (2nn stages ST202, ST204, ST206, ...) have different configurations.

First, the node control unit 205 provided in the odd stages ST201, ST203, ST205, ... has first to eleventh switching elements Tr1 to Tr11, as shown in FIG.

That is, the first switching device Tr1 provided in the 2n-1 stage transmits the enable node Q of the 2n-1 stage to the first DC voltage source in response to the scan pulse from the 2n-2 stage. Charge to Vdc1).

For example, the first switching device Tr1 included in the third stage ST203 of FIG. 4 may be configured to respond to the second scan pulse Vout2 from the second stage ST202 of the third stage ST203. The enable node Q is charged with the first DC voltage source Vdc1.

To this end, a gate terminal of the first switching device Tr1 provided in the third stage ST203 is connected to the second stage ST202, and a drain terminal of the power supply line for transmitting the first DC voltage source Vdc1. The source terminal is connected to the enabling node Q of the third stage ST203.

The second switching device Tr2 provided in the 2n-1 stage is in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the 2n-1 stage. The enable node Q of the stage is discharged to the second DC voltage source Vdc2.

For example, the second switching device Tr2 provided in the third stage ST203 of FIG. 4 is the first AC voltage source Vac1 supplied to the first disable node QB1 of the third stage ST203. In response to), the enabling node Q of the third stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the second switching device Tr2 provided in the third stage ST203 is connected to the first disable node QB1 of the third stage ST203, and the drain terminal thereof is connected to the third disable node QB1. It is connected to the enable node Q of the stage ST203, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The third switching device Tr3 provided in the 2n-1 stage responds to the second AC voltage source Vac2 supplied to the second disable node QB2 of the 2n-1 stage through the 2nn stage. Thus, the enable node Q of the 2n-1 stage is discharged to the second DC voltage source Vdc2.

That is, the third switching device Tr3 provided in the 2n-1 stage is configured to respond to the second AC voltage source Vac2 supplied to the second disable node QB2 of the 2n-1 stage. The enable node Q of the 2n-1 stage is discharged to the second DC voltage source Vdc2, where the state of the second disable node QB2 provided in the 2n-1 stage is the second n stage. Is controlled by the node control unit 205.

For example, the third switching device Tr3 included in the third stage ST203 of FIG. 4 is connected to the second disable node QB2 of the third stage ST203 through the fourth stage ST204. In response to the supplied second AC voltage source Vac2, the enable node Q of the third stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the third switching device Tr3 provided in the third stage ST203 is connected to the second disable node QB2 of the third stage ST203, and the drain terminal of the third stage ST203 is connected to the second disable node QB2. It is connected to the enable node Q of the three stages ST203, and the source terminal is connected to a power supply line for transmitting the second DC voltage source Vdc2.

The fourth switching device Tr4 provided in the 2n-1 stage transmits the enable node Q of the 2n-1 stage to the second DC voltage source Vdc2 in response to the scan pulse from the 2n + 2th stage. To discharge).

For example, the fourth switching device Tr4 included in the third stage ST203 of FIG. 4 may be configured to respond to the sixth scan pulse Vout6 from the sixth stage ST206 of the third stage ST203. The enable node Q is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the fourth switching device Tr4 provided in the third stage ST203 is connected to the sixth stage ST206, and the drain terminal is a node for enabling the third stage ST203. It is connected to (Q), the source terminal is connected to the power supply line for transmitting the second DC voltage source (Vdc2).

The fifth switching device Tr5 provided in the 2n-1 stage is turned on or turned off in response to the first AC voltage source Vac1 and, when turned on, the common node N of the 2n-1 stage. ) Is charged to the first AC voltage source Vac1.

For example, the fifth switching device Tr5 provided in the third stage ST203 of FIG. 4 is turned on or turned off in response to a first AC voltage source Vac1, and when turned on, the third stage The common node N of ST203 is charged with the first AC voltage source Vac1.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the third stage ST203 are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal is connected to the third terminal ST203. It is connected to the common node N of the stage ST203.

The sixth switching device Tr6 provided in the 2n-1 stage is the second n-1 stage in response to the first DC voltage source Vdc1 charged in the enabling node Q of the 2n-1 stage. Common node N is discharged to second DC voltage source Vdc2.

For example, the sixth switching device Tr6 provided in the third stage ST203 of FIG. 4 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the third stage ST203. In response, the common node N of the third stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the sixth switching element Tr6 provided in the third stage ST203 is connected to the enable node Q of the third stage ST203, and the drain terminal of the third stage ST203 is provided. It is connected to the common node N of ST203, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The seventh switching device Tr7 provided in the 2n-1 stage is formed in response to the first AC voltage source Vac1 supplied to the common node N of the 2n-1 stage. The first disable node QB1 and the first disable node QB1 of the second nn stage are charged with the first AC voltage source Vac1.

That is, the seventh switching device Tr7 included in the 2n-1 stage is for the state of the first disable node QB1 provided in the 2n-1 stage and for the first disable provided in the 2n stage. The state of node QB1 is controlled together.

For example, the seventh switching device Tr7 included in the third stage ST203 of FIG. 4 may respond to the first AC voltage source Vac1 supplied to the common node N of the third stage ST203. The first disable node QB1 of the third stage ST203 and the first disable node QB1 of the fourth stage ST204 are charged with the first AC voltage source Vac1.

To this end, the gate terminal of the seventh switching device Tr7 provided in the third stage ST203 is connected to the common node N of the third stage ST203, and the drain terminal of the first AC voltage source is provided. It is connected to the power supply line which transmits (Vac1), and a source terminal is connected to the 1st disable node QB1 of the said 3rd stage ST203.

The eighth switching device Tr8 provided in the 2n-1 stage includes the first disable node QB1 and the 2n stage of the 2n-1 stage in response to the scan pulse from the 2n-2 stage. The first disable node QB1 is discharged to the second DC voltage source Vdc2.

That is, the eighth switching device Tr8 provided in the 2n-1 stage is for the first disable node QB1 provided in the 2n-1 stage and the first disable device provided in the 2nn stage. The state of node QB1 is controlled together.

For example, the eighth switching device Tr8 of the third stage ST203 of FIG. 4 may be configured to respond to the second scan pulse Vout2 from the second stage ST202 of the third stage ST203. The first disable node QB1 of the first disable node QB1 and the fourth stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the eighth switching element Tr8 provided in the third stage ST203 is connected to the second stage ST202, and the drain terminal of the first stage ST203 is disabled. It is connected to the node QB1, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The ninth switching device Tr9 of the 2n-1 stage is provided in response to the first DC voltage source Vdc1 charged in the enabling node Q of the 2n-1 stage. The first disable node QB1 and the first disable node QB1 of the second nn stage are discharged to the second DC voltage source Vdc2.

That is, the ninth switching device Tr9 provided in the second n-1 stage is in a state of the first disable node QB1 provided in the second n-1 stage and the first disable provided in the second nn stage. The state of the node QB1 is controlled together.

For example, the ninth switching device Tr9 of the third stage ST203 of FIG. 4 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the third stage ST203. In response, the first disable node QB1 of the third stage ST203 and the first disable node QB1 of the fourth stage ST204 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the ninth switching device Tr9 provided in the third stage ST203 is connected to the enable node Q of the third stage ST203, and the drain terminal of the third stage ST203 is provided. It is connected to the first disable node QB1 of ST203, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The tenth switching device Tr10 of the 2n-1 stage moves the common node N of the 2n-1 stage to the second DC voltage source Vdc2 in response to the start pulse Vst from the timing controller. Discharge.

For example, the tenth switching element Tr10 included in the third stage ST203 of FIG. 4 controls the common node N of the third stage ST203 in response to the start pulse Vst from the timing controller. Discharge to the second DC voltage source Vdc2.

To this end, the gate terminal of the tenth switching element Tr10 provided in the third stage ST203 is connected to the timing controller, and the drain terminal is connected to the common node N of the third stage ST203. The source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The tenth switching device Tr10 discharges (initializes) the common node N included in the stage to which the stage belongs to it in response to the start pulse Vst outputted once every frame.

The eleventh switching element Tr11 provided in the 2n-1 stage (including the first stage ST201) is turned on or turned off in response to the first AC voltage source Vac1 and is turned on. The second disable node QB2 of the 2n-1 stage is discharged to the second DC voltage source Vdc2.

That is, the eleventh switching device Tr11 provided in the 2n-1 stage directly discharges the second disable node QB2 of the 2n-1 stage. In other words, the 2n-1 stage controls the state of the second disable node QB2 provided therein by the eleventh switching element Tr11 and the node controller 205 of the 2n stage.

For example, the eleventh switching element Tr11 included in the third stage ST203 of FIG. 4 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the third switching element Tr11 is turned on. The second disable node QB2 of the stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, a gate terminal of the eleventh switching element Tr11 is connected to a power line for transmitting the first AC voltage source Vac1, and a drain terminal of the second disable node of the third stage ST203 QB2), the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

Meanwhile, the pull-up switching device Tru provided in the 2n-1 stage transmits the corresponding clock pulse to the 2n-1 stage in response to the first DC voltage source Vdc1 charged in the enable node Q of the 2n-1 stage. -1 Output as scan pulse. The 2n-1 scan pulse is supplied to the 2n-1 gate line.

For example, the pull-up switching device Tru provided in the third stage ST203 of FIG. 4 responds to the first DC voltage source Vdc1 charged in the enabling node Q of the third stage ST203. The third clock pulse CLK3 is output as the third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line.

To this end, a gate terminal of the pull-up switching device Tru provided in the third stage ST203 is connected to an enable node Q of the third stage ST203, and a drain terminal thereof is connected to the third clock pulse. It is connected to a clock transmission line for transmitting CLK3, and a source terminal is connected to the third gate line.

The first pull-down switching device Trd1 included in the 2n-1 stage has a second direct current in response to the first AC voltage source Vac1 charged in the first disable node QB1 of the 2n-1 stage. The voltage source Vdc2 is output as an off voltage source. Then, this off voltage source is supplied to the 2n-1 gate line.

For example, the first pull-down switching device Trd1 included in the third stage ST203 of FIG. 4 may include the first AC voltage source Vac1 charged in the first disable node QB1 of the third stage ST203. The second direct current voltage source Vdc2 is output as an off voltage source, and the off voltage source is supplied to the third gate line in response to.

To this end, the gate terminal of the first pull-down switching device Trd1 provided in the third stage ST203 is connected to the first disable node QB1 of the third stage ST203, and the source terminal is It is connected to the power supply line which transmits the 2nd DC voltage source Vdc2, and the drain terminal is connected to the said 3rd gate line.

The second pull-down switching device Trd2 provided in the 2n-1 stage responds to the second AC voltage source Vac2 charged in the second disable node QB2 of the 2n-1 stage through the 2n stage. To output the second DC voltage source Vdc2 as an off voltage source. Then, this off voltage source is supplied to the 2n-1 gate line.

That is, the second pull-down switching device Trd2 provided in the 2n-1 stage is configured in response to the second AC voltage source Vac2 supplied to the second disable node QB2 of the 2n-1 stage. The state of the second disable node QB2 included in the 2n-1 stage is controlled by the node controller 205 of the 2n stage.

For example, the second pull-down switching device Trd2 included in the third stage ST203 of FIG. 4 is the second AC voltage source Vac2 charged in the second disable node QB2 of the third stage ST203. The second DC voltage source Vdc2 is output as an off voltage source, and the off voltage source is supplied to the third gate line.

To this end, the gate terminal of the second pull-down switching device Trd2 provided in the third stage ST203 is connected to the second disable node QB2 of the third stage ST203, and the source terminal is It is connected to the power supply line which transmits the 2nd DC voltage source Vdc2, and the drain terminal is connected to the said 3rd gate line.

On the other hand, since the stage does not exist in the first front end of the first stage ST201, the first and eighth switching elements Tr1 and Tr8 included in the first stage ST201 have the start pulse (Tr1) from the timing controller. Operate in response to Vst).

Meanwhile, the node controller 205 provided in even-numbered stages ST202, ST204, ST206, ... also has first to eleventh switching elements Tr1 to Tr11, as shown in FIG.

That is, the first switching device Tr1 provided in the second n-th stage charges the enabling node Q of the second n-th stage to the first DC voltage source Vdc1 in response to the scan pulse from the second n-2 stage. Let's do it.

For example, the first switching device Tr1 included in the fourth stage ST204 of FIG. 4 may be configured to respond to the second scan pulse Vout2 from the second stage ST202 of the fourth stage ST204. The enable node Q is charged with the first DC voltage source Vdc1.

To this end, the gate terminal of the first switching device Tr1 provided in the fourth stage ST204 is connected to the second stage ST202, and the drain terminal is a power source for transmitting the first DC voltage source Vdc1. The source terminal is connected to the enable node Q of the fourth stage ST204.

The second switching device Tr2 provided in the second nn stage is provided in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the second nn stage through the second n-1 stage. The enable node Q of the stage is discharged to the second DC voltage source Vdc2.

That is, the second switching device Tr2 provided in the second n-stage is in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the second n-th stage. The enable node Q is discharged to the second DC voltage source Vdc2, wherein the state of the first disable node QB1 provided in the second n-stage is determined by the node controller 205 of the second n-1 stage. Controlled by

For example, the second switching device Tr2 included in the fourth stage ST204 of FIG. 4 is connected to the first disable node QB1 of the fourth stage ST204 through the third stage ST203. The enable node Q of the fourth stage ST204 is discharged to the second DC voltage source Vdc2 in response to the supplied first AC voltage source Vac1.

To this end, the gate terminal of the second switching element Tr2 provided in the fourth stage ST204 is connected to the first disable node QB1 of the fourth stage ST204, and the drain terminal of the second switching element Tr2 is connected to the first disable node QB1. It is connected to the enable node Q of the 4th stage ST204, and a source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The third switching device Tr3 provided in the second n stage is configured to enable the second n stage in response to a second AC voltage source Vac2 supplied to the second disable node QB2 of the second n stage. The node Q is discharged to the second DC voltage source Vdc2.

For example, the third switching device Tr3 included in the fourth stage ST204 of FIG. 4 is the second AC voltage source Vac2 supplied to the second disable node QB2 of the fourth stage ST204. In response to), the enable node Q of the fourth stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the third switching device Tr3 provided in the fourth stage ST204 is connected to the second disable node QB2 of the fourth stage ST204, and the drain terminal of the third switching element Tr3 is connected to the fourth terminal ST204. It is connected to the enable node Q of the 4th stage ST204, and a source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The fourth switching device Tr4 provided in the second nn stage discharges the enable node Q to the second DC voltage source Vdc2 in response to the scan pulse from the second n + 2th stage.

For example, the fourth switching device Tr4 included in the fourth stage ST204 of FIG. 4 may be configured to respond to the sixth scan pulse Vout6 from the sixth stage ST206 of the fourth stage ST204. The enable node Q is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the fourth switching device Tr4 provided in the fourth stage ST204 is connected to the sixth stage ST206, and the drain terminal is for enabling the fourth stage ST204. It is connected to the node Q, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The fifth switching device Tr5 provided in the second n-th stage is turned on or off in response to a second AC voltage source Vac2, and when turned on, the fifth switching element Tr5 turns off the common node N of the second n-th stage. 2 Charge with AC voltage source (Vac2).

For example, the fifth switching device Tr5 provided in the fourth stage ST204 of FIG. 4 is turned on or turned off in response to a second AC voltage source Vac2, and when turned on, the fourth stage ST204 is turned on. The common node N of ST204 is charged with the second AC voltage source Vac2.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the fourth stage ST204 are connected to a power line for transmitting the second AC voltage source Vac2, and the source terminal is connected to the fourth terminal ST204. It is connected to the common node N of the stage ST204.

The sixth switching device Tr6 included in the second n-th stage is the common node N of the second n-th stage in response to the first DC voltage source Vdc1 charged in the enabling node Q of the second n-th stage. Is discharged to the second DC voltage source Vdc2.

For example, the sixth switching device Tr6 included in the fourth stage ST204 of FIG. 4 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST204. In response, the common node N of the fourth stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the sixth switching element Tr6 provided in the fourth stage ST204 is connected to the enable node Q of the fourth stage ST204, and the drain terminal is connected to the fourth stage. It is connected to the common node N of ST204, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The seventh switching element Tr7 included in the second n-th stage is configured as a second disable node of the second n-th stage in response to the second AC voltage source Vac2 supplied to the common node N of the second n-th stage. QB2) and the second disable node QB2 of the 2n-1 stage are charged with the second AC voltage source Vac2.

That is, the seventh switching device Tr7 included in the second n stage includes the state of the second disable node QB2 provided in the second n stage and the second disable node provided in the 2n-1 stage. The state of (QB2) is controlled together.

For example, the seventh switching device Tr7 provided in the fourth stage ST204 of FIG. 4 may respond to the second AC voltage source Vac2 supplied to the common node N of the fourth stage ST204. The second disable node QB2 of the fourth stage ST204 and the second disable node QB2 of the third stage ST203 are charged with the second AC voltage source Vac2.

To this end, the gate terminal of the seventh switching element Tr7 provided in the fourth stage ST204 is connected to the common node N of the fourth stage ST204, and the drain terminal of the second AC voltage source ( Vac2) is connected to the power supply line, and the source terminal is connected to the second disable node QB2 of the fourth stage ST204.

The eighth switching device Tr8 provided in the second n-th stage includes the second disable node QB2 of the second n-th stage and the second n-th stage of the second n-1 stage in response to the scan pulse from the second n-2 stage. The disable node QB2 is discharged to the second DC voltage source Vdc2.

That is, the eighth switching device Tr8 provided in the second n-stage includes the state of the second disable node QB2 provided in the second n-n stage and the second disable node provided in the 2n-1th stage. The state of (QB2) is controlled together.

For example, the eighth switching device Tr8 of the fourth stage ST204 of FIG. 4 may be configured to respond to the second scan pulse Vout2 from the second stage ST202 of the fourth stage ST204. The second disable node QB2 of the second disable node QB2 and the third stage ST203 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the eighth switching element Tr8 provided in the fourth stage ST204 is connected to the second stage ST202, and the drain terminal of the third stage ST203 is disabled. It is connected to the node QB2, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The ninth switching device Tr9 provided in the second n stage is configured to disable the second disable of the second n stage in response to the first DC voltage source Vdc1 charged in the enabling node Q of the second n stage. The node QB2 and the second disable node QB2 of the 2n-1 stage are discharged to the second DC voltage source Vdc2.

That is, the ninth switching device Tr9 provided in the second n-stage is for the state of the second disable node QB2 provided in the second n-n stage and for the second disable provided in the 2n-1th stage. The state of node QB2 is controlled together.

For example, the ninth switching device Tr9 of the fourth stage ST204 of FIG. 4 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST204. In response, the second disable node QB2 of the fourth stage ST204 and the second disable node QB2 of the third stage ST203 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the ninth switching device Tr9 provided in the fourth stage ST204 is connected to the enable node Q of the fourth stage ST204, and the drain terminal of the fourth stage ST204 is connected to the enable node Q. It is connected to the second disable node QB2 of ST204, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The tenth switching device Tr10 provided in the second nn stage discharges the common node N of the second nn stage to the second DC voltage source Vdc2 in response to the start pulse Vst from the timing controller.

For example, the tenth switching element Tr10 included in the fourth stage ST204 of FIG. 4 receives the common node N of the third stage ST203 in response to the start pulse Vst from the timing controller. Discharge to the second DC voltage source Vdc2.

To this end, the gate terminal of the tenth switching element Tr10 provided in the fourth stage ST204 is connected to the timing controller, and the drain terminal is connected to the common node N of the third stage ST203. The source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The tenth switching element Tr10 discharges (initializes) the common node N provided in the stage to which the stage belongs to it in response to the start pulse Vst outputted once every frame.

The eleventh switching element Tr11 included in the second n stage (including the second stage ST202) is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the second n The first disable node QB1 of the stage is discharged to the second DC voltage source Vdc2.

That is, the eleventh switching device Tr11 provided in the second n stage directly discharges the second disable node QB2 of the second nn stage. In other words, the second n-th stage controls the state of the first disable node QB1 included in the second n-th stage together with the node controller 205 of the eleventh switching element Tr11 and the 2n-1st stage.

For example, the eleventh switching element Tr11 provided in the fourth stage ST204 of FIG. 4 is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the fourth switching element Tr11 is turned on. The first disable node QB1 of the stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, a gate terminal of the eleventh switching element Tr11 provided in the fourth stage ST204 is connected to a power line for transmitting the second AC voltage source Vac2, and a drain terminal thereof is connected to the fourth stage ST204. Is connected to a first disable node QB1, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The scan pulse output from the pull-up switching device Tru provided in the 2n stage, and the off voltage sources output from the first and second pull-down switching devices Trd1 and Trd2 provided in the second n stage may include a second n gate line, It is supplied to a 2n + 1 stage, a 2n + 2 stage, a 2n-3 stage, and a 2n-2 stage.

For example, the fourth scan pulse Vout4 output from the pull-up switching device Tru provided in the fourth stage ST204, and the first and second pull-down switching devices provided in the fourth stage ST204 The off voltage sources output from Trd1 and Trd2 are supplied to the fourth gate line, the fifth stage ST205, the sixth stage ST206, the first stage ST201, and the second stage ST202.

As described above, the shift register according to the present invention can reduce the number of switching elements for controlling the nodes as compared with the conventional stage because the adjacent stages share the nodes of each other.

The shift register configured as described above is embedded in the liquid crystal panel. That is, all the switching elements included in the shift register are devices having a semiconductor layer made of amorphous silicon, and they are manufactured through the same process as the pixel switching elements formed in the display unit of the liquid crystal panel.

5 is a view showing a liquid crystal panel in which a shift register is incorporated according to an embodiment of the present invention.

As shown in FIG. 5, the liquid crystal panel 600 includes a display unit 600a and a non-display unit 600b surrounding the display unit 600a.

The display unit 600a is an area for displaying an image, and the display unit 600a includes a plurality of pixel areas PD defined by a plurality of gate lines GL and a plurality of data lines DL that cross each other. ) In each pixel area PD, a pixel switching element TFT (thin film transistor) and a pixel electrode PXL are formed.

The pixel switching element TFT is turned on when a scan pulse is applied to supply the data signal to the pixel electrode PXL, and then turned off to supply the data signal supplied to the pixel electrode PXL to the next frame. Keep up to time.

The off-state characteristic is important because the pixel switching element TFT is turned off for most of the time.

In contrast, all the control switching elements included in the shift register SR, that is, the pull-up switching device Tru, the first pull-down switching device Trd1, the second pull-down switching device Trd2, and the first to elevenths. The switching currents Tr1 to Tr11 have an on current characteristic because the voltage sources for charging and discharging the nodes Q, QB1 and QB2 are continuously supplied.

Accordingly, the on / off ratio of the pixel switching element TFT is very important, and the on / off ratio of the control switching element is less important than the pixel switching element TFT.

In general, the on current of the switching element is inversely proportional to its channel length. That is, the shorter the channel length is, the on current increases. However, on the contrary, leakage current also increases.

In the present invention, the size of the liquid crystal panel 600 is reduced by reducing the channel length of the control switching element to be smaller than the channel length of the pixel switching element TFT based on the fact that the on / off ratio of the control switching elements may be small. In addition to reducing the power consumption and improving the output characteristics through the on-current gain.

Specifically, the control switching elements are the pull-up switching device Tru, the first pull-down switching device Trd1, the second pull-down switching device Trd2, and the first to eleventh switching elements provided in the 2n-th stage. Tr1 to Tr11, the pull-up switching device Tru, the first pull-down switching device Trd1, the second pull-down switching device Trd2, and the first to eleventh switching elements provided in the 2n-1th stage. Tr1 to Tr11),

The effect can be achieved by making the channel length of each switching element included in the control switching elements smaller than the channel length of the pixel switching element TFT.

In this case, the channel length of each switching element included in the control switching elements may have a size between 1% and 50% of the channel length of the pixel switching element TFT.

Alternatively, the effect may be achieved by making the channel length of the pull-up switching device Tru provided in the 2n-1 th stage smaller than the channel length of the pixel switching device TFT.

In this case, the channel length of the pull-up switching device Tru provided in the 2n-1 th stage may have a size between 1% and 50% of the channel length of the pixel switching device TFT.

Alternatively, the first switching device Tr1 provided in the 2n-1st stage, the first switching device Tr1 provided in the 2nth stage, and the fifth switching device provided in the 2n-1st stage (Tr5), the fifth switching element Tr5 provided in the 2nth stage, the seventh switching element Tr7 provided in the 2n-1st stage, and the seventh switching element Tr7 provided in the 2nth stage The above effect can be achieved by making any one channel length smaller than the channel length of the pixel switching element TFT.

At this time, the first switching device Tr1 provided in the 2n-1st stage, the first switching device Tr1 provided in the 2nth stage, and the fifth switching device Tr5 provided in the 2n-1st stage Among the fifth switching device Tr5 provided in the 2nth stage, the seventh switching device Tr7 provided in the 2n-1st stage, and the seventh switching device Tr7 provided in the 2nth stage, One channel length may have a size between 1% and 50% of the channel length of the pixel switching element TFT.

FIG. 6 is a diagram for explaining a comparison between an output from a conventional shift register and an output from a shift register according to the present invention.

As shown in Fig. 6, the scan pulse Vout_P from the shift register SR of the present invention using the control switching element having a channel length of 40 μm is a conventional shift using the control switching element having a channel length of 45 μm. It has a faster rising time and a falling time compared to the scan pulse Vout_R from the register SR.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The liquid crystal display device according to the present invention as described above has the following effects.

In the present invention, by reducing the channel length of the control switching element than the channel length of the pixel switching element, it is possible to reduce the size of the liquid crystal panel and to improve the output characteristics through the on-current gain.

Claims (17)

  1. A liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines;
    A shift register embedded in the liquid crystal panel and outputting a scan pulse for driving the gate lines;
    A plurality of control switching elements provided in the shift register to control an output of the shift register;
    A pixel switching element provided in the pixel region, for switching a data signal from the data line in response to a scan pulse from the gate line and supplying the data signal to a pixel electrode of the pixel region;
    And a channel length of the pixel switching element and a channel length of the at least one control switching element are different from each other.
  2. The method of claim 1,
    And a channel length of at least one control switching element is smaller than a channel length of the pixel switching element.
  3. The method of claim 2,
    And the channel length of the control switching element is between 1% and 50% of the channel length of the pixel switching element.
  4. The method of claim 1,
    The shift register includes a plurality of stages for outputting the scan pulse;
    Each stage said,
    An enabling node;
    A pull-up switching device configured to output the scan pulse according to a logic state of the enable node;
    At least two nodes for disabling;
    At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage source according to a logic state of each of the disable nodes; And,
    And a node controller for controlling a logic state of an enable node and a disable node, and a logic state of a disable node included in a stage different from itself.
  5. The method of claim 4, wherein
    And a channel length of the pull-up switching element is smaller than a channel length of the pixel switching element.
  6. The method of claim 4, wherein
    Each stage includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and a second pull-down switching element connected to the second disable node. Including;
    The node controller provided in the 2n-3 (n is a natural number of 2 or more) stages controls the logic states of the enable node and the first disable node provided in the 2n-3th stage, To control the logic state of the first disable node provided in the stage,
    The node controller provided in the 2n-2th stage controls the logic states of the enable node and the second disable node included in the 2n-2nd stage, and the second control unit provided in the 2n-2nd stage. 1 A liquid crystal display device controlling the logic state of a node for disabling.
  7. The method of claim 6,
    The first disable node provided in the 2n-3rd stage and the first disable node provided in the 2n-2nd stage are electrically connected to each other,
    And a second disable node provided in the 2n-2 th stage and a second disable node provided in the 2n-3 th stage are electrically connected to each other.
  8. The method of claim 6,
    The node control unit provided in the 2n-3rd stage is configured to determine a logic state of the first disable node provided in the 2n-3rd stage and a logic state of the first disable node provided in the 2n-2nd stage. Controlled by the first AC voltage source,
    The node controller provided in the 2n-2th stage is configured to determine a logic state of a second disable node provided in the 2n-2nd stage and a second disable node provided in the 2n-3rd stage. A liquid crystal display device characterized by controlling with a second alternating current voltage source having a phase inverted with respect to one alternating current voltage source.
  9. The method of claim 6,
    The 2n-1st stage and the 2nth stage are enabled in response to the scan pulses from the 2n-2th stage and are disabled in response to the scan pulses from the 2n + 1th stage,
    2n-3nd stage and 2n-2nd stage are disabled in response to the scan pulse from the 2n-1st stage, and
    And the 2n + 1th stage and the 2n + 2th stage are enabled in response to the scan pulse from the 2nth stage.
  10. The method of claim 9,
    The node controller provided in the 2n-1th stage is
    A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-2th stage;
    A second switching device configured to discharge the enable node to a second DC voltage source in response to a first AC voltage source supplied to a first disable node;
    A third switching for discharging the enable node of the 2n-1st stage to the second DC voltage source in response to a second AC voltage source supplied to the second disable node of the 2n-1st stage through a 2nth stage; device;
    A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage;
    A fifth switching device that is turned on or turned off in response to a first AC voltage source and charges a common node with the first AC voltage source when turned on;
    A sixth switching device discharging the common node to a second DC voltage source in response to a first DC voltage source charged in the enable node;
    A seventh switching element configured to charge the first disabling node of the 2n-1st stage and the first disabling node of the 2nth stage with the first AC voltage source in response to the first AC voltage source supplied to the common node; ;
    An eighth switching element configured to discharge the first disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to a scan pulse from the 2n-2th stage;
    A ninth switching for discharging the first disabling node of the 2n-1st stage and the first disabling node of the 2nth stage to a second DC voltage source in response to the first DC voltage source charged in the enable node; device;
    A tenth switching device configured to discharge the common node to a second DC voltage source in response to a start pulse from an external device; And,
    And an eleventh switching element which is turned on or off in response to the first AC voltage source and discharges the second disable node to a second DC voltage source when turned on. .
  11. The method of claim 10,
    The node controller provided in the 2nth stage is
    A first switching device configured to charge an enabling node with a first DC voltage source in response to a scan pulse from the 2n-2th stage;
    A second switching device discharging the enable node of the 2nth stage to a second DC voltage source in response to the first AC voltage source supplied to the first disable node of the 2nth stage through the 2n-1st stage;
    A third switching device configured to discharge the enable node to a second DC voltage source in response to a second AC voltage source supplied to a second disable node;
    A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage;
    A fifth switching device which is turned on or off in response to a second AC voltage source and charges a common node with the second AC voltage source when turned on;
    A sixth switching device discharging the common node to a second DC voltage source in response to a first DC voltage source charged in the enable node;
    A seventh switching element configured to charge the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage with the second AC voltage source in response to a second AC voltage source supplied to the common node. ;
    An eighth switching element for discharging the second disable node of the 2n th stage and the second disable node of the 2n-1 th stage to a second DC voltage source in response to a scan pulse from the 2n-2 th stage; ;
    A ninth switching for discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; device;
    A tenth switching device configured to discharge the common node to a second DC voltage source in response to a start pulse from an external device; And,
    And an eleventh switching element which is turned on or turned off in response to the second alternating current voltage source and discharges the second disable node to a second direct current voltage source at turn-on time. .
  12. The method of claim 11,
    The control switching devices may include the pull-up switching device, the first pull-down switching device, the second pull-down switching device, the first to eleventh switching elements provided in the 2n-th stage, and the pull-up provided in the 2n-1th stage. A switching element, a first pull-down switching element, a second pull-down switching element, and first to eleventh switching elements;
    And a channel length of each switching element included in the control switching elements is smaller than a channel length of the pixel switching element.
  13. The method of claim 12,
    And a channel length of each switching element included in the control switching elements is between 1% and 50% of the channel length of the pixel switching element.
  14. The method of claim 11,
    The control switching devices may include the pull-up switching device, the first pull-down switching device, the second pull-down switching device, the first to eleventh switching elements provided in the 2n-th stage, and the pull-up provided in the 2n-1th stage. A switching element, a first pull-down switching element, a second pull-down switching element, and first to eleventh switching elements;
    And a channel length of the pull-up switching element provided in the 2n-1th stage is smaller than the channel length of the pixel switching element.
  15. The method of claim 14,
    And a channel length of the pull-up switching device provided in the 2n-1th stage is between 1% and 50% of the channel length of the pixel switching device.
  16. The method of claim 11,
    The control switching devices may include the pull-up switching device, the first pull-down switching device, the second pull-down switching device, the first to eleventh switching elements provided in the 2n-th stage, and the pull-up provided in the 2n-1th stage. A switching element, a first pull-down switching element, a second pull-down switching element, and first to eleventh switching elements;
    A first switching device provided in the 2n-1st stage, a first switching device provided in the 2nth stage, a fifth switching device provided in the 2n-1st stage, and a fifth switching device provided in the 2nth stage The channel length of any one of the device, the seventh switching device provided in the 2n-1st stage, and the seventh switching elements provided in the 2nth stage is smaller than the channel length of the switching device for the pixel. LCD display device.
  17. The method of claim 16,
    A first switching device provided in the 2n-1st stage, a first switching device provided in the 2nth stage, a fifth switching device provided in the 2n-1st stage, and a fifth switching device provided in the 2nth stage The channel length of any one of the device, the seventh switching device provided in the 2n-1 st stage, and the seventh switching elements provided in the 2n th stage is 1% to 50 with respect to the channel length of the switching device for pixels. A liquid crystal display device having a size between%.
KR1020060137642A 2006-12-29 2006-12-29 A liquid crystal display device KR101327840B1 (en)

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KR1020060137642A KR101327840B1 (en) 2006-12-29 2006-12-29 A liquid crystal display device

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110065823A (en) * 2009-12-10 2011-06-16 엘지디스플레이 주식회사 Liquid crystal display device
KR20150078587A (en) * 2013-12-31 2015-07-08 엘지디스플레이 주식회사 A shift register and method for manufacturing the same, and an image display device using the shift register
US9412315B2 (en) 2011-09-09 2016-08-09 Samsung Display Co., Ltd. Gate driving circuit and display apparatus having the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100853720B1 (en) * 2002-06-15 2008-08-25 삼성전자주식회사 Shift resister for driving amorphous-silicon thin film transistor gate and liquid crystal display device having the same
KR101066493B1 (en) * 2004-12-31 2011-09-21 엘지디스플레이 주식회사 Shift register
KR101127842B1 (en) * 2005-06-13 2012-03-21 엘지디스플레이 주식회사 Shift Register and Liquid Crystal Display Using the Same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110065823A (en) * 2009-12-10 2011-06-16 엘지디스플레이 주식회사 Liquid crystal display device
US9412315B2 (en) 2011-09-09 2016-08-09 Samsung Display Co., Ltd. Gate driving circuit and display apparatus having the same
US10115365B2 (en) 2011-09-09 2018-10-30 Samsung Display Co., Ltd. Gate driving circuit and display apparatus having the same
KR20150078587A (en) * 2013-12-31 2015-07-08 엘지디스플레이 주식회사 A shift register and method for manufacturing the same, and an image display device using the shift register

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