KR20160147089A - Display Device - Google Patents

Abstract

According to the present invention, a display device comprises: a plurality of gate lines connected to pixels by a pixel row unit; and a gate driving unit configured to provide a gate pulse to the gate lines. The gate driving unit comprises a shift register configured to shift the gate pulse by using stages which are dependently connected. An i^th stage of the shift register comprises: a Q node configured to control a pullup transistor; a QB node configured to control a pulldown transistor; and a node control circuit configured to control the Q node and the QB node; and a carry line configured to provide a Q node voltage to a (i+k)^th stage wherein k is a natural number which is i or less.

Description

[0001]

The present invention relates to a display device.

The display device is arranged such that the data lines and the gate lines are orthogonal and the pixels are arranged in a matrix form. Video data voltages to be displayed are supplied to the data lines and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied and all of the display lines are sequentially scanned by the gate pulse to display the video data.

A gate driver for supplying gate pulses to the gate lines of the flat panel display typically includes a plurality of integrated circuits (ICs). Since each of the gate drive ICs must sequentially output gate pulses, it basically includes a shift register and may include circuits and output buffers for adjusting the output voltage of the shift register depending on the driving characteristics of the display panel.

The gate driver may be a combination of thin film transistors in a bezel region which is a non-display region in the display panel, and is also referred to as a gate-in-panel (GIP) type. The GIP circuit includes a stage corresponding to the number of gate lines. Each stage outputs a gate pulse supplied to each gate line. The stage outputs the gate pulse using the output of the front stage as a carry signal.

Recently, the resolution of the display panel is increased and the size of the display panel is becoming larger, and the carry signal connected to the output terminal of the gate pulse may be delayed. The carry signal is delayed and the voltage level of the carry signal is lowered, so that the Q node, which is the output stage control node of the gate pulse, becomes insufficiently charged. If the charging of the Q node is poor, the gate pulse is not normally outputted, resulting in a problem that the charging of data in the pixel becomes poor.

In order to solve the above-described problems, the present invention is to provide a display device capable of improving the charging failure of the Q node.

According to an aspect of the present invention, a display device includes a plurality of gate lines connected to pixels in units of pixel lines, and a gate driver for providing gate pulses to gate lines. The gate driver includes a shift register that shifts the gate pulse using the stages to which it is connected. The i-th stage (i is a natural number) of the shift register includes a Q-node for controlling the pull-up transistor, a QB node for controlling the pull-down transistor, a node control circuit for controlling the voltages of the Q- ) < / RTI > (k is a natural number less than i) th stage.

The display device of the present invention can prevent the carry signal from being delayed by the load of the pixels connected to the output stage because each stage of the gate driver operates by directly receiving the Q node voltage of the previous stage.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a configuration of a display device according to the present invention;
Fig. 2 shows a shift register according to an embodiment; Fig.
3 is a view showing a stage of a shift register according to an embodiment;
4 is a diagram showing a connection structure of carry signals between stages;
5 is a waveform diagram showing input and output signals of a stage;
6 is a view showing a shift register according to a comparative example;
7 is a view showing a problem of a shift register according to a comparative example;
8 is a view showing a shift register according to the second embodiment;
9 is a waveform diagram showing input and output signals of a stage according to the second embodiment;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1 is a block diagram showing a display device according to an embodiment of the present invention. Referring to FIG. 1, the display device of the present invention includes a display panel 100, a timing controller 110, a data driving circuit, and a gate driving circuit 130.

The display panel 100 includes a display region 100A in which subpixels are formed and a non-display region 100B in which various signal lines, pads, and the like are formed outside the display region 100A. A plurality of pixels P are arranged in the display area 100A. The pixel P includes a pixel circuit PC that operates in response to the supplied data signal DATA corresponding to the scan signal supplied through the switching element SW connected to the gate line GL and the data line DL . The pixel circuit PC and the switching element SW may be implemented in different forms depending on the type of the display panel.

The timing controller 110 receives timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a main clock MCLK from the host computer through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 110 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the gate drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 120 and the polarity of the data voltage.

The scan timing control signal includes a gate start pulse VST, a gate clock CLK, a rear stage signal NEXT, and the like. The gate start pulse VST is input to the shift register 130 to control the shift start timing. The gate clock CLK is level-shifted through the level shifter 130 and then input to the shift register 140. The trailing edge signal NEXT initializes each node of the shift register 140 after the shift register 140 outputs the gate pulse Gout.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 120. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 120 based on the rising or falling edge.

The data driving circuit includes a plurality of source drive ICs 120. [ Each source drive IC 120 receives digital video data (RGB) from the timing controller 110. The source driver IC 120 converts the digital video data RGB to a gamma compensation voltage in response to the source timing control signal from the timing controller 110 to generate a data voltage and synchronize the data voltage with the gate pulse To the data lines of the display panel 100.

The gate driving circuit includes a level shift 130 and a shift register 140.

The level shifter 130 level shifts the transistor-transistor-logic (TTL) logic level voltage of the gate clocks CLK input from the timing controller 110 to the gate high voltage VGH and the gate low voltage VGL . The level shifter 130 may be mounted on the PCB 105.

The shift register 140 is composed of stages for shifting the start pulse VST or the carry signal Qout in accordance with the gate clocks CLK and sequentially outputting the gate pulse Gout. The shift register 140 may be implemented as a GIP circuit in the display panel 100. [

Since the shift register 140 uses the Q node voltage of the front stage directly as the carry signal Qout, the carry signal Qout is delayed and improves the smooth pre-charging . A detailed description thereof will be described later.

2 is a view showing a shift register 140 according to the present invention.

Referring to FIG. 2, the gate shift register 140 according to the present invention includes first through n-th stages ST1 through STn which are connected in a dependent manner. The i-th (i is a natural number equal to or smaller than n) stage STi outputs the i-th gate pulse Gouti. The ith gate pulse Gouti is provided to the pixels arranged in the i-th pixel row.

In the following description, the term "front stage" means that the stage is located at the upper portion of the reference stage. For example, based on the i-th stage STi, the front stage designates any one of the first stage ST1 to the (i-1) th stage ST (i-1). Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, based on the i-th stage STi, the trailing stage designates any one of the (i + 1) th stage ST [i + 1] to the nth stage ST [n].

Fig. 3 is a block diagram showing a configuration of a stage i (i is a natural number 2 <i <n) in Fig. 2, and Fig. 4 is a diagram showing a carry signal connection between i-stage and (i + 1) stages.

3 and 4, the i-th stage STi includes a node control circuit (NCON) and an output portion 145. [

The node control circuit (NCON) receives the gate timing control signal to control the Q node (Q) and the QB node (QB). The node control circuit 141 includes a charge control transistor T1, an auxiliary control circuit 143, and a discharge control transistor T2.

The charge control transistor T1 includes a first electrode coupled to the gate high voltage (VGH) input, a second electrode coupled to the Q node Q, and a gate electrode coupled to the carry line 149 of the front stage. The charge control transistor T1 charges the Q node Q with the gate high voltage VGH based on the carry signal Qout supplied through the carry line 149. [ The first electrode may be connected to the gate high voltage (VGH) input terminal in addition to the high potential voltage source.

The charge control transistor Tl of the first stage STG1 operates by receiving the start pulse VST instead of the previous single stage carry signal.

The auxiliary control circuit 143 is directly or indirectly connected to the Q node Q and the QB node to initialize or stabilize the voltage of the Q node Q or the voltage of the QB node QB. The auxiliary control circuit 143 may be a combination of transistors and may be implemented by selectively applying a known technique. For example, the auxiliary control circuit 143 may add a transistor responsive to the downstream signal NEXT and use it to initialize the voltage of the Q node QB or QB node QB. And the rear stage signal NEXT can use the gate pulse of the rear stage.

The discharge control transistor T2 includes a first electrode connected to the QB node QB, a second electrode connected to the low potential voltage (VSS) input terminal, and a gate electrode receiving the gate pulse of the front stage. The discharge control transistor T2 discharges the voltage of the QB node QB to the low potential voltage VSS in response to the gate pulse of the front stage.

The output unit 145 outputs the gate pulse Gouti provided to the i-th pixel row. The output section 145 includes a pull-up transistor Tpu and a pull-down transistor Tpd. A gate electrode of the pull-up transistor Tpu is connected to the Q node Q, a first electrode thereof is connected to the gate clock CLK, and a second electrode thereof is connected to the output terminal A. The gate electrode of the pull-down transistor Tpd is connected to the QB node QB, the electrode is connected to the output terminal A, and the second electrode is connected to the low potential voltage (VSS) input terminal.

The pull-up transistor Tpu is turned on when the Q node Q is at the high level voltage, and outputs the gate clock CLK supplied from the first electrode to the gate pulse Gouti. The pull-down transistor Tpd is turned on when it is the high level voltage of the QB node QB and discharges the voltage of the output terminal A to the low potential voltage VSS.

The carry line 149 provides the voltage of the Q node Q to the charge control transistor T1 of the following stage STG [i + k] (k is a natural number less than i).

5 is a diagram showing a waveform for driving the shift register of the present invention and an output waveform of the node control circuit according to the waveform. Referring to FIG. 5, the driving method of the present invention will be described as follows. The operation of the shift register will be described focusing on the operation of the first stage STG1 receiving the start pulse VST and the second stage receiving the carry signal Qout1 from the first stage STG2.

During the first period t1, the start pulse VST maintains the turn-on voltage of the charge control transistor T1. When the charge control transistor T1 is an n-type transistor as shown in Figs. 3 and 4, the start pulse VST maintains a high level voltage. The start pulse VST is provided to the charge control transistor Tl of the first stage. The charge control transistor T1 of the first stage is turned on by the start pulse VST during the first period t1 to charge the Q node Q with the high potential voltage VGH supplied from the first electrode do.

During the second period t2, the pull-up transistor Tpu of the output section 145 receives the gate clock CLK. The second period t2 may be set to be equal to or greater than one horizontal period. The high level voltage of the gate clock CLK can use the high potential voltage VDD or the gate high voltage VGH of the constant potential.

During the second period t2, the voltage level of the first electrode of the pull-up transistor Tpu is increased by the gate clock CLK, and the voltage level of the first electrode of the gate electrode of the pull-up transistor Tpu is increased, And is bootstrapped. As described above, in the process of bootstrapping the gate electrode of the pull-up transistor Tpu, the pull-up transistor Tpu is turned on when the gate-source voltage reaches the threshold voltage Vth. As the pull-up transistor Tpu is turned on, the gate clock CLK provided through the electrode outputs the gate pulse Gout1 through the output terminal A.

At the end of the second period t2, the gate clock CLK is inverted to the low level, and accordingly, the voltage of the output stage A becomes the low potential level. As the pull-up transistor Tpu discharges the voltage at the output terminal A, the voltage of the bootstrapped gate electrode during the first period t1 decreases.

During the third period t3, the auxiliary control circuit 143 of the node control circuit 141 receives the following signal NEXT. The auxiliary control circuit 143 operates based on the following stage signal NEXT to initialize the Q node Q and the QB node QB. And the rear stage signal NEXT can use the gate pulse of the rear stage.

The Q node Q of each stage is connected to the charge control transistor Tl of the subsequent stage through the carry line 149. [ That is, the charge control transistor Tl of the subsequent stage directly receives the voltage of the Q node Q of the previous stage. Therefore, the charge control transistor T1 of the second stage STG2 receives the voltage of the Q node Q of the first stage STG1 as the carry signal Qout1. Likewise, the charge control transistor T1 included in the stage after the third stage receives the Q node (Q) voltage of the previous stage as the carry signal Qout. As described above, the charge control transistor T1 of i (i is a natural number smaller than or equal to 2 and less than n) th stage STGi receives the Q node Q voltage of the previous stage STG [i-1] as the carry signal Qout, The delay of the carry signal due to the panel load can be improved. Since the first voltage level V1 charged in the Q node Q has a voltage level higher than the second voltage level V2 of the gate high voltage VGH, the voltage level of the carry signal Qout becomes high. The principle of improving the charging characteristic by charging the Q node Q using the carry signal Qout having a high voltage level is as follows.

When the Q node Q is to be charged to the gate high voltage during the first period t1, the Q node Q actually corresponds to the difference between the gate potential Vg and the threshold voltage Vth of the charge control transistor The voltage is charged. Since the charge control transistor T1 of the comparative example receives the gate pulse having the voltage of the gate high voltage, the Q node Q becomes the voltage corresponding to the magnitude of the "gate high voltage-threshold voltage". As a result, in the comparative example, the charge of the Q node is insufficient. Particularly, in a shift register using the gate pulse Gout as a carry signal, such a problem is conspicuous due to the delay of the carry signal.

6 is a view showing a shift register of a comparative example as compared with the shift register of the present invention. Referring to FIG. 6, the rear stage NEXT receives the gate pulse Gout of the front stage as a carry signal. When the resolution of the display panel is increased and the panel size is enlarged, the output of the gate pulse Gout is delayed as shown in FIG. 7 due to the load of a plurality of transistors included in the pixels. For example, assuming that the output of the ideal gate pulse Gout is "Vgout1 ", the gate pulse is delayed in the form of" Vgout2 " Since the shift register according to the comparative example shown in Fig. 6 uses the gate pulse Gout of the front stage as the carry signal, the carry signal is also delayed as the gate pulse Gout is delayed. In this comparative example, a charging waveform such as "Qout2" having a lower voltage than the ideal Q node Q charging waveform such as "Qout1 " appears because of the delay of the carry signal and the voltage level of the carry signal. If the charging of the Q node Q is not performed smoothly, the output voltage of the gate pulse Gout becomes low, and as a result, data is not charged smoothly in the pixel.

On the other hand, since the shift register 140 according to the present invention uses the Q node voltage of the front stage directly as a carry signal, the delay of the carry signal due to the load of the pixel transistors connected to the output stage A can be improved have. In addition, since the carry signal has a voltage level higher than the gate high voltage, the charge voltage of the Q node can be increased. Therefore, the shift register 140 according to the present invention can prevent the data charging failure in the pixels by increasing the charging characteristic of the Q node.

FIG. 8 is a diagram showing a carry signal connection between stages according to the second embodiment, FIG. 9 is a diagram showing a waveform for driving the stage shown in FIG. 8 and an output waveform of a main node. The detailed description of the substantially same configuration as the above-described embodiment in the second embodiment will be omitted.

In the second embodiment, the i &lt; th &gt; stage STi includes a node control circuit (NCON) and an output portion 145. [

The node control circuit (NCON) receives the gate timing control signal to control the Q node (Q) and the QB node (QB). The node control circuit 141 includes a charge control transistor T1, an auxiliary control circuit 143, and a discharge control transistor T2.

The charge control transistor T1 includes a first electrode coupled to the Q clock CLK_Q input, a second electrode coupled to the Q node Q, and a gate electrode coupled to the carry line 149 of the front stage. The charge control transistor T1 charges the Q node Q when the Q clock CLK_Q is at the high level voltage based on the carry signal Qout provided through the carry line 149. [

The charge control transistor Tl of the first stage STG1 operates by receiving the start pulse VST instead of the previous single stage carry signal.

The auxiliary control circuit 143 is directly or indirectly connected to the Q node Q and the QB node to initialize or stabilize the voltage of the Q node Q or the voltage of the QB node QB.

The discharge control transistor T2 includes a first electrode connected to the QB node QB, a second electrode connected to the low potential voltage (VSS) input terminal, and a gate electrode receiving the gate pulse of the front stage. The discharge control transistor T2 discharges the voltage of the QB node QB to the low potential voltage VSS in response to the gate pulse of the front stage.

The output unit 145 outputs the gate pulse Gouti provided to the i-th pixel row. The output section 145 includes a pull-up transistor Tpu and a pull-down transistor Tpd.

The carry line 149 provides the voltage of the Q node Q to the charge control transistor T1 of the following stage STG [i + k] (k is a natural number less than i).

The operation of the shift register will be described with reference to the operations of the first stage STG1 receiving the start pulse VST and the second stage receiving the carry signal Qout1 from the first stage STG2.

During the first period t1, the start pulse VST maintains the turn-on voltage of the charge control transistor T1. When the charge control transistor T1 is an n-type transistor as shown in Figs. 3 and 4, the start pulse VST maintains a high level voltage. The start pulse VST is provided to the charge control transistor Tl of the first stage. During the first period T1, the Q clock CLK_Q is inverted to a high level voltage. The charge control transistor T1 of the first stage is turned on by the start pulse VST during the first period t1 and charges the Q node Q with the Q clock CLK_Q supplied from the first electrode .

During the second period t2, the pull-up transistor Tpu of the output section 145 receives the gate clock CLK. The second period t2 may be set to be equal to or greater than one horizontal period. During the second period t2, the voltage level of the first electrode of the pull-up transistor Tpu is increased by the gate clock CLK, and the voltage level of the first electrode of the gate electrode of the pull-up transistor Tpu is increased, And is bootstrapped. As described above, in the process of bootstrapping the gate electrode of the pull-up transistor Tpu, the pull-up transistor Tpu is turned on when the gate-source voltage reaches the threshold voltage Vth. As the pull-up transistor Tpu is turned on, the gate clock CLK provided through the electrode outputs the gate pulse Gout1 through the output terminal A.

At the end of the second period t2, the gate clock CLK is inverted to the low level, and accordingly, the voltage of the output stage A becomes the low potential level. As the pull-up transistor Tpu discharges the voltage at the output terminal A, the voltage of the bootstrapped gate electrode during the first period t1 decreases.

During the third period t3, the auxiliary control circuit 143 of the node control circuit 141 receives the following signal NEXT. The auxiliary control circuit 143 operates based on the following stage signal NEXT to initialize the Q node Q and the QB node QB. And the rear stage signal NEXT can use the gate pulse of the rear stage.

The Q node Q of each stage is connected to the charge control transistor Tl of the subsequent stage through the carry line 149. [ That is, the charge control transistor Tl of the subsequent stage directly receives the voltage of the Q node Q of the previous stage.

As described above, the charge control transistor T1 of i (i is a natural number smaller than or equal to 2 and less than n) th stage STGi receives the Q node Q voltage of the previous stage STG [i-1] as the carry signal Qout, The delay of the carry signal due to the panel load can be improved. Since the first voltage level V1 charged in the Q node Q has a voltage level higher than the second voltage level V2 of the gate high voltage VGH, the voltage level of the carry signal Qout becomes high.

As shown in the first and second embodiments, the first electrode of the charge control transistor T1 receives a constant voltage such as a gate high voltage VGH or a high potential voltage VDD, or a constant voltage such as a Q clock CLK_Q A clock signal can be input. The voltage input to the charge control transistor T1 may be selected in accordance with the auxiliary control circuit 143. [

In the first and second embodiments, the carry line of the i &lt; th &gt; stage has mainly described the transfer of the carry signal to the (i + 1) -th stage. The connection structure of the carry line is not limited to this and can be implemented in various embodiments. For example, the carry line may transmit the Q-node voltage of the i-th stage to (i + k) (k is a natural number less than i) stage. The connection structure of the stages can be selected in accordance with the node control circuit 141 and the auxiliary control circuit 143. [

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display panel 110: timing controller
120: Data driver 130: Level shifter
140: shift register 149: carry line

Claims (6)

A plurality of gate lines connected to pixels in unit pixel lines; And
A gate driver for providing a gate pulse to the gate line,
Wherein the gate driver includes a shift register that shifts the gate pulse using the stages connected thereto,
The i (i is a natural number) stage of the shift register is
A Q node for controlling a pull-up transistor;
A QB node for controlling a pull-down transistor;
A node control circuit for controlling voltages of the Q node and the QB node; And
And a carry line for providing the Q node voltage to (i + k) (k is a natural number less than i) th stage. The method according to claim 1,
The node control circuit
A first electrode coupled to the high potential source, a second electrode coupled to the Q node, and a charge control transistor coupled to the carry line of the previous stage. The method according to claim 1,
The node control circuit
And a discharge control transistor including a first electrode connected to the QB node, a second electrode connected to a low potential voltage source, and a gate electrode receiving a gate pulse of the front stage. 3. The method of claim 2,
Wherein the charge control transistor is operated by the Q node voltage supplied from the carry line to precharge the high potential voltage to the Q node. 5. The method of claim 4,
And the gate clock is applied as a voltage for operating the pull-up transistor after the charge control transistor is turned off. 6. The method of claim 5,
And when the pull-up transistor is operated by the gate clock, the precharged Q node is bootstrapped to a voltage higher than the voltage level of the high potential voltage.

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